CN101271843A - Production method for reducing wafer defect - Google Patents
Production method for reducing wafer defect Download PDFInfo
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- CN101271843A CN101271843A CNA2007100382222A CN200710038222A CN101271843A CN 101271843 A CN101271843 A CN 101271843A CN A2007100382222 A CNA2007100382222 A CN A2007100382222A CN 200710038222 A CN200710038222 A CN 200710038222A CN 101271843 A CN101271843 A CN 101271843A
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- wafer
- etching
- reative cell
- silicon nitride
- nitride layer
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Abstract
The invention provides a manufacturing method used for reducing the defects of wafers, comprising the steps that: a. an etching machine station is provided, which is provided with a reaction chamber which is provided with the wafer to be disposed; b. the voltage of the etching machine station is turned on, and an electrical field is generated in the reaction chamber to carry out the etching operation to the wafer; c. a pumping device which is communicated with the reaction chamber is provided, a certain electrical field in the reaction chamber is maintained after the etching operation is completed, and the pumping operation is carried out by pumping in large-flux inert gases which are not participated in the reaction at the same time. Compared with the prior art, the manufacturing method of the invention increases a pumping step after the etching operation is complete, thus the possibility that the surface of the wafer is polluted by the impurities in the reaction chamber and the generation of wafer defects is reduced.
Description
Technical field
The present invention relates to a kind of process for fabrication of semiconductor device, specifically, relate to a kind of manufacture method that in etch process, can reduce wafer defect.
Background technology
In fabrication of semiconductor device, etch process is an extremely important step.Adopt electricity slurry physics formula bump because dry etching is an electric paste etching (plasma etching), be anisotropic etching, can obtain good size Control, can realize the conversion of trickle figure, so electric paste etching is widely adopted at present.
When carrying out etching, in the reative cell (chamber) of the etching machine that processed object wafer (wafer) is placed on.Wafer has Semiconductor substrate such as silicon substrate and is deposited on silicon nitride layer and polysilicon layer as grid above the silicon substrate.As a rule, it is uneven needing etched pattern density, and therefore when at first silicon nitride layer being carried out etching, the zone that pattern density is low will be subjected to very big pressure, causes the distortion of silicon nitride layer easily, and the part silicon nitride layer is squeezed bad when serious.Under the electric field action of etching machine, squeeze the particle matter that bad silicon nitride layer produces a large amount of suspensions.After the etching of silicon nitride layer is finished, close etching machine voltage, the electric field of reative cell disappears, and the particle matter of suspension will drop on the surface of wafer, and polluting wafer causes the blemish of wafer.Finish behind the silicon nitride layer etching step, need further polysilicon to be carried out etching step.Back falls particle matter at crystal column surface to be caused in the etching step at polysilicon the incomplete phenomenon of etching taking place, and has had a strong impact on the qualification rate that wafer is made.
A kind of manufacture method of reduced wafer defect newly need be provided in view of the foregoing.
Summary of the invention
The technical problem that the present invention solves provides a kind of manufacture method that reduces wafer defect.
For solving the problems of the technologies described above, the invention provides a kind of manufacture method that reduces wafer defect, it comprises the steps: that a. provides etching machine, and this etching machine has reative cell, and pending wafer is placed in the reative cell; B. connect the voltage of etching machine, produce electric field in the reative cell, wafer is carried out etching step; C., the air extractor that communicates with reative cell is provided, after etching finishes, keeps the certain electric field of reative cell, feed simultaneously and do not participate in the big flow inert gas that reacts, carry out pump step.
Compared with prior art, manufacture method of the present invention increases pump step behind etching step, has reduced the possibility of the contaminating impurity crystal column surface in the reative cell, has improved the qualification rate that wafer is made.
Description of drawings
To the description of one embodiment of the invention, can further understand purpose, specific structural features and the advantage of its invention by following in conjunction with its accompanying drawing.Wherein, accompanying drawing is:
Fig. 1 reduces the flow chart of the manufacture method of wafer defect for the present invention.
Embodiment
See also Fig. 1, the invention discloses a kind of manufacture method that reduces wafer defect, it comprises the steps: that a. provides etching machine, and it has reative cell, and pending wafer is placed in the reative cell; B. open the voltage of etching machine, produce electric field in the reative cell, wafer is carried out etching step; C., the air extractor that communicates with reative cell is provided, after etching finishes, keeps the certain electric field of reative cell, feed simultaneously and do not participate in the big flow inert gas that reacts, carry out pump step.
Wafer generally comprises the grid of Semiconductor substrate such as silicon substrate and deposition formation on Semiconductor substrate, and grid comprises the silicon nitride layer on upper strata and the polysilicon layer of lower floor.The described etching step of above-mentioned steps b is that the silicon nitride layer at the grid of wafer carries out etching step, is easy to generate the impurity such as the particle matter on polluting wafer surface in this step, and under the reative cell effect of electric field, is suspended in the reative cell.Through above-mentioned steps c the impurity in the reative cell is taken away, avoid the electric field of reative cell to disappear after, impurity drops on crystal column surface, the polluting wafer surface.Simultaneously, also reduced effectively and the incomplete phenomenon of etching in the step of ensuing etching polysilicon layer, occurred.Manufacture method disclosed by the invention has reduced the defective that wafer produces effectively in etch process, improved the qualification rate of wafer.
Claims (3)
1. manufacture method that reduces wafer defect, it comprises the steps: that a. provides etching machine, and this etching machine has reative cell, and pending wafer is placed in the reative cell; B. connect the voltage of etching machine, produce electric field in the reative cell, wafer is carried out etching step; C., the air extractor that communicates with reative cell is provided, it is characterized in that: after etching finishes, keep the certain electric field of reative cell, feed simultaneously and do not participate in the big flow inert gas that reacts, carry out pump step.
2. manufacture method as claimed in claim 1 is characterized in that: described wafer comprises as the silicon nitride layer of grid and is positioned at polysilicon layer below the silicon nitride layer, and step b is that the silicon nitride layer to wafer carries out etching step.
3. manufacture method as claimed in claim 2 is characterized in that: in pump step, reative cell is kept suitable electric field, and the particle matter that is produced in the etches both silicon nitride layer process is taken away by the gas that big flow does not participate in reacting.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100382222A CN100547742C (en) | 2007-03-20 | 2007-03-20 | Reduce the manufacture method of wafer defect |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100382222A CN100547742C (en) | 2007-03-20 | 2007-03-20 | Reduce the manufacture method of wafer defect |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101271843A true CN101271843A (en) | 2008-09-24 |
| CN100547742C CN100547742C (en) | 2009-10-07 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2007100382222A Active CN100547742C (en) | 2007-03-20 | 2007-03-20 | Reduce the manufacture method of wafer defect |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100547742C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102249179A (en) * | 2010-05-20 | 2011-11-23 | 上海华虹Nec电子有限公司 | Dry etching method for improving profile angle of micro-electro-mechanical system (MEMS) sensing film cavity |
| CN102931074A (en) * | 2012-10-18 | 2013-02-13 | 上海宏力半导体制造有限公司 | Forming method of semiconductor structure |
-
2007
- 2007-03-20 CN CNB2007100382222A patent/CN100547742C/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102249179A (en) * | 2010-05-20 | 2011-11-23 | 上海华虹Nec电子有限公司 | Dry etching method for improving profile angle of micro-electro-mechanical system (MEMS) sensing film cavity |
| CN102931074A (en) * | 2012-10-18 | 2013-02-13 | 上海宏力半导体制造有限公司 | Forming method of semiconductor structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100547742C (en) | 2009-10-07 |
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| C06 | Publication | ||
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING |
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| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20111117 Address after: 201203 No. 18 Zhangjiang Road, Shanghai Co-patentee after: Semiconductor Manufacturing International (Beijing) Corporation Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: 201203 No. 18 Zhangjiang Road, Shanghai Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |