CN101268924B - Electronic endoscope device - Google Patents
Electronic endoscope device Download PDFInfo
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- CN101268924B CN101268924B CN2008100877569A CN200810087756A CN101268924B CN 101268924 B CN101268924 B CN 101268924B CN 2008100877569 A CN2008100877569 A CN 2008100877569A CN 200810087756 A CN200810087756 A CN 200810087756A CN 101268924 B CN101268924 B CN 101268924B
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Abstract
An electronic endoscope device where use efficiency of a circuit of a control section can be increased and also operational reliability of the circuit can be improved. The electronic endoscope device has a plurality of exclusively executed operation modes. A CPU (10) and a peripheral circuit are constructed inside the device, and the device has an FPGA (1) for controlling execution of the operation modes and also has a changeover request detecting section for detecting a changeover request of an operation mode to be executed. An internal construction of the FPGA (1) is changed based on the result of detection by the changeover request detecting section.
Description
The application be that on 06 21st, 2006, application number are 200610082948.1 the applying date, denomination of invention divides an application for the application of " electronic endoscope apparatus ".
Technical field
The present invention relates to a kind of electronic endoscope apparatus.
Background technology
In recent years, thus extensively utilize as armarium and to observe in the body cavity internal organs etc. or use as required and insert the endoscope apparatus that the treatment apparatus in the treatment apparatus passage can carry out various metacheirisises.In addition, in industrial field, in the defective of observing, check thin diameter tube inside such as boiler, turbine, electromotor, chemical plant or corrosion, be extensive use of technoscope.
Endoscope apparatus is mainly by constituting as the lower part: light supply apparatus, irradiating illumination light; The insertion section is in the insertion body cavity, in the thin diameter tube; Operating portion carries out bending operation to the insertion section.From the operating portion to the insertion section, dispose to the insertion section front end transmit the fibre-optic bundle etc. of illumination light the illumination light delivery unit, transmit the observation optical transport unit that obtains by irradiating illumination light from the image orientation of the light of subject etc.In addition, operating portion is provided with to be used to detect by an unaided eye and incides the connecting portion etc. of the light supply apparatus of photoconduction etc. by what image orientation was transmitted from the eyepiece portion of the light of subject and with the illumination light that is used to make regulation.
In addition, as disclosed in the TOHKEMY 2005-103325 communique, following endoscope apparatus also is developed, practicability: this endoscope apparatus is at front end, the image orientation end configuration solid-state imager of operating portion, for example CCD of insertion section, the light from look-out station of the illumination light that will penetrate from photoconduction, by objective lens optical system at shooting surface imaging and convert the signal of telecommunication to, this signal of telecommunication is carried out signal processing, thereby can on monitor etc., show the electronic image of look-out station.
In the electronic endoscope apparatus that uses as armarium, device breaks down or takes place under the unusual situation in medical treatment, guarantees when medical treatment is carried out in requirement that required MIN function moves.Therefore, in electronic endoscope apparatus, by the action that is used to carry out common medical treatment, be provided with action pattern, according to from the pattern indication of outside, the situation of device etc., switching motion pattern in the different action of contents processings such as action that device is inner when breaking down.In addition, by a plurality of action patterns are set, each action pattern can be checked the action of other action patterns, owing to can confirm before the switching motion pattern whether the action pattern that will change normally moves, thereby also have the advantage that improves safety.
In the control part of electronic endoscope apparatus, be provided with various setting values that are used for basis input in advance or the various circuit of indicating the control device each several part from the operation of outside, but owing to the circuit difference of using according to action pattern, therefore the circuit that uses when the switching motion pattern also is converted.In existing electronic endoscope apparatus, as shown in Figure 6, prepare and CPU is installed or moves required peripheral circuit by each action pattern.Fig. 6 is the block diagram of structure of the control part of the existing electronic endoscope apparatus of explanation.For example, as shown in Figure 6, being set with, in control part, be provided with the CPU100 and peripheral circuit 101 and CPU102 that under safety is guaranteed pattern, uses and the peripheral circuit 103 that under normal mode, use as the common use pattern of the action pattern that is used to carry out common medical treatment with as guaranteeing under the situation of two action patterns of pattern in the safety of the action pattern that device is inner when fault has taken place.
In above-mentioned electronic endoscope apparatus,, there is substrate area to become big problem realizing under the situation of these action patterns a plurality of CPU100,102, peripheral circuit 101,103 being installed on substrate on the substrate.In addition owing to be not to carry out a plurality of action patterns simultaneously, therefore use pattern usually carrying out during do not use CPU102 and peripheral circuit 103, safety guarantee that pattern carrying out during do not use CPU100 and peripheral circuit 101.Therefore, the problem that also has the service efficiency reduction of circuit.
As the method that addresses this problem, can consider following method: summarize can be shared circuit, use jointly under each action pattern as common circuit, the packing density of circuit is carried out densification, thereby dwindles circuit scale, improve the service efficiency of circuit.But, circuit that uses under each action pattern and common circuit are disposed at isolating position on substrate, perhaps need to cut off under the situation of under other action patterns, using circuit, it is complicated that signal path becomes, even can summarize common circuit in logic, also has the problem of the difficulty of installing physically.In addition, there are the following problems: when improving the packing density of circuit, can not sufficiently obtain the gap between holding wire or between circuit, so holding wire each other or the parts probability that causes short circuit, misoperation takes place that contacts with each other uprise, cause reliability to reduce.
In addition, in such electronic endoscope apparatus, be provided with and be used for according to the various setting values of input in advance or from the operation indication of outside, the controller at each position of control device.Field programmable gate array), CPLD (ComplexProgrammable Logic Device: constitute under the situation of controller CPLD) etc. by CPU (central arithmetic processing apparatus), FPGA (Field ProgrammableGate Array:, operated by rotary motion anomaly monitoring unit, this anomaly monitoring unit has: detecting unit out of control, detect the out of control of controller; Reset unit in order to prevent to bring destruction for the equipment of controlling by controller action out of control, detecting under the controller situation out of control, resets controller, and initialization is carried out in action.
As the anomaly monitoring unit, WatchDog Timer (watch dog timer) is widely known by the people and is commonly used.WatchDog Timer directly is connected with the controller of monitored object, for whether supervisory controller is carrying out regular event, controller control output end mouth, supervision is used for the pulse signal of zero clearing with the specified period of the intervalometer of software realization, thereby when controller become unusual operating state and can not output pulse signal, during fixing not under the situation of impulsing, to controller output reset signal.Time-out period till resetting from the intervalometer zero clearing to output has eigenvalue in each WatchDog Timer, need to select to use the WatchDog Timer that is fit to the controller specification.
But, under the situation of the controller that constitutes fujinon electronic video endoscope by the FPGA that is provided with CPU in inside, CPLD, when the power supply of engaging means, do not begin software initialization, till configuration is finished.Therefore, spended time is wanted in the startup of CPU.Under the situation of having selected time-out period short WatchDog Timer between than the starting period of CPU, do not have output to be used for the pulse signal of specified period of zero clearing intervalometer in the startup of CPU, thus have that output resets in the startup of CPU, device repeats to restart during energized problem.
For fear of this problem, need the WatchDog Timer that uses time-out period longer than the start-up time of CPU.In this case, though can prevent the situation that repeats to restart when above-mentioned CPU starts, under the CPU situation out of control, the timing that begins to reset also postpones in the process of diagnosis or observation.For example, be inserted into when CPU is out of control under the endoceliac state in the insertion section, there is device generation misoperation and injures endoceliac probability, therefore in the medical device headed by the fujinon electronic video endoscope, there be the problem that compare difficulty of the long WatchDog Timer of time-out period of using owing to secure context.
Therefore, in the present invention, a purpose is to provide a kind of service efficiency that can improve the control part circuit, and can improve the electronic endoscope apparatus of the reliability of circuit operation.
In addition, in the present invention,, also can prevent the electronic endoscope apparatus that CPU repeats to restart even another purpose is to provide a kind of use time-out period the WatchDog Timer shorter than the start-up time of CPU.
Summary of the invention
The electronic endoscope apparatus relevant with first mode of the present invention is to carry out the electronic endoscope apparatus with a plurality of action patterns exclusively, this electronic endoscope apparatus possesses the conversion that the conversion of the control part of the execution of control action pattern, action pattern that detect to carry out requires and requires test section, requires the internal structure of the testing result change control part of test section according to conversion.
The electronic endoscope apparatus relevant with second mode of the present invention possesses: controller, when regular event, export first pulse signal; The false pulse generating unit generates second pulse signal; Start and finish test section, detect the startup of controller and finish; Anomaly monitoring signal generating unit is finished the testing result of test section according to startup, and any one of first pulse signal or second pulse signal exported as the anomaly monitoring signal; Abnormity detection portion according to the anomaly monitoring signal, detects the unusual of controller and exports reset signal.
The electronic endoscope apparatus relevant with the present invention, have a plurality of action patterns of being carried out exclusively, it is characterized in that: possess control part, this control part has in internal configurations and the FPGA of CPU and peripheral circuit and/or CPLD is arranged and control the execution of aforementioned activities pattern, according to the aforementioned activities pattern of carrying out, the internal structure difference of aforementioned FPGA and/or aforementioned CPLD.
The electronic endoscope apparatus relevant with the present invention is characterized in that, possesses: controller, output pulse signal when regular event; Start detection of end portion, the startup that detects aforementioned controller finishes; Abnormity detection portion according to aforementioned pulse signal, detects the unusual of aforementioned controller, the output abnormality detection signal; The reset signal generating unit, under the situation that has received aforementioned anomaly detection signal, according to the testing result of aforementioned startup detection of end portion, under the situation that the startup of aforementioned controller finishes, the output reset signal.
Description of drawings
Fig. 1 is the block diagram of structure of the control part of the explanation electronic endoscope apparatus relevant with the 1st embodiment of the present invention.
Fig. 2 is the figure of the internal structure of explanation nonvolatile memory.
Fig. 3 is the block diagram of the circuit structure of the FPGA inside of explanation under common use pattern.
Fig. 4 A is the block diagram of the internal structure of the explanation FPGA relevant with communicating by letter of external equipment with Fig. 4 B, and Fig. 4 A is the block diagram of the internal structure of the FPGA under explanation is dispatched from the factory pattern in factory, and Fig. 4 B is the block diagram that explanation writes the internal structure of the FPGA1 under the pattern.
Fig. 5 is the flow chart of the boot sequence of explanation electronic endoscope apparatus.
Fig. 6 is the block diagram that the structure of the control part that has electronic endoscope apparatus now is described.
Fig. 7 is the block diagram of the structure of the explanation anomaly monitoring portion relevant with the controller of the related electronic endoscope apparatus of the 2nd embodiment of the present invention.
Fig. 8 is the sequential chart of the anomaly monitoring action of explanation CPU when normal the startup.
Fig. 9 is that the sequential chart that the anomaly monitoring when unusual moves takes place in startup explanation CPU.
Figure 10 is the block diagram of the structure of the explanation anomaly monitoring portion relevant with the controller of the related electronic endoscope apparatus of the 3rd embodiment of the present invention.
Figure 11 is the block diagram of the structure of the explanation anomaly monitoring portion relevant with the controller of the related electronic endoscope apparatus of the 4th embodiment of the present invention.
Figure 12 is the block diagram of the structure of the explanation anomaly monitoring portion relevant with the controller of the related electronic endoscope apparatus of the 5th embodiment of the present invention.
The specific embodiment
Embodiments of the present invention are described with reference to the accompanying drawings.
The 1st embodiment
In the 1st embodiment, the situation that is set with following 4 action patterns in electronic endoscope apparatus is described.The electronic endoscope apparatus relevant with present embodiment is the device that can change internal circuit configuration according to action pattern.
First is the action pattern when using electronic endoscope apparatus usually, common use pattern.Under common use pattern, carry out following function: be arranged on the control of the not shown panel on the electronic endoscope apparatus in order to make user's input operation indication, electronic endoscope apparatus is communicated by letter with ancillary equipment, be arranged on lighting of not shown lamp on the electronic endoscope apparatus, extinguish and light modulation, be arranged on the control of the various drive divisions of enclosure interior for each the position action that makes electronic endoscope apparatus, the control of air delivery pump, detect the temperature mistake that the abnormal ascending by the enclosure interior temperature causes by internal error detection portion, the output control (output of buzzer sound and the literal on panel show) of the warning during various drive divisions unusual etc.
Second be when in nonvolatile memory 2 described later, writing data action pattern, write pattern.Writing under the pattern, carrying out following action: the software that writes configuration data (the circuit composition data of FPGA inside), carries out by the CPU10 that is installed in FPGA1 inside to nonvolatile memory 2 from the write device of outside.The 3rd is action pattern, factory when electronic endoscope apparatus carries out inner setting, confirming operation when factory the dispatches from the factory pattern of dispatching from the factory.
The 4th is that the action pattern safety of electronic endoscope apparatus when breaking down is guaranteed pattern.Under safety is guaranteed pattern, when detecting the internal fault of electronic endoscope apparatus, carry out: the lamp on the optical axis of the illumination light of never illustrated light supply apparatus irradiation is lighted guarantees, the action of air delivery pump is guaranteed, to the functions such as mistake demonstration of panel.
The structure of the control part of the electronic endoscope apparatus relevant with embodiments of the present invention at first, is described according to Fig. 1.Fig. 1 is the block diagram of structure of the control part of the explanation electronic endoscope apparatus relevant with embodiments of the present invention.At this, only the part about the action pattern conversion in the control part is described.
As shown in Figure 1, the control part of the electronic endoscope apparatus in the embodiments of the present invention is by constituting as the lower part: and FPGA (Field Programable Gate Array: field programmable gate array) 1, inside has CPU (central processor) 10; Nonvolatile memory 2, preserve the software carried out by the CPU10 that is installed among the FPGA1 and with the corresponding configuration data of action pattern; CPLD (Complex Programmable LogicDevice: compound PLD) 3, the not shown circuit that is used for being loaded into from nonvolatile memory 2 sense datas FPGA1 is installed; Clock generator 4 generates clock signal clk and outputs to FPGA1 and CPLD3; Device interior abnormal detection circuit 5, the internal abnormality of detected electrons endoscope apparatus; Communication I/F equipment 6 is used for communicating with external equipment; And SRAM7.
FPGA1, nonvolatile memory 2 and CPLD3 are electrically connected mutually by address bus 8 and data/address bus 9.As shown in Figure 2, preserve the configuration data of the FPGA1 that under each action pattern, uses and the software of carrying out by CPU10 in the nonvolatile memory 2.
Fig. 2 is the figure of the internal structure of explanation nonvolatile memory 2.For example, as shown in Figure 2, the inside of nonvolatile memory 2 is by piecemeal, in the address is the piece of 0x000000～0x1FFFFF, preserve the software of under use pattern usually, carrying out, in the address is the piece of 0x200000～0x2FFFFF, preserve the configuration data under use pattern usually by CPU10.In addition, in the address is the piece of 0x300000～0x3FFFFF, preserve the software of carrying out by CPU10 under the pattern of writing, in the address is the piece of 0x400000～0x4FFFFF, preserve the configuration data under the pattern of writing.And, in being the piece of 0x500000～0x5FFFFF, the address preserves the software of carrying out by CPU10 under dispatching from the factory pattern in factory, in the address is the piece of 0x600000～0x6FFFFF, preserve in safety and guarantee configuration data under the pattern, in the address is the piece of 0x700000～0x7FFFFF, preserve in safety and guarantee the software carried out by CPU10 under the pattern, in the address is the piece of 0x800000～0x8FFFFF, preserve in safety and guarantee configuration data under the pattern.
Like this, in a nonvolatile memory 2, preserve software and configuration data under whole action patterns, the corresponding configuration data of action pattern, the software that are written into and carry out to FPGA1 from nonvolatile memory 2.And use (exhibition Open The Ru).Specifically, carry out address decoder by the peripheral circuit of the CPU10 of FPGA1, CPLD3 etc., by address bus 8 to nonvolatile memory 2 outputs corresponding with the action pattern of execution read in start address.In nonvolatile memory 2, extract configuration data, software out according to the start address that reads in of input, be loaded into FPGA1, CPLD3 by data/address bus 9.
Though also can when software design, specify and read in start address, but as mentioned above, can carry out address decoder by the peripheral circuit of CPU such as FPGA1, CPLD3, by hardware controls corresponding with each action pattern read in start address, thereby reduce the storage management of being undertaken by software.In addition, address decoder generally is formed in the periphery of CPU10, but also can be formed in FPGA1 inside when constituting CPU10 in the inside of FPGA1 as present embodiment.
Except that reading in start address, also export various control signals to nonvolatile memory 2 from FPGA1 and CPLD3.In addition, between FPGA1 and CPLD3, status signal intercoms mutually.And, transmit to FPGA1 dateout, data from CPLD3 and to use clock signal.In addition, from FPGA1 and device interior abnormal detection circuit 5 to CPLD3 output action pattern switching signal.
In this structure, be written into the configuration data of FPGA1 and the software of CPU10 by CPLD3 and nonvolatile memory 2, but also can realize CPLD3 and nonvolatile memory 2 by an equipment (CPU or configuration device) that satisfies these functions.
Secondly, the circuit structure to FPGA1 inside describes.The circuit structure of FPGA1 inside dynamically changes by be written into the configuration data of back in internal application from nonvolatile memory 2, according to action pattern different circuit structures is installed.But, under any one action pattern, all need CPU10, therefore according to action pattern, the peripheral circuit of CPU10 adopts different circuit structures.
In addition, in CPU10, owing to carry out the software that is written into from nonvolatile memory 2, so the function of CPU10 is according to action pattern and difference.That is, under common use pattern, by CPU10 carry out the operation control of not shown panel, with the control of the exercises of communicating by letter of ancillary equipment, writing under the pattern, obtain interface between nonvolatile memory 2 and the external equipment by CPU10.In addition, under dispatch from the factory pattern in factory, pass through CPU10, in order in electronic endoscope apparatus, to write various inner settings or to carry out confirming operation, obtain and external equipment between interface, under safety is guaranteed pattern,, carry out the lighting of lamp, not shown air delivery pump, the control of panel by CPU10.
At this, use the circuit structure of the FPGA1 inside of Fig. 3 explanation under common use pattern.Fig. 3 is the block diagram of the circuit structure of the FPGA1 inside of explanation under common use pattern.Under normal mode, be provided with CPU10 in FPGA1 inside, be equipped with peripheral circuit in the outer periphery of CPU10, wherein, this peripheral circuit constitutes just like the lower part: serial-to-parallel converter circuit 11 is used for the serial data of sending from external equipment is carried out parallelization; Keyword decoder 12; Lamp state detection circuit 13 is used for detecting the state of the lamp that is arranged on electronic endoscope apparatus; Frequency divider 14; Parallel/serial conversion circuit 15, be used for the parallel data of being handled by CPU10 is carried out serialization and output; Be used to control the pump control circuit 16 of air delivery pump; The output of the buzzer sound when buzzer control circuit 17, control detect temperature mistake that the abnormal ascending because of the temperature of enclosure interior causes or various drive divisions unusual by internal error detection portion.
Like this, constitute CPU10 and peripheral circuit, can follow the change of action pattern dynamically to carry out the circuit change of the inside of FPGA1, only construct necessary circuit, therefore, improve the service efficiency of circuit by inside at FPGA1.In addition,, therefore circuit scale, substrate area can be dwindled, also cost degradation can be realized owing to do not need CPU required in whole action patterns, peripheral circuit are installed on the substrate, and, also relevant with the miniaturization of device.
Secondly, the circuit that the FPGA1 inside that the conversion by action pattern causes be described changes.At this, pay close attention to the circuit relevant with the communication of external equipment, use Fig. 4 A and Fig. 4 B explanation to dispatch from the factory pattern to the circuit change that writes pattern from factory.Fig. 4 A and Fig. 4 B are the block diagrams of the internal structure of the explanation FPGA1 relevant with the communication of external equipment, the internal structure of the FPGA under Fig. 4 A shows and dispatches from the factory pattern in factory, the internal structure that Fig. 4 B shows the FPGA1 under the pattern of writing.
Shown in Fig. 4 A, under dispatch from the factory pattern in factory, for the inner setting of the confirming operation that can make electronic endoscope apparatus, serial number etc. as external equipment dispatch from the factory with checkout facility 21 and electronic endoscope apparatus between communicate, need to be provided with by communication I/F equipment 6 and can carry out CPU10 and dispatch from the factory with the detection order wire that dispatches from the factory of the communication between the checkout facility 21.In addition, shown in Fig. 4 B, writing under the pattern, for from the program of obtaining the configuration data of FPGA1, carrying out by the CPU10 that is configured in FPGA1 inside with equipment 22 that writes as external equipment, and in nonvolatile memory 2, upgrade, need to be provided with by communication I/F equipment 6 and can carry out CPU10 and write using order wire with writing of the communication between the equipment 22.
Do not need to write under dispatch from the factory pattern in factory and use order wire, check and use order wire writing not need under the pattern to dispatch from the factory.Promptly, no matter under any pattern, the order wire that uses has only one, do not use order wire with order wire with writing owing to can not use the inspection of dispatching from the factory simultaneously, therefore can be with synthetic one of two order wires, according to the connection destination of action pattern converts communications I/F equipment 6, be the communication port of CPU10, thereby, guarantee the order wire that two action patterns are required.In addition, being connected of the terminal by substrate wiring fixed communication I/F equipment 6 and FPGA1, therefore, being connected of terminal by conversion FPGA1 and the connectivity port of CPU10, follow the change of order wire of the change of action pattern.
Promptly, under dispatched from the factory pattern in factory, the internal circuit of FPGA1 constituted and is connected with communication I/F equipment 6 with checkout facility 21 dispatching from the factory, and the terminal of the FPGA1 that will be connected with communication I/F equipment 6 and the 1st COM1 23 of CPU10 are connected, thereby, the inspection order wire of guaranteeing to dispatch from the factory.Action pattern is transformed under the situation of the pattern of writing from factory's pattern of dispatching from the factory, the internal circuit of change FPGA1 makes will write with equipment 22 and is connected with communication I/F equipment 6, and the FPGA1 terminal that will be connected with communication I/F equipment 6 and the 2nd COM1 24 of CPU10 be connected, thereby guaranteeing to write uses order wire.
Like this, change the internal circuit of FPGA1 according to action pattern, the 1st COM1 23 of CPU10 and the 2nd COM1 24 can communicate according to action pattern and the external equipment that is connected on the I/F equipment 6 by identical communication I/F equipment 6.Therefore, do not need to guarantee individually in advance the order wire that each action pattern is required, can constitute and action pattern corresponding communication line then and there by the internal circuit of change FPGA1.
In addition, under dispatch from the factory pattern in factory, except the circuit relevant, in FPGA1 inside, also be provided with the circuit that is used to carry out confirming operation, be each circuit of Mechanical Driven control circuit 28, panel control circuit 29 and lamp control circuit 30 as the peripheral circuit of CPU10 with the communication of external equipment.For these peripheral circuits are connected with CPU10, the 1st～the 3I/O port 25～27 is set, on CPU10 respectively with corresponding peripheral circuit connection.Writing under the pattern, except the circuit relevant with the communication of external equipment, the peripheral circuit in FPGA1 inside as CPU10 also is provided with panel control circuit 29.Panel control circuit 29 is connected with 1I/O port 25, do not use CPU10 remaining the 2nd, 3I/O port 25,27.In addition, writing under the pattern, need write start address, send data or receive data to nonvolatile memory 2 outputs, so CPU10 be connected with data/address bus 9 by address bus 8 with nonvolatile memory 2 from nonvolatile memory 2 to nonvolatile memory 2.
Next, the effect in the electronic endoscope apparatus that the flowchart text of use Fig. 5 constitutes as mentioned above about the device startup.Fig. 5 is the flow chart of the boot sequence of explanation electronic endoscope apparatus.In order to observe, to dispose subject and use under the situation of electronic endoscope apparatus, only select common use pattern.In addition, in the observation of subject, disposing, when action pattern easily convert inspections of dispatching from the factory to, safeguard in the factory of use dispatch from the factory pattern, when writing pattern, have problems probably.Therefore, in the present embodiment, suppose in acquiescence and the time select common use pattern, only be converted to this action pattern under the situation in required movement pattern consciously, the start-up course of device is described.
As shown in Figure 5, at first, in step S1, when connecting the power supply of electronic endoscope apparatus, in following step S2, the configuration data of normal mode is loaded into FPGA1 by data/address bus 9 from nonvolatile memory 2.Secondly, in step S3,, use the circuit of pattern usually in the FPGA1 internal application according to the configuration data that is written into.In addition, not shown panel is provided with and is used to make the user to indicate the button 1,2 of the conversion of action pattern, is incorporated with in the circuit to detect these push-button after application.
Then, in step S4, the initialization of beginning CPU10.In the initialized process of carrying out CPU10,, monitor all the time whether the button 1 of panel or button 2 press (step S5) by testing circuit in the peripheral circuit that is included in CPU10, conduct conversion request detection portion.In step S5, in the initialization procedure of CPU10, under the situation that the button 1 that is judged as panel or button 2 are not pressed, enter the initialization that step S15 finishes CPU10.In addition, invalid under the situation effective under the situation that button 1,2 is configured to only be pressed in the CPU10 initialization is carried out, that initialization is pressed after finishing in step S15, and become in case when usually the use pattern finishes the startup of device, just can not convert the pattern of writing, the factory pattern of dispatching from the factory to.
In step S5, in the initialization of CPU10, under the situation that the button 1 that is judged as panel or button 2 have been pressed, enter step S6, judge that the button of pressing is button 1 or button 2.
In step S6, be under the situation of button 1 being judged as the button of pressing, enter step S7, export action pattern is changed to the action pattern switching signal that the pattern of writing is a content to CPLD3 from FPGA1.CPLD3, in following step S8, the circuit of cancellation FPGA1 inside is exported the write start address corresponding with the pattern that writes by address bus 8 to nonvolatile memory 2.Then, in step S9, nonvolatile memory 2 is according to the start address that reads in that receives, and is written into the configuration data of the pattern that writes of FPGA1 by data/address bus 9, enters step S13.
On the other hand, in step S6, be under the situation of button 2 being judged as the button of pressing, enter step S10, export action pattern is changed to the action pattern switching signal that factory's pattern of dispatching from the factory is a content to CPLD3 from FPGA1.CPLD3, in following step S11, the circuit of cancellation FPGA1 inside, by address bus 8 to nonvolatile memory 2 output and factory dispatch from the factory pattern corresponding write start address.Then, in step S12, nonvolatile memory 2 is according to the start address that reads in that receives, and by data/address bus 9 the dispatch from the factory configuration data of pattern of factory is loaded into FPGA1, enters step S13.
In step S13,, write the dispatch from the factory circuit of pattern of pattern or factory in the internal application of FPGA1 according to the configuration data that is written into.Then, in step S14, the initialization of beginning CPU10 in step S15, finishes the initialization of CPU10.At last, in step S16, finish the startup of required movement pattern.
As mentioned above, from energized in finish during CPU10 initialized, do not pressing the button under 1,2 the situation with common use pattern starting drive, pressing the button under 1 the situation writing the pattern starting drive, pressing the button under 2 the situation pattern starting drive that dispatches from the factory with factory.In addition, in above-mentioned example, button by panel press the conversion of carrying out action pattern, also can be according to use etc., for example use from external equipment send order, by with communicating by letter of external equipment carry out remote manipulation send order, by the switch on the substrate carry out the order indication, from other method such as the indication of device interior wrong detection unit, input action pattern conversion indication.In addition, can also be by after receiving action pattern conversion indication, inner or outside from FPGA1 to the action pattern switching signal of CPLD3 output needle to the required movement pattern, the configuration data of this action pattern is loaded into FPGA1 and uses from nonvolatile memory 2, thereby carry out the conversion of action pattern.And, also can after starting end, wait and at random change action pattern.
In addition, in use pattern lower device moves usually, the CPU10 of FPGA1 inside or peripheral circuit detect under the situation of device internal abnormality such as unusual of internal temperature, various drive divisions, guarantee that action pattern is converted to safety pattern is the action pattern switching signal of content to CPLD3 output from the CPU10 or the peripheral circuit of FPGA1 inside.The circuit of CPLD3 cancellation FPGA1 inside, by address bus 8 to nonvolatile memory 2 output with safe guarantee pattern corresponding write start address.Nonvolatile memory 2 guarantees that with safety the configuration data of pattern is loaded into FPGA1 by data/address bus 9 according to the start address that reads in that receives.In FPGA1, use the configuration data that is written into, finish to guarantee to safety the conversion of the action pattern of pattern from common use pattern.
Like this, in the electronic endoscope apparatus of present embodiment, by under each action pattern, being formed in FPGA1 inside as the CPU10 and the peripheral circuit of necessary function, follow the change of action pattern dynamically to carry out the circuit change of the inside of FPGA1, owing to need not on substrate, to install required CPU, the peripheral circuit of whole action patterns, thereby can dwindle circuit scale, the substrate area of on substrate, installing, improve circuit service efficiency, seek cost degradation.
In addition, CPU, peripheral circuit directly are not installed on substrate, but when starting action pattern at every turn, by being written into configuration data from nonvolatile memory 2, and carry out circuit application in FPGA1 inside, also can reduce the bad probability of circuit bad or that cause owing to heating, static and deterioration in time from circuit is installed, can improve the performance of circuit operation, particularly reliability.
And then, following substrate deterioration and under the situation about needing to be maintained in time, the circuit structure that uses in the inside of FPGA1, CPLD3 is owing to be kept in the configuration data, this configuration data is kept in the nonvolatile memory 2, thereby other FPGA1, CPLD also can migrate and need not and replace inquiring into by each parts such as CPU10, peripheral circuits, thereby can cut down time, the cost that spends on replacing inquiring into.
As mentioned above, according to present embodiment, the electronic endoscope apparatus that can realize improving the circuit service efficiency of control part and can improve the reliability of circuit operation.
The 2nd embodiment
At first, according to Fig. 7, the overall structure of the anomaly monitoring portion of the controller relevant with the related electronic endoscope apparatus of the 2nd embodiment of the present invention is described.Fig. 7 is the block diagram of the structure of the explanation anomaly monitoring portion relevant with the controller of the related electronic endoscope apparatus of the 2nd embodiment of the present invention.
As shown in Figure 7, relevant with the controller of the related electronic endoscope apparatus of the 2nd embodiment of the present invention anomaly monitoring portion is by constituting as the lower part: the controller FPGA 201 that becomes monitored object; As the WatchDog Timer IC202 of abnormity detection portion, detect the unusual of FPGA201 and make it carry out homing action; Clock 203 generates clock signal clk and outputs to FPGA 201.
In CPU 211, represent the initialization end notification signal the SEL whether initialization of the software of CPU211 output has finished to 214 outputs of house dog control part.In the present embodiment, under the executory situation of being initialized as of software, as initialization end notification signal SEL output LOW, under the situation that initialization finishes, as initialization end notification signal SEL output HIGH.In addition, also export watchdog zero clearing signal WDCK to house dog control part 214 from CPU 211.WatchDog Timer reset signal WDCK is the pulse signal of fixed cycle, and it is output in the initialization of software is carried out not, but finishes back output in initialization.
In watchdog zero clearing signal generating unit 213, use the clock signal clk that receives from clock 203, generate the watchdog zero clearing timer signal WDCK_HW of any period of setting in advance by the designer, and output to house dog control part 214.
In house dog control part 214, the signal according to from CPU 211 and 213 receptions of watchdog zero clearing signal generating unit generates WatchDog Timer reset signal WD_CLR, outputs to WatchDog Timer IC 202.Promptly, at the initialization end notification signal SEL that receives from CPU 211 is under the situation of LOW, the watchdog zero clearing timer signal WDCK_HW that receives from watchdog zero clearing signal generating unit 213 exports as WatchDog Timer reset signal WD_CLR, at initialization end signal SEL is under the situation of HIGH, and the WatchDog Timer reset signal WDCK that receives from CPU211 exports as WatchDog Timer reset signal WD_CLR.
Wherein, house dog control part 214 has the startup monitoring unit of the startup situation of supervisory controller.And, house dog control part 214 is provided with not shown enumerator, and this enumerator is counted the number of times (pulse number) that the watchdog zero clearing timer signal WDCK_HW that receives from watchdog zero clearing signal generating unit 213 exports as WatchDog Timer reset signal WD_CLR.Start monitoring unit and constitute the maximum N whether the count value K that monitors this enumerator has reached the umber of pulse of prior registration, under the situation that reaches maximum N, do not export WatchDog Timer reset signal WD_CLR.By constituting in this wise, in startup, take place to finish unusually and not under the initialized situation at CPU 211, can stop 202 output WatchDog Timer reset signal WD_CLR to WatchDog Timer IC, to CPU 211 output reset signal WD_RST_N, it is out of control that CPU 211 is stopped from WatchDog Timer IC 202.
In WatchDog Timer IC 202, from the intervalometer zero clearing begin fixing during in, under the situation of house dog control part 214 input WatchDog Timer reset signal WD_CLR, generate reset signal WD_RST_N signal and also output to CPU 211.During above-mentioned intervalometer zero clearing begins fixing till the output reset signal WD_RST_N, be called time-out period, have the values of decision in advance by WatchDog Timer IC 202.
In addition, during the FPGA 201 execution configurations, do not import WatchDog Timer reset signal WD_CLR to WatchDog Timer IC 202 from house dog control part 214.Therefore, carry out at FPGA 201 under the situation of the time ratio time-out period length that disposes,, might cause resetting from WatchDog Timer IC 202 output reset signal WD_RST_N.But in the present embodiment, CPU 211 is formed in the inside of FPGA 201, and FPGA 201 is high impedance status except that special pin, even therefore FPGA 201 carries out under the situation of the time ratio time-out time length that disposes, also can avoid resetting.
Secondly, use Fig. 8 and Fig. 9, the anomaly monitoring action of the electronic endoscope apparatus that as above constitutes is described.Fig. 8 is the sequential chart of the anomaly monitoring action of explanation when CPU 211 normal startups.Fig. 9 is the sequential chart that the anomaly monitoring action when generation is unusual in CPU starts is described.
At first, use the sequential chart of Fig. 8, the anomaly monitoring action when CPU 211 is normally started describes.At first, when connecting the power supply of electronic endoscope apparatus, FPGA201 carries out configuration.In configuration is carried out, do not import WatchDog Timer reset signal WD_CLR to WatchDog Timer IC 202 from house dog control part 214.But, as mentioned above, because FPGA 201 be high impedance status,, also do not import reset signal WD_RST_N to CPU 211 in the inside of FPGA 201 formation even therefore carry out under the situation of time ratio time-out period length of configuration at FPGA201 except that special pin.
When the configuration of FPGA 201 finishes, carry out the initialization of CPU 211.Therefore, from the initialization end notification signal SEL of CPU 211 to house dog control part 214 output LOW.In addition, in watchdog zero clearing signal generating unit 213, the clock signal clk according to receiving from clock 203 generates the watchdog zero clearing timer signal WDCK_HW as the pulse signal of any period, outputs to house dog control part 214.
In house dog control part 214, the watchdog zero clearing timer signal WDCK_HW that receives from watchdog zero clearing signal generating unit 213 outputs to WatchDog Timer IC 202 as WatchDog Timer reset signal WD_CLR.In addition, in house dog control part 214, by not shown enumerator output number of times (number of output pulse) is counted, this output number of times is the number of times that watchdog zero clearing timer signal WDCK_HW is exported as WatchDog Timer reset signal WD_CLR.
In house dog control part 214, according to various design informations calculate CPU 211 normally finish till the initialization during in, output to the maximum of pulse number WatchDog Timer IC 202, watchdog zero clearing timer signal WDCK_HW as WatchDog Timer reset signal WD_CLR, and set maximum N for.That is: maximum N was set in the cycle of watchdog zero clearing timer signal WDCK_HW, multiply by the maximum N of umber of pulse and time of obtaining, be equivalent to time till CPU 211 normally finishes initialization (can from the time that detailed estimate obtains).
In Fig. 8, the count value K of the enumerator in house dog control part 214 reaches before the maximum N, and CPU 211 normally finishes initialization.When the initialization at CPU 211 finishes, be transformed into HIGH to the initialization end notification signal SEL of house dog control part 214 outputs from LOW from CPU 211.In addition, when when the initialization of CPU 211 finishes, from CPU 211 to the WatchDog Timer reset signal WDCK of house dog control part 214 outputs as the pulse signal of fixed cycle.
In house dog controller 214, when receiving the initialization end notification signal SEL of HIGH, with output to WatchDog Timer IC 202 WatchDog Timer reset signal WD_CLR, be transformed into the WatchDog Timer reset signal WDCK of reception from the watchdog zero clearing timer signal WDCK_HW that receives from watchdog zero clearing signal generating unit 213 from CPU 211.After this, under the state that CPU211 moves usually, WatchDog Timer IC 202 receives from WatchDog Timer reset signal WD_CLR from house dog control part 214, continues to monitor that CPU 211 has no abnormal.
Secondly, use the sequential chart of Fig. 9, the anomaly monitoring action that produces under the situation unusual, that initialization does not have to finish during CPU 211 is started describes.Identical during from the action till the initialization of beginning CPU 211 of the power supply of connecting electronic endoscope apparatus, with the regular event that uses Fig. 8 explanation, so describe in the executory action of this initialization to CPU 211.
In the initialization of CPU 211 is carried out, from the initialization end notification signal SEL of CPU211 to house dog control part 214 output LOW.In addition, in watchdog zero clearing control part 214, the watchdog zero clearing timer signal WDCK_HW that receives from watchdog zero clearing signal generating unit 213 outputs to WatchDog Timer IC 202 as WatchDog Timer reset signal WD_CLR, and, to the number of times (number of the pulse of output) that watchdog zero clearing timer signal WDCK_HW exports as WatchDog Timer reset signal WD_CLR, in not shown enumerator, count as count value K.
In Fig. 9, CPU 211 takes place unusual in initialization is carried out, owing to initialization does not finish, therefore, even reach the umber of pulse maximum N that count value K sets, still from the initialization end notification signal SEL of CPU211 to house dog control part 214 output LOW.When count value K reaches maximum N, stop 202 output WatchDog Timer reset signal WD_CLR to WatchDog Timer IC from house dog control part 214.In WatchDog Timer IC 202, receive the last pulse of WatchDog Timer reset signal WD_CLR from house dog control part 214, do not receive next pulse through the time-out period of setting yet, thereby detect CPU 211 and taken place unusually.Thus, through behind the time-out period, export reset signal WD_RST_N to CPU 211 from WatchDog Timer IC 202.
Like this, in the electronic endoscope apparatus of present embodiment, CPU 211 carries out in the initialization, the watchdog zero clearing timer signal WDCK_HW that generates by watchdog zero clearing signal generating unit 213 as the pulse signal of any period, be used as WatchDog Timer reset signal WD_CLR and output to WatchDog Timer IC 202, even thereby use the time-out period WatchDog Timer IC 202 shorter than the start-up time of CPU 211, can prevent that also CPU 211 repeats to restart in initialization.
In addition, by using the short WatchDog Timer IC 202 of time-out period, when CPU 211 generations are unusual and out of control under common user mode, can promptly CPU 211 be resetted and recover.
In addition, count by 214 pairs of number of times (output pulse number) suitable with the initialization time of implementation of CPU 211, that watchdog zero clearing timer signal WDCK_HW exports as WatchDog Timer reset signal WD_CLR of house dog control part, whether the initialization that detects CPU211 in just can be the term of execution of the initialization of design finishes., initialization unusual and out of control in CPU 211 generation in initialization is carried out is absorbed under the situation of the state that does not finish, by stopping from house dog control part 214, just can reset and recover CPU 211 to WatchDog Timer IC202 output WatchDog Timer reset signal WD_CLR.
And, in the configuration of FPGA 201 is carried out, by the pin beyond FPGA 201 special pin is made as high impedance status, even under the long situation of the time-out period of the time ratio WatchDog Timer IC 202 that FPGA 201 execution are disposed, also can avoid in the configuration of FPGA201 is carried out, carrying out homing action.
The 3rd embodiment
Secondly, use Figure 10 that the 3rd embodiment of the present invention is described.Figure 10 is the block diagram of the structure of the explanation anomaly monitoring portion relevant with the controller of the related electronic endoscope apparatus of the 3rd embodiment of the present invention.In the above-described 2nd embodiment, carry out in the initialization at CPU 211, the watchdog zero clearing timer signal WDCK_HW of the pulse signal by any period that will generate as watchdog zero clearing signal generating unit 213 outputs to WatchDog Timer IC 202, do not make and export reset signal WD_RST_N, thereby avoid in initialization, carrying out the homing action of CPU 211 from WatchDog Timer IC 202.With respect to this, invalid by making in CPU231 carries out initialization in the present embodiment from the reset signal WD_RST_N of WatchDog Timer IC 202 outputs, thus avoid in initialization, carrying out the homing action of CPU231.
The anomaly monitoring portion relevant with the controller of electronic endoscope apparatus, except that internal structure difference as the controller FPGA221 of monitored object, all identical with the 2nd embodiment, at this, only the internal structure to FPGA221 describes, and omits explanation for identical element labelling same-sign.In addition, for various signals from the output of each element, also labelling same-sign and omit explanation.
As shown in figure 10, FPGA221 is by constituting as the lower part: CPU231; Other control parts 212, each position such as the memorizer of control electronic endoscope apparatus, panel; As the watchdog reset control part 233 of reset signal generating unit, judge whether to make CPU231 to carry out homing action, export reset signal RESET to CPU231.In addition, initialization end notification signal SEL and WatchDog Timer reset signal WDCK output to watchdog reset control part 233 and WatchDog Timer IC 202 from CPU231 respectively.
In watchdog reset control part 233, according to from the reset signal WD_RST_N of WatchDog Timer IC 202 output with from the initialization end notification signal SEL of CPU231 output, RESET outputs to CPU231 with reset signal.That is, receiving the initialization end notification signal SEL of HIGH, and also receiving under the situation of reset signal WD_RST_N, to CPU231 output reset signal RESET.In addition, even under the situation of the initialization end notification signal SEL that receives LOW, when the reset signal WD_RST_N that receives more than the specific times N ', to CPU231 output reset signal RESET.At this, N ' sets for specific times: be equivalent to time till CPU 231 normally finishes initialization in the time that the specific times N ' that multiply by umber of pulse on the cycle of reset signal WD_RST_N obtains (can from the time that detailed estimate obtains).
By constituting in this wise, in CPU 211 initialization are carried out, because from CPU231 output WatchDog Timer reset signal WDCK, though thereby from WatchDog Timer IC 202 output reset signal WD_RST_N, also can avoid carrying out homing action by house dog control part 214.In addition, watchdog reset control part 233 has the startup monitoring unit of the startup situation of supervisory controller.And, watchdog reset control part 233 monitors that CPU231 carries out the initialized time, be absorbed under the situation of the state that does not finish in, initialization unusual and out of control, will output to CPU231 as reset signal RESET from watchdog reset control part 233 from the reset signal WD_RST_N of WatchDog Timer IC 202 outputs when CPU 211 generation in initialization is carried out.Thus, just can reset and recover CPU 211.
The 4th embodiment
Secondly, use Figure 11 that the 4th embodiment of the present invention is described.Figure 11 is the block diagram of the structure of the explanation anomaly monitoring portion relevant with the controller of the related electronic endoscope apparatus of the 4th embodiment of the present invention.In above-mentioned the 2nd embodiment, in the exterior arrangement of FPGA 201 WatchDog Timer IC 202 is arranged, in the present embodiment, the inside this point that WatchDog Timer portion 242 is configured in FPGA241 is inequality.WatchDog Timer portion 242 and WatchDog Timer IC 202 are similarly, in the time-out period of setting, not under the situation of house dog control part 214 input WatchDog Timer reset signal WD_CLR, to CPU 211 output reset signal WD_RST_N, carry out homing action.Other elements, identical with the 2nd embodiment from the various signals of each element output.
By WatchDog Timer portion 242 being configured in the inside of FPGA241, just can at random set the time-out period of WatchDog Timer portion 242, improve the degree of freedom of design.In addition,, therefore in configuration, do not export reset signal WD_RST_N, can positively avoid carrying out homing action because till the configuration of FPGA241 finished, WatchDog Timer portion 242 did not move yet.
The 5th embodiment
Secondly, use Figure 12 that the 5th embodiment of the present invention is described.Figure 12 is the block diagram of structure of the anomaly monitoring portion of the controller relevant with the related electronic endoscope apparatus of bright the 5th embodiment of the present invention.In above-mentioned the 2nd embodiment,, in the present embodiment, these are configured in the outside this point difference of FPGA251 though watchdog zero clearing signal generating unit 213 and house dog control part 214 are configured in the inside of FPGA 201.
In the present embodiment, as shown in figure 12, for example at the outer setting CPLD252 of FPGA251, at internal configurations watchdog zero clearing signal generating unit 213 and the house dog control part 214 of CPLD252.CPLD252 compares with FPGA251, early finish configuration.Under the early situation that finishes to dispose, finish configuration from FPGA251 and begin to carry out homing action than CPLD252 at FPGA251 to during till the WatchDog Timer IC 202 output WatchDog Timer reset signal WD_CLR, producing time-delay.But thus, can avoid unwanted homing action.Other elements, identical with the 2nd embodiment from the various signals of each element output.
By constituting in this wise, can obtain the effect identical with the 2nd embodiment, can also improve design freedom.
In addition,, also can replace WatchDog Timer IC 202, in the internal configurations WatchDog Timer portion of CPLD252 as the variation of the 5th embodiment.By constituting in this wise, WatchDog Timer portion does not move till the configuration end of CPLD252, thereby even under the early situation that finishes to dispose, can avoid unnecessary homing action than CPLD252 at FPGA251 yet.
As mentioned above, according to the relevant electronic endoscope apparatus of the from the 2nd to the 5th embodiment, the electronic endoscope apparatus that can be achieved as follows, this device has the anomaly monitoring portion of the unusual execution homing action that detects controller, even use the time-out time WatchDog Timer shorter, can prevent that also CPU from repeating to restart than the start-up time of CPU.
The application is that priority proposes with Japanese patent application 2005-181153 number of proposing in Japan in Japanese patent application 2005-195407 number of proposing in Japan on July 4th, 2005 and on June 21st, 2005, and above-mentioned disclosure is quoted in description in the application, claims.
Claims (5)
1. an electronic endoscope apparatus has a plurality of action patterns of being carried out exclusively, it is characterized in that having:
Control part, the execution of its control aforementioned activities pattern; And
Conversion request detection portion, it detects the conversion request of performed aforementioned activities pattern, wherein,
Aforementioned control part only in the initialization action of aforementioned control part, according to the detected testing result of aforementioned conversion request detection portion, carries out the change of the internal structure corresponding with the aforementioned activities pattern.
2. electronic endoscope apparatus according to claim 1 is characterized in that:
Aforementioned control part possesses CPLD and/or in internal configurations the FPGA of CPU and peripheral circuit is arranged, and according to the testing result of aforementioned conversion request detection portion, changes the internal structure of aforementioned FP GA and/or aforementioned CPLD.
3. electronic endoscope apparatus according to claim 2 is characterized in that:
Aforementioned control part also possesses nonvolatile memory, this nonvolatile memory preserve aforementioned a plurality of action pattern separately about the data of the internal structure of aforementioned FPGA and/or aforementioned CPLD and the software of carrying out by aforementioned CPU.
4. according to the electronic endoscope apparatus described in the claim 3, it is characterized in that:
Aforementioned control part changes the internal structure of aforementioned control part by reading about the data of aforementioned internal structure and being loaded among aforementioned FPGA and/or the aforementioned CPLD from aforementioned nonvolatile memory.
5. according to any described electronic endoscope apparatus in the claim 1～4, it is characterized in that:
When detecting aforementioned electronic endoscope apparatus unusual, conversion request from pattern to safety that guarantee detects in aforementioned conversion request detection portion, and the internal structure of aforementioned control part is altered to the internal structure that aforementioned safety is guaranteed pattern.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005181153A JP3993618B2 (en) | 2005-06-21 | 2005-06-21 | Electronic endoscope device |
| JP2005-181153 | 2005-06-21 | ||
| JP2005-195407 | 2005-07-04 | ||
| JP2005195407A JP5063872B2 (en) | 2005-07-04 | 2005-07-04 | Electronic endoscope device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200610082948 Division CN1883369A (en) | 2005-06-21 | 2006-06-21 | Electronic endoscope device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101268924A CN101268924A (en) | 2008-09-24 |
| CN101268924B true CN101268924B (en) | 2010-11-03 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008100877569A Active CN101268924B (en) | 2005-06-21 | 2006-06-21 | Electronic endoscope device |
| CN 200610082948 Pending CN1883369A (en) | 2005-06-21 | 2006-06-21 | Electronic endoscope device |
| CNU2006201177527U Expired - Fee Related CN201036549Y (en) | 2005-06-21 | 2006-06-21 | Electronic endoscope device |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 200610082948 Pending CN1883369A (en) | 2005-06-21 | 2006-06-21 | Electronic endoscope device |
| CNU2006201177527U Expired - Fee Related CN201036549Y (en) | 2005-06-21 | 2006-06-21 | Electronic endoscope device |
Country Status (2)
| Country | Link |
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| JP (1) | JP3993618B2 (en) |
| CN (3) | CN101268924B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3993618B2 (en) * | 2005-06-21 | 2007-10-17 | オリンパスメディカルシステムズ株式会社 | Electronic endoscope device |
| CN101604244B (en) * | 2008-06-13 | 2012-11-28 | 中兴通讯股份有限公司 | Device and method for realizing that FPGA can be used when being electrified and remote upgrade of FPGA |
| CN103200859B (en) * | 2011-07-05 | 2015-07-22 | 奥林巴斯医疗株式会社 | Image pickup device and endoscope system |
| JP2015001892A (en) * | 2013-06-17 | 2015-01-05 | 株式会社デンソー | Electronic control device |
| JP6491672B2 (en) * | 2014-04-09 | 2019-03-27 | コーニンクレッカ フィリップス エヌ ヴェＫｏｎｉｎｋｌｉｊｋｅ Ｐｈｉｌｉｐｓ Ｎ．Ｖ． | Devices, systems, and methods for use and reuse of certified endovascular devices |
| CN104536840B (en) * | 2014-12-31 | 2018-04-03 | 北京兆易创新科技股份有限公司 | A kind of Watch Dog Timer and its control method |
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| CN1448106A (en) * | 2002-03-29 | 2003-10-15 | 奥林巴斯光学工业株式会社 | Endoscope pick-up device |
| CN1578471A (en) * | 2003-06-27 | 2005-02-09 | 奥林巴斯株式会社 | Image processing device |
| CN1883369A (en) * | 2005-06-21 | 2006-12-27 | 奥林巴斯医疗株式会社 | Electronic endoscope device |
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| JPH0519019A (en) * | 1991-07-09 | 1993-01-26 | Fujitsu Ltd | Method and circuit for assuring operation of semiconductor device |
| JPH1028671A (en) * | 1996-05-13 | 1998-02-03 | Olympus Optical Co Ltd | Electronic endoscope device |
| JP2003122600A (en) * | 2001-10-18 | 2003-04-25 | Matsushita Electric Works Ltd | Watch dog timer device |
| JP3787519B2 (en) * | 2001-11-29 | 2006-06-21 | 三菱電機株式会社 | PLD / FPGA data programming method |
| JP2003339635A (en) * | 2002-05-28 | 2003-12-02 | Olympus Optical Co Ltd | Electronic endoscope |
| JP4827387B2 (en) * | 2003-10-10 | 2011-11-30 | オリンパス株式会社 | Image processing device |
| JP2005342147A (en) * | 2004-06-02 | 2005-12-15 | Olympus Corp | Electronic endoscope apparatus |
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2005
- 2005-06-21 JP JP2005181153A patent/JP3993618B2/en not_active Expired - Fee Related
-
2006
- 2006-06-21 CN CN2008100877569A patent/CN101268924B/en active Active
- 2006-06-21 CN CN 200610082948 patent/CN1883369A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1448106A (en) * | 2002-03-29 | 2003-10-15 | 奥林巴斯光学工业株式会社 | Endoscope pick-up device |
| CN1578471A (en) * | 2003-06-27 | 2005-02-09 | 奥林巴斯株式会社 | Image processing device |
| CN1883369A (en) * | 2005-06-21 | 2006-12-27 | 奥林巴斯医疗株式会社 | Electronic endoscope device |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN201036549Y (en) | 2008-03-19 |
| JP3993618B2 (en) | 2007-10-17 |
| CN1883369A (en) | 2006-12-27 |
| CN101268924A (en) | 2008-09-24 |
| JP2007000206A (en) | 2007-01-11 |
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Effective date of registration: 20151126 Address after: Tokyo, Japan, Japan Patentee after: Olympus Corporation Address before: Tokyo, Japan, Japan Patentee before: Olympus Medical Systems Corp. |