CN101261783A - A 'computer composition principle' simulation experimental system - Google Patents
A 'computer composition principle' simulation experimental system Download PDFInfo
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- CN101261783A CN101261783A CNA2008100609599A CN200810060959A CN101261783A CN 101261783 A CN101261783 A CN 101261783A CN A2008100609599 A CNA2008100609599 A CN A2008100609599A CN 200810060959 A CN200810060959 A CN 200810060959A CN 101261783 A CN101261783 A CN 101261783A
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Abstract
A simulation experiment system of Principles of Computer Composition comprises a single module experiment simulation subsystem and a whole machine experiment simulation subsystem, wherein the single module experiment simulation subsystem includes a register group module simulation unit, an universal register module simulation unit, an arithmetic unit module simulation unit, a memory and bus module simulation unit, an instruction unit simulation unit, a microprogrammed controller module simulation unit and a sequence and start-stop module simulation unit; the single module experiment simulation subsystem includes an initial module, a switch button detection module and a switch motion operating module; the whole machine experiment simulation subsystem includes an initial module, an operational mode identification module, an instruction fetch module, an instruction analysis module and an instruction executing module. The invention provides a simulation experiment system of Principles of Computer Composition which is cost-cutting and can effectively meet the all requirements of assistant teaching experiments.
Description
Technical field
The present invention relates to simulating experimental system.
Background technology
The supporting laboratory facilities of existing " Principles of Computer Composition " course mainly contain:
(1), hardware experiments instrument form: with the computer module of circuit composition.Provide operation to circuit in the experimental teaching, obtain experiment effect.Current college teaching great majority adopt this kind mode.
Problem and shortcoming: experimental teaching must be bought experimental apparatus, and price is more expensive, experimental apparatus maintenance cost height.The experimental apparatus fault can influence teaching efficiency.
(2), hardware experiments instrument and software program combining form: with the computer module of circuit composition, provide operation to circuit in the experimental teaching, obtain experiment effect, obtain data with supporting software from the hardware experiments instrument simultaneously, on software interface, show experiment effect.This mode objective interface.Some colleges and universities adopts this kind mode.
Problem and shortcoming: software must rely on the hardware experiments instrument and use, and when the experiment instrument fault, can't use.Problem and shortcoming are with first kind of mode.
(3), pure software emulated versions: with the function of software realization computer hardware module, the user to virtual hardware operation, obtains experimental result on software interface.This method does not have hardware experiments chamber investment cost and maintenance issues, and is simple to operate, and objective interface can guarantee experiment teaching effect.Current also do not have this type of complete product.Some College Teachers has been developed the software of a certain module of emulation (as arithmetical unit hardware), but does not have the complete product of a computing machine of emulation.
Problem and shortcoming: the only emulation of some module, still need be by experiment instrument, cost height and can not assist the whole requirements that solve education experiment.
Summary of the invention
The cost height of existing in order to overcome " Principles of Computer Composition " experimental facilities, can not assist the deficiency of the whole requirements that solve education experiment, the invention provides a kind ofly reduce cost, effective " Principles of Computer Composition " simulating experimental system of whole requirements of aided education experiment.
The technical solution adopted for the present invention to solve the technical problems is:
A kind of " Principles of Computer Composition " simulating experimental system, comprise single module experiment simulation subsystem and complete machine experiment simulation subsystem, described single module experiment simulation subsystem comprises registers group modular simulation unit, general-purpose register is sent out the modular simulation unit, the operator block simulation unit, storer and bus module simulation unit, the instruction unit simulation unit, microprogram control unit modular simulation unit and sequential and start and stop modular simulation unit, described single module experiment simulation subsystem comprises: initialization module, whether as seen to be used to be provided with each object, variable initial value is set, described object comprises hardware chip, operating switch and intermodule information channel, described variable comprises the hardware chip value, the signal value of operating switch, signal value on the truck, the control signal implication of operating switch representative, the direction of information transmission; The shift knob detection module is used for detecting for automatic in the flash button member, can excite action, writes code in this action, and judgement is data switch or control signal switch; The data switch operational module is used for the information flow animation that video data is input to experiment module, and gives the module hardware chip value with data switch value assignment;
The switch motion operational module is used for the definition according to this module by signal, judges whether control signal is effective to experiment module, and as effectively, the function code of execution module is then finished the function of requirement.If not then module is not moved; Described complete machine experiment simulation subsystem comprises:
Initialization module is used for all objects and variable on the initialization complete machine interface;
The operational mode identification module is used for detecting the operation button, and little single step button or full speed button are pressed in judgement, and the operational mode indexed variable is set;
Instruction fetch module is used for giving internal memory current address value with the value assignment, looks into the internal storage data array according to internal memory current address value, obtains internal memory current data value, and this value is sent to order register; Internal memory current address value, internal memory current data value, order register value show with display lamp;
The analysis instruction module, be used for tabling look-up and obtain little address of the corresponding microprogram of this instruction according to the value of order register, the subscript of little address as the microprogram memory array, find the 1st micro-order of microprogram, code in the micro-order is the control signal of each module, according to micro-instruction code, send control signal for the module that relates to, module is finished function corresponding according to control signal; Display lamp shows micro-order value, little address value, each module control signal lamp value;
The execution command module is used for according to the micro-order that obtains, and transmits control signal for each single module montage, it is the controlled signal combination of each single module montage, if control signal is effective, then this module realizes the function of self, and execution result is embodied in the variable of hardware chip.
As preferred a kind of scheme: described registers group modular simulation unit, general-purpose register send out modular simulation unit, operator block simulation unit, storer and bus module simulation unit, instruction unit simulation unit, microprogram control unit modular simulation unit and sequential and start and stop modular simulation unit adopts flash Actionscript_ exploitation, be issued as the HTML form, the tissue of experimental system adopts HTML hyperlink form to connect.
Technical conceive of the present invention is: system's standalone version development platform is Macromedia flash 8.With HTML hyperlink form each experiment is organized together.Native system does not need to install on computers, can directly move.Running environment is the browser (IE 6 above versions carry this plug-in unit) that flash player plug-in unit is arranged.Grid version development platform of the present invention is Macromedia flash 8, ASP.System needs the IIS environment just can move.
Software of the present invention provides the list of hyperlinks of finishing experimental selection by html page.The experiment that the user carries out according to content choice.Experiment 1 is single module experimental implementation to experiment 7, and experiment 8 is complete machine experimental implementation.Each experiment all comprises experiment instruction explanation document.
Experiment one is the registers group modular simulation
Experiment two is general purpose register block emulation
Experiment three is operator block emulation
Experiment four is storer and bus module emulation
Experiment five is the emulation of instruction component models
Experiment six is microprogram control unit modular simulations
Experiment seven is sequential and start and stop modular simulation
Experiment eight is complete machine comprehensive simulatings
The user selects the experimental project that will carry out from list of experiments, by reading the experiment instruction document, understand the basic principle of operation and the step of experiment, enters emulation experiment machine interface complete operation again.Emulation experiment machine interface is a background with true experiment instrument photo, can give the strong sense of reality of operator like this.The hardware module that experiment relates to and the logic of this module all identify and draw out, realize the actual situation combination.
The experiment instruction document is a HTML static page form.
The emulation experiment machine divides 2 classes, single module experiment simulation and comprehensive experimental machine emulation.
1, the single module experiment simulation includes
1.1, single module experiment simulation function
The operator connects the line of requirement of experiment, can operate input switch, provides data, address, control signal to experiment module.The user specifies signal jack and the input switch jack that connects by click during line, and connection line appears on the interface, if malunion is true, does not then have signal wire and occurs.
After line was finished, the user can operate this experiment module.Use the click switch, switch has corresponding variation, pilot lamp on the switch can light on and off be represented data " 1 " and " 0 ", and the animation of representation signal transmission can be demonstrated simultaneously, and the user can see the high-low level signal that the operation of oneself provides is delivered to specifically where chip block has got on.In the experimentation, mouse can be moved on the chip, the data value of this chip internal can show with binary mode.The work-based logic complete simulation hardware effort situation of module, chip is made different operating to the control signal various combination.
Yellow signal flow animation is represented the data information transfer route, and red signal flow represents that the control signal switch provides high level to send to the chip pin of connection.Value on data switch display lamp, gauge tap display lamp, the bus display lamp is consistent with experiment instrument display format.Can also directly click the chip in the module in addition, the data value in the inquiry chip.For the more chip of function, go back display reminding information, the control signal of reminding the user to provide has been selected which kind of function of this chip.
1.2, single module design of Simulation thinking
In the single module experiment, the object and the relation that relate to have:
1) object: hardware chip, operating switch, intermodule truck.
2) attribute: signal value, the control signal implication of operating switch representative, the direction (decision animated) of information transmission, the function that hardware chip is finished on the signal value of hardware chip value, operating switch, the truck.
3) action: the control Significance of operating switch arrives hardware chip through the information transmission path, and hardware chip starts built-in function to be realized.
Emulation experiment machine original state, after the user did operation to operating switch, the experimental machine revolution was reportedly passed and the hardware capability running status, and the control action of switch is embodied at any time.
Corresponding single module simulation analysis, we set up the example of each object in flash.Exercisable object has graphic elements, film clip element, button member among the Flash.Hardware chip represents that with graphic elements property value represents with film clip element animation that with the dynamic variable value representation of graphic elements association, information transmission action the operating switch action is represented with button member.
Flash ActionScript program thread:
(1) whether visible initialization operation is finished at first frame, comprise and the variable initial value setting of each object
(2) shift knob detects: button member is to detect automatically in flash, can excite on (press) action.Write code in this action, judgement is data switch or control signal switch
(3) if data switch is operated, then video data is input to the information flow animation of experiment module.And give the module hardware chip value with data switch value assignment.
(4) if gauge tap operation then according to the definition of this module by signal, judges whether these control signals are effective to experiment module, effectively, the function code of execution module is then finished the function of requirement.If not then module is not moved.
2, complete machine experimental machine emulation
2.1 complete machine experimental machine The Realization of Simulation function
The complete machine experiment is that all modules are linked together by bus, becomes a complete computing machine.Experimental duties are to adopt the order set of prototype to program, and full speed, single step or little single step run program are finished program function on experimental machine.Procedure result can record or read display lamp from hardware chip and check.
Comprehensive complete machine emulation content comprises 2 parts:
Part 1 is that the user imports self-editing assembly level program and is converted into the process simulation that binary code deposits internal memory in.
2.1.1 assembly routine compilation process emulation
This part realizes allowing the user to import self-editing assembly routine, and compiling generates binary code.Functional module comprises user program file operation module, the user program debugging module, and the user program compiling generates the binary code module.
What user program file operation module provided program file opens, edits, preserves operation.Opening operation is that the program file that the user has editted is read in the emulation interface.We can only read the txt text by the simulated program of exploitation, so the user will write on program code in the text-only file in advance.Editing operation provides at the input text frame and realizes, can finish the program input, add, deletes basic operation.User program is preserved operational module and is triggered by button, after the user presses save button, the content in the input text frame can be saved as text, and the user can preserve and utilization again code.
The user program debugging module is according to the experiment instrument order set, checks grammar mistake and instruction errors in the user program file.Because the Instruction System Design of model experiment machine is fairly simple, 34 instructions altogether, and all be to adopt fixing operation sign indicating number form, instruction length has two kinds of 1 byte and 2 bytes, has only the instruction of counting addressing modes immediately just to be translated as 2 bytes.So identification and misarrangement to instruction are judged just than being easier to, and utilize the string operation function, extract delegation from program file, after removing the head and the tail space, according to order format relatively to character string, if order format in the non-order set occurs, then provide miscue, return edit page.
If instruction meets the order format of order set regulation, then the user program compiling generates the binary code module, obtains the hexadecimal code of this instruction by tabling look-up, and is placed in the array of representing memory headroom, according to instruction length, change the memory headroom address number simultaneously.
2.1.2 program run emulation module
The operation of program comes down to each several part that hardware the forms process of coordination in succession.This part emulation, the function that relates to each module realizes the data transfer between each module, the sequence of operation of each module.
The function of each module realizes with single module emulation part, but the source of data, address and control signal is then no longer by manual operations, but obtained by bus.Data transfer between each module is all undertaken by bus, comprises data bus, address bus and control bus.So during data transfer, the flow direction of flash demo data is arranged between each module.The data value of each module is then realized preserving with variable.
Program run is initial, and the initializaing variable value of each module is 0.After the user presses the operation button, the basic order of simulation computer program run: instruction fetch, analysis instruction, execution command.
Program run on the replicating machine provides little single step run and 2 kinds of patterns of full speed running.Little single step button of pressing according to the user still is the full speed running button, and a value of statistical indicant is set, and according to value of statistical indicant, whether the stop statement that is set in behind each step micro-order animation is carried out.
Flash ActionScript program thread:
(1) all objects and variable on the initialization complete machine interface
(2) detect the operation button, press little single step button or full speed button, the operational mode indexed variable is set
(3) instruction fetch: the item of hardware that this process relates to has programmable counter PC, internal memory, order register; The variable that this process relates to has PC value, internal memory current address value, internal memory current data value, order register value.The signal transmission of this process is to give internal memory current address value with pc value assignment, looks into the internal storage data array according to internal memory current address value, obtains internal memory current data value, and this value is sent to order register.This process comprises that also internal memory current address value, internal memory current data value, order register value show with display lamp except animation flows.
(4) analysis instruction: controller module emulation be microprogram control unit, so the process of analysis instruction is the process that finds microprogram according to the value in the order register.Microprogram adopts the horizontal type microinstruction format, is stored in advance in the microprogram memory, and we design a value in the array preservation microprogram memory.The hardware that this process relates to has order register, microprogram control memory; The variable that this process relates to has order register value, little address value, micro-order value.The signal transmission of this process is to table look-up according to the value of order register to obtain little address of the corresponding microprogram of this instruction, the subscript of little address as the microprogram memory array, finds the 1st micro-order of microprogram.Code in the micro-order is the control signal of each module, so can send control signal for the module that relates to according to micro-instruction code, module be finished function corresponding according to control signal.The animation of this process also will show micro-order value, little address value, each module control signal lamp value with display lamp except the demonstration signal flow.
The microcycle time difference of each instruction has 2～4 in the experiment instrument order set.We are 4 with all instruction microcycle unifications, and when the microcycle was less than 4 instruction execution, the vacant microcycle carried out transfer instruction and gets final product.
(4) execution command: the micro-order that obtains according to back, transmit control signal for each single module montage, promptly the controlled signal combination of each single module montage is effective as if control signal, then this module realizes the function of self, and execution result is embodied in the variable of hardware chip.4 micro-orders are finished, and then re-execute for (3) step.Up to running into stop instruction, system is out of service.
Beneficial effect of the present invention mainly shows: whole requirements of reduce cost, effective aided education being tested.
Description of drawings
Fig. 1 is the overall construction drawing of " Principles of Computer Composition " simulating experimental system.
Fig. 2 is the single module object and concerns synoptic diagram.
Fig. 3 is a single module simulation status transition diagram.
Fig. 4 is single module simulation flow figure.
Fig. 5 is complete machine simulation flow figure.
Embodiment
Below in conjunction with accompanying drawing the present invention is further described.
With reference to Fig. 1～Fig. 5, a kind of " Principles of Computer Composition " simulating experimental system, comprise single module experiment simulation subsystem and complete machine experiment simulation subsystem, described single module experiment simulation subsystem comprises registers group modular simulation unit, general-purpose register is sent out the modular simulation unit, the operator block simulation unit, storer and bus module simulation unit, the instruction unit simulation unit, microprogram control unit modular simulation unit and sequential and start and stop modular simulation unit, described single module experiment simulation subsystem comprises: initialization module, whether as seen to be used to be provided with each object, variable initial value is set, described object comprises hardware chip, operating switch and intermodule information channel, described variable comprises the hardware chip value, the signal value of operating switch, signal value on the truck, the control signal implication of operating switch representative, the direction of information transmission; The shift knob detection module is used for detecting for automatic in the flash button member, can excite action, writes code in this action, and judgement is data switch or control signal switch; The data switch operational module is used for the information flow animation that video data is input to experiment module, and gives the module hardware chip value with data switch value assignment; The switch motion operational module is used for the definition according to this module by signal, judges whether control signal is effective to experiment module, and as effectively, the function code of execution module is then finished the function of requirement.If not then module is not moved; Described complete machine experiment simulation subsystem comprises: initialization module is used for all objects and variable on the initialization complete machine interface; The operational mode identification module is used for detecting the operation button, and little single step button or full speed button are pressed in judgement, and the operational mode indexed variable is set; Instruction fetch module is used for giving internal memory current address value with the value assignment, looks into the internal storage data array according to internal memory current address value, obtains internal memory current data value, and this value is sent to order register; Internal memory current address value, internal memory current data value, order register value show with display lamp; The analysis instruction module, be used for tabling look-up and obtain little address of the corresponding microprogram of this instruction according to the value of order register, the subscript of little address as the microprogram memory array, find the 1st micro-order of microprogram, code in the micro-order is the control signal of each module, according to micro-instruction code, send control signal for the module that relates to, module is finished function corresponding according to control signal; Display lamp shows micro-order value, little address value, each module control signal lamp value; The execution command module is used for according to the micro-order that obtains, and transmits control signal for each single module montage, it is the controlled signal combination of each single module montage, if control signal is effective, then this module realizes the function of self, and execution result is embodied in the variable of hardware chip.
Described registers group modular simulation unit, general-purpose register send out modular simulation unit, operator block simulation unit, storer and bus module simulation unit, instruction unit simulation unit, microprogram control unit modular simulation unit and sequential and start and stop modular simulation unit adopts the flashActionscript_ exploitation, be issued as the HTML form, the tissue of experimental system adopts HTML hyperlink form to connect.
Embodiment 1: operator block emulation explanation
(1) selects to test three on the list of experiments
(2) enter experiment three experiment instruction documents, the document end is the simulation operations link
(3) click simulation operations, enter arithmetical unit replicating machine interface
(4) on data switch bus connector, click, to operator block bus connector, click again, the data path of white between data switch and operator block bus, occurs
(5) on gauge tap EDR1, click, to the control signal EDR1 of operator block, click again, occur connecting signal wire between two points.On gauge tap EDR2, click, to the control signal EDR2 of operator block, click again, occur connecting signal wire between two points.
After successively the control signal of nominal on the gauge tap being clicked, click corresponding operator block control signal, make to occur connecting signal wire between 10 control signals.
Click pulse button point CCK1 and EDR1CK again, 2 pulse signal lines appear in CCK2 and EDR2CK.
The operation of above-mentioned line does not have sequence requirement, and only requiring between the continuous signal of clicking for 2 times has line, otherwise line can not occur.
(6) can make arithmetical unit finish computing by to data switch and gauge tap different value now.Suppose to finish 22H+33H
(7) operate on data switch, making the binary combination of switch is 00100010, and the switch with the EDR1 correspondence in gauge tap is changed to 0, and other switch is changed to 1.On EDR1CK, click.The animation that occurs signal flow at data switch to the DR1 path.This moment can be with click DR1 hardware chip, watches that numerical value is 00100010 in the chip.
(8) operate on data switch, making the binary combination of switch is 00110011, and the switch with the EDR2 correspondence in gauge tap is changed to 0, and other switch is changed to 1.On EDR2CK, click.The animation that occurs signal flow at data switch to the DR2 path.This moment can be with click DR2 hardware chip, watches that numerical value is 00110011 in the chip.
(9) gauge tap s0～s3 is changed to 1001, CN is changed to 0 with gauge tap.This moment can be with click ALU hardware chip, watches that numerical value is 01010101 in the chip.
(10) the ALU-O gauge tap is changed to 0, to the data bus lamp signal flow animation is arranged by operator block, data light signal shows that the value of ALU hardware chip is 01010101.
(11) can adjust the switch combination of S0～s3 this moment, the other information of ALU chip shows the operation that present ALU chip carries out.Can and click the result that the ALU chip views nonidentity operation by data light signal simultaneously.
Embodiment 2: complete machine emulation explanation
(1) selects to test eight on the list of experiments
(2) enter complete machine experiment instruction explanation document, the document end is the simulation operations link
(3) click the link of complete machine simulation operations, enter the program editing page
(4) loading routine in the input text frame.Suppose that our loading routine is as follows
MOV?A，#55
MOV?R0，#11
ADD?A，R0
(5) pressing submit button, enter the program compilation interface, by clicking instruction fetch, interpretive order button, is the hexadecimal code form with every instruction translation.Code is as follows
00?5F
01?55
02?6C
03?11
04?0C
(6) after the last item instruction translation is finished, enter the replicating machine interface.Can click memory chip, view the code that the back translation obtains.Can click the microprogram control unit chip, view the microprogram of depositing in advance in the machine.
(7) click little single step or single step run button, executive routine.Suppose by little single step run program.
(8) click little single step run button, to memory chip signal flow is arranged from the PC chip, the address addr=0 of internal memory.The address bus pilot lamp is shown as 00000000, and internal memory has signal flow to the IR1 chip, and the data bus pilot lamp is shown as 01011111, and instructing lamp is shown as 01011111.Little address=00H.Have the micro-signal pilot lamp to be shown as 010011011111111111111111 this moment.Control signal lamp PC-O, EIR1, RM, MLD flicker.Finish and get the finger micro-order.
(9) click little single step run button, to the microprogram memory chip signal flow is arranged from the IR1 chip, little address=17H.Little address display lamp is 00010111.The micro-instruction code pilot lamp is 110111011111101111111111.Finish analysis instruction
(10) click little single step run button, to general-purpose register A chip signal flow is arranged from memory chip, memory address addr=1, address bus pilot lamp are 00000001, and the data bus pilot lamp is 01010101.Control signal lamp PC-O, ERA, RM, MLD are effective.Click general-purpose register A chip this moment, and can view the interior numerical value of A is 55H.Finish article one command function, send A-register 55H.
(11) click little single step run button, to memory chip signal flow is arranged from the PC chip, the address addr=2 of internal memory.The address bus pilot lamp is shown as 00000010, and internal memory has signal flow to the IR1 chip, and the data bus pilot lamp is shown as 01101100, and instructing lamp is shown as 01101100.Little address=18H.Have the micro-signal pilot lamp to be shown as 010011011111111111111111 this moment.Control signal lamp PC-O, EIR1, RM, MLD flicker.Finish and get the finger micro-order.
(12) click little single step run button, to the microprogram memory chip signal flow is arranged from the IR1 chip, little address=1BH.Little address display lamp is 00011011.The micro-instruction code pilot lamp is 110111011011111111111111.Finish analysis instruction
(13) click little single step run button, to register R0 chip signal flow is arranged from memory chip, memory address addr=3, address bus pilot lamp are 00000011, and the data bus pilot lamp is 00010001.Control signal lamp PC-O, RM, MLD, WR are effective.Click register R0 chip this moment, and can view the interior numerical value of R0 is 11H.Finish the second command function, send R0 register 11H.
(14) click little single step run button, to memory chip signal flow is arranged from the PC chip, the address addr=4 of internal memory.The address bus pilot lamp is shown as 00000100, and internal memory has signal flow to the IR1 chip, and the data bus pilot lamp is shown as 00001100, and instructing lamp is shown as 00001100.Little address=03H.Have the micro-signal pilot lamp to be shown as 111111111111110011111001 this moment.Control signal lamp PC-O, EIR1, RM, MLD flicker.Finish and get the finger micro-order.
(15) click little single step run button, to the DR1 chip signal flow is arranged from the A chip, can clicking DR1, to view DR1 value be 55H.Control signal lamp ERA, RA-O, RR, EDR1 flicker are arranged.Finish the 1st micro-order of add instruction ADD microprogram.
(16) click little single step run button, little address=04H.Have the micro-signal pilot lamp to be shown as 111111110111111101111001 this moment.Finish the 2nd micro-order of getting add instruction ADD microprogram.
(17) click little single step run button, to the DR2 chip signal flow is arranged from the R0 chip, can clicking DR2, to view DR2 value be 11H.Control signal lamp RR, EDR2 flicker is arranged.Finish the 2nd micro-order of add instruction ADD microprogram.
(18) click little single step run button, little address=05H.Have the micro-signal pilot lamp to be shown as 111111111111101111111001 this moment.Finish the 3rd micro-order of getting add instruction ADD microprogram.
(19) click little single step run button, to the A chip signal flow is arranged from ALU, click ALU views the ALU value and is 66H, and click A chip views the A value and is 66H.Finish the 2nd micro-order of getting add instruction ADD microprogram, also promptly finish the 3rd instruction.
(20) click little single step run button, to memory chip signal flow is arranged from the PC chip, the address addr=5 of internal memory.The address bus pilot lamp is shown as 00000101, and internal memory has signal flow to the IR1 chip, and the data bus pilot lamp is shown as 11111111, and instructing lamp is shown as 11111111.Little address=3FH.Have the micro-signal pilot lamp to be shown as 111111111101111111111111 this moment.Control signal lamp PC-O, EIR1, RM, MLD flicker.Finish and get the finger micro-order.
(21) click little single step run button, machine is shut down without any action.
Claims (2)
1, a kind of " Principles of Computer Composition " simulating experimental system, it is characterized in that: described simulating experimental system comprises single module experiment simulation subsystem and complete machine experiment simulation subsystem, described single module experiment simulation subsystem comprises that registers group modular simulation unit, general-purpose register send out modular simulation unit, operator block simulation unit, storer and bus module simulation unit, instruction unit simulation unit, microprogram control unit modular simulation unit and sequential and start and stop modular simulation unit, and described single module experiment simulation subsystem comprises:
Initialization module, whether as seen to be used to be provided with each object, variable initial value is set, described object comprises hardware chip, operating switch and intermodule information channel, and described variable comprises signal value, the control signal implication of operating switch representative, the direction of information transmission on the signal value, truck of hardware chip value, operating switch; The shift knob detection module is used for detecting for automatic in the flash button member, can excite action, writes code in this action, and judgement is data switch or control signal switch;
The data switch operational module is used for the information flow animation that video data is input to experiment module, and gives the module hardware chip value with data switch value assignment;
The switch motion operational module is used for the definition according to this module by signal, judges whether control signal is effective to experiment module, and as effectively, the function code of execution module is then finished the function of requirement.If not then module is not moved;
Described complete machine experiment simulation subsystem comprises:
Initialization module is used for all objects and variable on the initialization complete machine interface;
The operational mode identification module is used for detecting the operation button, and little single step button or full speed button are pressed in judgement, and the operational mode indexed variable is set;
Instruction fetch module is used for giving internal memory current address value with the value assignment, looks into the internal storage data array according to internal memory current address value, obtains internal memory current data value, and this value is sent to order register; Internal memory current address value, internal memory current data value, order register value show with display lamp;
The analysis instruction module, be used for tabling look-up and obtain little address of the corresponding microprogram of this instruction according to the value of order register, the subscript of little address as the microprogram memory array, find the 1st micro-order of microprogram, code in the micro-order is the control signal of each module, according to micro-instruction code, send control signal for the module that relates to, module is finished function corresponding according to control signal; Display lamp shows micro-order value, little address value, each module control signal lamp value;
The execution command module is used for according to the micro-order that obtains, and transmits control signal for each single module montage, it is the controlled signal combination of each single module montage, if control signal is effective, then this module realizes the function of self, and execution result is embodied in the variable of hardware chip.
2, a kind of " Principles of Computer Composition " as claimed in claim 1 simulating experimental system, it is characterized in that: described registers group modular simulation unit, general-purpose register send out modular simulation unit, operator block simulation unit, storer and bus module simulation unit, instruction unit simulation unit, microprogram control unit modular simulation unit and sequential and start and stop modular simulation unit adopts the flashActionscript_ exploitation, be issued as the HTML form, the tissue of experimental system adopts HTML hyperlink form to connect.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102591776A (en) * | 2011-12-30 | 2012-07-18 | 苏州汉清投资管理有限公司 | System for automatically generating codes |
| CN103295461A (en) * | 2013-05-13 | 2013-09-11 | 西安电子科技大学 | Experimental microprocessor and experimental method for same |
| CN104269098A (en) * | 2014-10-13 | 2015-01-07 | 上海交通大学 | System for enhancing sense of immediacy of network experiment wire connection |
| CN105047044A (en) * | 2015-09-15 | 2015-11-11 | 华北理工大学 | Computer principle practical teaching method |
| CN105930584A (en) * | 2016-04-19 | 2016-09-07 | 安徽大学 | Virtual experiment platform of computer organization and system structure and realization method for virtual experiment platform |
| TWI558148B (en) * | 2015-05-07 | 2016-11-11 | 緯創資通股份有限公司 | Method for showing address information and electronic device using the same |
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| CN1612160A (en) * | 2003-10-31 | 2005-05-04 | 上海科技馆 | Method for stimulating experiment via computer |
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2008
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102591776A (en) * | 2011-12-30 | 2012-07-18 | 苏州汉清投资管理有限公司 | System for automatically generating codes |
| CN103295461A (en) * | 2013-05-13 | 2013-09-11 | 西安电子科技大学 | Experimental microprocessor and experimental method for same |
| CN103295461B (en) * | 2013-05-13 | 2015-06-03 | 西安电子科技大学 | Experimental microprocessor |
| CN104269098A (en) * | 2014-10-13 | 2015-01-07 | 上海交通大学 | System for enhancing sense of immediacy of network experiment wire connection |
| CN104269098B (en) * | 2014-10-13 | 2016-05-25 | 上海交通大学 | Strengthen the system of network experiment line telepresenc |
| TWI558148B (en) * | 2015-05-07 | 2016-11-11 | 緯創資通股份有限公司 | Method for showing address information and electronic device using the same |
| CN105047044A (en) * | 2015-09-15 | 2015-11-11 | 华北理工大学 | Computer principle practical teaching method |
| CN105047044B (en) * | 2015-09-15 | 2018-03-09 | 华北理工大学 | Computer Organization Principles practice teaching method |
| CN105930584A (en) * | 2016-04-19 | 2016-09-07 | 安徽大学 | Virtual experiment platform of computer organization and system structure and realization method for virtual experiment platform |
| CN105930584B (en) * | 2016-04-19 | 2019-03-26 | 安徽大学 | A kind of Virtual Experiment Platform Based and its implementation of computer composition and system structure |
| CN111390908A (en) * | 2020-03-26 | 2020-07-10 | 哈尔滨工业大学 | Webpage-based mechanical arm virtual dragging method |
| CN111390908B (en) * | 2020-03-26 | 2022-05-17 | 哈尔滨工业大学 | Webpage-based mechanical arm virtual dragging method |
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| CN101261783B (en) | 2010-07-07 |
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