CN105930584A - Virtual experiment platform of computer organization and system structure and realization method for virtual experiment platform - Google Patents
Virtual experiment platform of computer organization and system structure and realization method for virtual experiment platform Download PDFInfo
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Abstract
The invention discloses a virtual experiment platform of a computer organization and system structure. The virtual experiment platform comprises a simulation chip toolkit module, a functional part design management module, a simulation functional part component library module, a complete machine design management module and a simulation model machine task management module. The simulation chip toolkit module is used for realizing design of a chip, wherein a chip management module can create, modify or add a chip toolkit configuration file; and a chip storage module can generate the chip according to the chip toolkit configuration file and stores the chip in a chip component library. The functional part design management module can call m chips from the chip component library and splice the chips according to the computer organization and system structure to generate a functional part design configuration file. The simulation functional part component library module is used for storing simulation functional parts generated by loading the functional part design configuration file. According to the virtual experiment platform, a logic component library of the virtual simulation experiment platform and a simulation engine of a system can be constructed from a smallest functional unit chip.
Description
Technical field
The present invention relates to the Virtual Experiment Platform Based technical field of computer, particularly relate to a kind of computer composition with
The Virtual Experiment Platform Based of system structure and its implementation.
Background technology
The design of traditional simulation system platform and realization are due to technological development and the restriction of problem, and present stage can only
Some simple logic of analogue computer bottom architecture and the principle realizing computer part functional part represent.
Native system realizes at the bottom of computer in terms of the visual design and in terms of the logic function two of computer bottom framework
The operation scene reduction of layer parts, it is achieved that the logical device storehouse of Virtual Simulative Experiment platform and the emulation of system
Engine builds, and by the assembling of the communication realizing system parts between each logical device example and complete machine and weight
Build.
Research complication system uses two kinds of methods, and one is to decompose, and two is polymerization.Organic in one complexity of design
Time overall, this system decomposition being become multiple subsystem, each subsystem can resolve into again less subsystem
System, until decomposing the subsystem that function is the most single, then realizes the subsystem that function is the most single
Function；Polymerization is the inverse process decomposed, several subsystems on certain level form one bigger
System.Based on above thinking, computer is divided into arithmetical unit, controller, memorizer, input equipment and defeated
Going out the parts such as equipment, can be sub-divided into the aggregate form of multiple chip for these each parts, chip is exactly
The border that recurrence is decomposed；First realize System on Chip/SoC function during design, and complete communication and the friendship of these chips
Mutually, prepare with recombinating for system is reusable.
The minimum functional unit of native system is chip, sets about design from chip, and each chip is carried out in terms of two
Design of Simulation, one is design shape on visual appearance, and two is the realization of logically design function.Software
Modular simulation design system component is distinguished with logical boundary, copying device can pass through limit
Boundary interacts restructuring, it is achieved analogue system assembly and the customizability of overall design framework.
Summary of the invention
The technical problem existed based on background technology, the present invention proposes a kind of computer composition and system structure
Virtual Experiment Platform Based and its implementation.
In the present invention, described computer includes: arithmetical unit, controller, memorizer, input equipment, output
Equipment, general register, data register, address register, command register, sequence timer,
Data path.
The computer that the present invention proposes forms the Virtual Experiment Platform Based with system structure, including: emulation chip work
Tool tank module, functional units design management module, copying component devices library module, overall design management
Module and phantom machine task management module；
Emulation chip workbox module includes:
Management of software ic module, is used for creating chip workbox configuration file, and adds and amendment chip workbox
Configuration file, described chip workbox configuration file comprises n emulation chip attribute, and described emulation chip belongs to
Property includes: the title of emulation chip, the affiliated type of emulation chip, various pin name, pin number,
Pin coordinate attributes and the menu realizing chip functions, described pin name and described pin coordinate attributes are altogether
With definition emulation chip pin, described emulation chip pin can be divided into data to input according to the characteristic completing function
Pin, data output pins, control signal input pin and control signal output pin；
Chip-stored module, including chip device storehouse, is used for loading chip workbox configuration file, thus raw
Become n emulation chip, and according to the affiliated type of n emulation chip in chip workbox configuration file by institute
State n emulation chip to be respectively stored in described chip device storehouse；
Chip task management module, for the data of emulation chip are inputted, data operation and data export into
Line pipe manage, described emulation chip comprise chip event information memory module, chip event information input module,
Chip event information modified module, chip event information output module and chip event information display module, imitative
On true chip, data-out pin is for receiving in the data output pins on other coupled emulation chips
Output data, according in chip attribute pin coordinate attributes information receive relevant position input data,
Obtained and store in chip event information memory module by chip event information input module, for chip event
Message output module, chip event information modified module and chip event information display module read, and emulate core
The data output pins on sheet data in the chip event information output module sending emulation chip, root
The output data of relevant position are sent according to the pin coordinate attributes information in chip attribute information；
Functional units design management module includes:
Definition simulation calculating device, emulation controller, emulation memory, simulation input device, simulation data set
Standby, emulation general register, emulation data register, emulation address register, emulation instruction register and
Emulation sequence timer is copying parts；
Systematic function part design management module, according to described computer composition and architecture, from chip device
Part storehouse is called m emulation chip, and this m emulation chip is spliced, form a kind of described emulation
Functional part, systematic function part design configuration file, and arrange and preserve the configuration of described functional units design
File, described functional units design configuration file comprises type belonging to copying parts, all m emulation
The chip connection status attribute of chip, wherein by multiplex roles winding displacement emulation chip pin is connected every
Two emulation chips have a chip connection status attribute, and each described chip connection status attribute comprises logical
Cross multiplex roles winding displacement by emulation chip pin be connected the title of two emulation chips, the title of various pin,
Pin number, the coordinate attributes of pin and the two emulation chip are connected to the original position on multiplex roles winding displacement
Pin and multiplex roles winding displacement occupy pin widths；
Functional part memory module, comprises functional part component inventory, sets by loading functional part for storage
The copying parts of meter configuration file generation and copying depositor, join by loading functional units design
Put the described chip connection status attribute of m emulation chip described in file acquisition, thus generate copying portion
Part and copying depositor also carry out classification storage management according to classification；
Copying component task management module, generates imitative by loading copying part design configuration file
True functional part and copying depositor, and defeated to the data of copying parts and copying depositor
Enter, data process and data output is managed, by calling comprise in copying parts various successively
The emulation chip of type carries out data process, thus realizes data flowing on copying parts；
Overall design management module includes:
Phantom machine design management module, according to computer composition and system structure, from copying parts
Component inventory calls m1 copying parts, is connected by multi-interface data path and form on the system bus
Phantom machine, and by composition each copying unit type of phantom machine, quantity and in working area
Two-dimensional position coordinate, and the connection status attribute between each copying parts is saved in phantom machine
In design configurations file；
This connection status attribute described is referred to as functional part connection status attribute, specifically includes by multi-interface data
Path, multi-interface data type of passage, the emulation merit that is connected on system bus by multi-interface data path
The interface coordinate of the multi-interface data path of energy parts or other multi-interface data paths and connection thereof, described system
System bus is the simple concatenation of multi-interface data path；
Phantom machine memory module, for storage by loading phantom machine design configurations file generated
Phantom machine, by loading phantom machine design configurations file, reads and forms described phantom machine
The type of all functional parts, quantity and the two-dimensional position coordinate in working area, generate in working area
All of copying parts, then set up emulation according to the connection status attribute between each copying parts
Data path between functional part connects, and copying parts are constituted a complete phantom machine；
Phantom machine task management module includes:
Phantom machine design of microinstruction module, for the machine instruction set of design simulation model machine, described machine
Device instruction set refer to phantom machine complete data entry operation, data output operation, data access operation,
The command history of the processes such as data operation operation, instruction skip operation so that the standby reality of phantom facility should
With the complete function in meaning, described data entry operation, data output operation, data access operation, number
It is referred to as the execution of machine instruction according to processes such as arithmetic operation, instruction skip operations, described machine instruction is carried out
Sequentially permutation and combination can make phantom machine complete volume of data and process task, described machine instruction suitable
Sequence permutation and combination is referred to as machine instruction sequence；
Microprogram performs control module, produces control signal for microinstruction sequence carries out biological function explore, enters
And the interface triggering copying parts enables relation, coordinate each copying parts and complete the data of stage
Operation, is finally completed the function of corresponding microcommand；
Wherein, emulation chip workbox module, functional units design management module and overall design management module
All run in client computer.
Preferably, chip device storehouse is basic component inventory, logic gate component storehouse, digital device storehouse, multiplex roles
Winding displacement storehouse.
Preferably, when functional part component inventory is copying component warehouse, emulation registers warehouse, emulation
Sequence pulse signal generator warehouse and emulation connect bus warehouse.
Preferably, chip-stored module according to the chip title of n chip in chip workbox configuration file,
Various pin name, pin number, pin coordinate attributes and realize chip functions menu generate chip,
According to the affiliated type of n emulation chip in chip workbox configuration file by described n emulation chip respectively
Store to the classification in chip device storehouse, thus complete the initialization in chip device storehouse.
Preferably, emulation chip attribute information include the title of emulation chip, the affiliated type of emulation chip,
The title of various pins, the quantity of pin and pin coordinate attributes.
Preferably, chip connection status attribute information is comprised and is connected by emulation chip pin by multiplex roles winding displacement
The title of two emulation chips, the title of various pin, pin number, the coordinate attributes of pin and this two
Original position pin that individual emulation chip is connected on multiplex roles winding displacement and multiplex roles winding displacement occupy pin widths.
Preferably, functional part connection status attribute information specifically includes by multi-interface data path, multiplex roles
Data path type, the copying parts being connected on system bus by multi-interface data path or other
The interface coordinate of the multi-interface data path of multi-interface data path and connection thereof.
Preferably, described emulation chip comprises chip event information memory module, chip event information input mould
Block, chip event information modified module, chip event information output module and chip event information display module,
Described event comprises data (data) attribute and data come into force remaining time (remained) attribute, described
Event uses two tuples (data, remained) to represent, when data come into force remaining time be 0 remove number
According to, after the data in chip event information memory module are read, data remaining times of coming into force is 0, only
When in chip event information memory module, the data redundancy entry-into-force time is 0, chip event information input module is
New data can be written to chip event information memory module；
Preferably, described multi-interface data type of passage and interface coordinate definition thereof are as follows:
Preferably, data entry operation described in phantom machine design of microinstruction module, data output operation,
The operation of data access operation, data operation, the realization of instruction skip operation are according to control signal trigger data
Opening of the enable switch of interface, then directly reads the data of storage in relief area, described data input behaviour
Make to be divided into following a few step to complete:
If data remaining times of coming into force is 0 in the relief area that the output port of S1 simulation input device is corresponding,
Then data input switch state status of simulation input device is read the buffering that data-out port is corresponding
Qu Zhong, and to arrange data remaining times of coming into force be 1, represents that this emulation input sets by two tuples (status, 1)
Standby incoming event, if data remaining times of coming into force not is 0 in relief area, enters waiting state, cycle
The described data of monitoring of property come into force remaining time, until this buffer data comes into force, remaining time is 0, at the beginning of completing
The data of step read in operation；
S2, data are successfully read in the relief area corresponding to the output port of simulation input device, will simultaneously
The enable switch of the data-out port of simulation input device is opened, if now relief area on system bus
Data remaining times of coming into force is 0, then incoming event two tuple (status, the 1) meeting in simulation input device
Being entered in the data buffer storage on system bus by data-out port, otherwise entering waiting state, until being
In system bus, data remaining time of coming into force of buffering is 0, simultaneously that the buffer data in simulation input device is raw
Effect subtracts 1 remaining time, and closes the enable switch of the output interface of simulation input device, completes data from peripheral hardware
Reading the process of system bus, described process is by emulating what microprogram control unit sent to simulation input device
Output port enables control signal and triggers；
S3, the input time in the data buffer zone on described system bus is read emulation data register
In R0, first judge buffer data remaining time corresponding with Data Input Interface in emulation data register R0
Whether it is 0, if the data redundancy time of this emulation data register is 0, opens emulation registers data defeated
Two tuples (status, 1) of relief area on system bus are read in emulation data and are posted by the enable switch of incoming interface
In the data buffer zone of the data input correspondence of storage R0, otherwise enter waiting state, until reading successfully,
Then buffer data on system bus is come into force and subtract 1 remaining time, be then shut off the number of emulation data register
Switch according to the enable of input switch and close, complete final data and read emulation data from simulation input device
The process of depositor, described process is made to the input interface of emulation data register by emulating microprogram control unit
Can control signal trigger；
S4, basis and the data path C1 on the output interface being connected to simulation input device, interface coordinate (x1,
Y1), the interface coordinate (x2, y2) that data path C1 is connected with system bus, with emulation data register R0
Data path C2 interface coordinate (x3, y3) being connected, the interface that data path C2 is connected with system bus is sat
Mark (x4, y4), it is possible to determine one from simulation input device to system bus, then from system bus to imitative
A data flow path between true function register R0: (x1, y1), (x2, y2), system bus,
(x4,y4)、(x3,y3)；
Preferably, selective laser sintering module produces control signal according to microprogram, and then triggers copying portion
The interface of part enables, and completes the data manipulation of stage, completes the control letter that the microprogram in each stage produces
Number sequence is referred to as the control field of microcommand, and a machine instruction can a point multistep complete, the most corresponding a plurality of the most micro-
Instruction, the parsing of microcommand takes direct control method, binary each represent making of copying interface
Can indicate, also indicating the address field taking out down hop microcommand, referred to as the lower location field of microcommand, complete
The a plurality of microcommand becoming multistep function is referred to as microprogram.
Preferably, microprogram control unit comprise control memorizer, microinstruction register, micro address register with
And micro-address forms parts.
Preferably, machine instruction set includes a plurality of machine instruction；Control memorizer and there is the attribute of memory space,
Memory space is made up of data buffer zone sequence, can be used to store the microcommand sequence realizing all machine instructions
Row, each data buffer zone controlling memorizer has only address designator in this emulation controller
Attribute, controls each data buffer zone of memorizer for obtaining from this emulation memory Data Input Interface
And store a microcommand, control storage in all data buffer zones of memorizer and realize whole machine instruction
All microcommands, every microcommand is stored in the control memorizer of microprogram control unit, shared storage
Space has address designator attribute and memory space length attribute, and address designator attribute is for controlling memorizer
The numbering of data buffer zone, described numbering is referred to as micro-address, and memory space length attribute is deposited for taking control
The data buffer zone quantity of reservoir；
Deposit in micro address register is that next pending microcommand place controls the address in memorizer
Identifier attribute, micro-address forms parts and is used for producing micro-address of next microcommand, and by this micro-address
It is stored in described micro address register；Microinstruction register comprises several data buffer zones, and size is equal to
Article one, microcommand occupies the length attribute of memory space in controlling memorizer, according to micro-address search microprogram
The address designator attribute of microcommand of storage in controller, takes out this buffer contents and is put into microcommand and deposits
In the data buffer zone of device, detailed process is described as follows:
S1, defined variable i, and initialize i=1；
S2, from emulation memory read i-th machine instruction, if i=1, then address formed parts
This machine instruction is decoded, to initialize micro address register, otherwise directly reads micro address register
Search and control the microcommand that memorizer acquisition is corresponding；
S3, the microcommand feeding microinstruction register storage that will take out, read two from the control field of microprogram
System bit position is used for producing the enable control signal controlling each copying unit interface, reads from lower location field
Take and perform the address of down hop microcommand and be stored in micro address register；
S4, i=i+1, it is judged that whether microprogram has reached the last item microcommand, and if it is order takes
Go out next machine instruction and turn S1 until all machine instructions perform to terminate, if the not up to micro-finger of the last item
Order, then turn S2 and perform next microcommand；
A kind of computer that the present invention proposes forms the Virtual Experiment Platform Based implementation method with system structure, and it is special
Levy and be, comprise the following steps:
S1, emulation chip workbox module is set, comprises management of software ic module, chip-stored module and chip
Task management module, management of software ic module creation revisable chip workbox configuration file initialization are stored in n
The attribute information of individual emulation chip, include along attribute information: the title of emulation chip, the institute of emulation chip
Belong to type, various pin name, pin number, pin coordinate attributes and realize the menu of chip functions,
Chip-stored module is used for loading chip workbox configuration file, thus generates n emulation chip, and according to
In chip workbox configuration file, described n emulation chip is stored by the affiliated type of n emulation chip respectively
In described chip device storehouse, chip task management module is for transporting the data input of emulation chip, data
Calculate and data output is managed；
S2, arrange functional units design management module, comprise systematic function part design management module, function
Parts memory module and copying component task management module, systematic function part design management module according to
Described computer composition and architecture, call m emulation chip from chip device storehouse, imitative by this m
True chip splices, and forms a kind of described copying parts, systematic function part design configuration file,
And arrange and preserve described functional units design configuration file, functional part memory module is for storing by adding
Carry copying parts and copying depositor that functional units design configuration file generates, by loading merit
Energy part design configuration file obtains the described chip connection status attribute of described m emulation chip, thus raw
Become copying parts and copying depositor and carry out classification storage management, copying portion according to classification
The data of copying parts and copying depositor are inputted by part task management module, data process sum
It is managed according to output, enters by calling the various types of emulation chips comprised in copying parts successively
Row data process, thus realize data flowing on copying parts；
S3, arrange overall design management module, comprise phantom machine design management module, phantom machine
Memory module and phantom machine task management module, phantom machine design management module is according to calculating unit
Become and system structure, from copying component devices storehouse, call m1 copying parts, pass through multiplex roles
Data path connect on the system bus composition phantom machine, and by composition phantom machine respectively emulate merit
Can unit type, between quantity and the two-dimensional position coordinate in working area, and each copying parts
Connection status attribute is saved in phantom machine design configurations file, and phantom machine memory module is used for depositing
Store up the phantom machine by loading phantom machine design configurations file generated, phantom machine task management
Module comprises phantom machine design of microinstruction module and microprogram performs control module, the micro-finger of phantom machine
Order design module performs control module for micro-for the machine instruction set of design simulation model machine, microprogram
Job sequence carries out biological function explore and produces control signal, and then the interface triggering copying parts enables relation,
Coordinate each copying parts and complete the data manipulation of stage, be finally completed the function of corresponding microcommand.
Preferably, copying parts are the set of emulation chip, have data input, data operation sum
According to output attribute, i.e. there is the attribute of emulation chip, can by copying parts and emulation chip according to
Join algorithm carries out being spliced into bigger copying parts, therefore by copying portion bigger described in composition
The unit of part is referred to as chip, and join algorithm generates copying parts as follows:
S1, defined variable i, and initialize i=1；
S2, copying component devices library module obtain i-th by loading functional units design configuration file
The connection status of emulation chip is supplied to the chip event information input module of i-th emulation chip；
S3, i-th emulation chip chip event information input module according to i-th connection status obtain with
The k that self is connectediIndividual emulation chip, and by kiThe output letter of the chip event information output module of individual emulation chip
Breath is stored in the chip event information memory module of i-th emulation chip；
S4, i-th emulation chip chip event information modified module from the event information of this i-th chip
After reading data message in memory module and processing, chip event information of being restored by operation result stores
In module；
S5, i-th emulation chip chip event information output module from chip event information memory module
Read operation result the output information as self；
S6, the value of i+1 is assigned to i, and judges whether sum (n1+n2+ ...+ni)≤m sets up,
If setting up, then performing S2, otherwise, representing the generation having completed copying parts, wherein, ni represents the
I emulation chip or copying parts comprise the quantity of emulation chip；
Preferably, copying parts have one or more operational data input interfaces, have 1 or many
Individual control signal input interface, has one or more operational data output interfaces, has defeated with operational data
Incoming interface, operational data output interface and the data buffer zone of control signal input interface equal number, each
Copying unit interface all forms mapping relations one by one, referred to as buffer interface with a data buffer zone and reflects
Penetrate relation, corresponding number can be found from copying unit interface by these buffer interface mapping relations
According to relief area；
Preferably, data buffer zone can be divided into data input buffer district, data defeated according to the data type of storage
Go out relief area and control signal relief area；
Preferably, emulation data path includes 1 data storage buffer and n copying unit interface,
Wherein, the Data Input Interface of n=copying parts, data output interface and control signal input interface number
The summation of amount.
Preferably, the foundation of data interaction is defined as interface and connects rules of interaction, and it is mutual that it includes that interface connects
Rule 1 and interface connect rules of interaction 2；
Interface connection rules of interaction 1:
(1) each is connected by Data Input Interface, data output interface and control signal input interface
The copying parts being connected on data path, each operational data input interface therein, according to each fortune
Calculate the enable switch of Data Input Interface；
(2) if the enable switch of this operational data input interface is for open mode, this operational data inputs
Data doublet in relief area on system bus can be replicated by interface according to buffer interface mapping relations
In the data input buffer district corresponding to operational data input interface；
(3) otherwise, do not perform；
Interface connection rules of interaction 2:
(1) each is connected by Data Input Interface, data output interface and control signal input interface
The copying parts being connected on data path, each operational data output interface therein, can be according to computing
Enable switch in data output interface；
(2) if the enable of output interface switchs for open mode constantly, this operational data output interface can root
According to buffer interface mapping relations, by the number on the data output buffer corresponding to operational data output interface
It is sent in the data storage buffer on system bus according to two tuples；
(3) otherwise, do not perform.
A kind of computer that the present invention proposes forms the Virtual Experiment Platform Based with system structure, including: emulation core
Sheet workbox module, functional units design management module, overall design management module；Computer includes: fortune
Calculate device, controller, memorizer, input equipment, outut device, general register, data register,
Location depositor, command register, sequence timer, data path.
In the present invention, emulation chip workbox module is for realizing the design to chip, wherein management of software ic mould
Block can arrange, can revise chip workbox configuration file；Chip-stored module can configure according to chip workbox
File generated chip also stores in chip device storehouse.The emulation core comprised in functional units design management module
Sheet task management module can call m chip from chip device storehouse, and ties with system according to computer composition
Structure is combined into copying parts.The storage of functional part memory module is by loading functional units design configuration literary composition
The copying parts that part generates；The phantom machine design management module energy that overall design management module comprises
Enough from functional part component inventory, call all of copying parts generated.Overall design management mould
The phantom machine memory module that block comprises, for stress model machine design configurations file acquisition copying portion
The connection status of part, thus generate phantom machine, phantom machine task management module can design and simulation mould
The machine instruction set of type machine, and by microprogram control unit, microinstruction sequence is carried out biological function explore and complete phase
Answer the function of microcommand, perform each machine instruction, until completing the execution process to all microcommands.
In the present invention, set about from minimum functional unit chip, design aspect and from meter from visual appearance
Logic function two aspect of calculation machine bottom framework is respectively to computer composition and the Virtual Experiment Platform Based of system structure
It is designed and realizes, it is achieved that the logical device storehouse of Virtual Simulative Experiment platform and the simulation engine structure of system
Build, and by the communication realizing system parts between each logical device example and the assembling of complete machine and reconstruction.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of a kind of computer composition and the Virtual Experiment Platform Based of system structure；
Fig. 2 is data entry operation flow chart.
Detailed description of the invention
As it is shown in figure 1, a kind of computer composition that Fig. 1 is the present invention to be proposed and the virtual experimental of system structure
The structured flowchart of platform.
With reference to Fig. 1, a kind of computer composition that the present invention proposes and the Virtual Experiment Platform Based of system structure, wrap
Include: emulation chip workbox module, functional units design management module, overall design management module；
Emulation chip workbox module includes:
Management of software ic module, is used for creating chip workbox configuration file, and adds and amendment chip workbox
Configuration file, described chip workbox configuration file comprises n emulation chip attribute, and described emulation chip belongs to
Property includes: the title of emulation chip, the affiliated type of emulation chip, various pin name, pin number,
Pin coordinate attributes and the menu realizing chip functions, described pin name and described pin coordinate attributes are altogether
With definition emulation chip pin, described emulation chip pin can be divided into data to input according to the characteristic completing function
Pin, data output pins, control signal input pin and control signal output pin；
Chip-stored module, including chip device storehouse, is used for loading chip workbox configuration file, thus raw
Become n emulation chip, and according to the affiliated type of n emulation chip in chip workbox configuration file by institute
State n emulation chip to be respectively stored in described chip device storehouse；
Chip task management module, for the data of emulation chip are inputted, data operation and data export into
Line pipe manage, described emulation chip comprise chip event information memory module, chip event information input module,
Chip event information modified module, chip event information output module and chip event information display module, imitative
On true chip, data-out pin is for receiving in the data output pins on other coupled emulation chips
Output data, according in chip attribute pin coordinate attributes information receive relevant position input data,
Obtained and store in chip event information memory module by chip event information input module, for chip event
Message output module, chip event information modified module and chip event information display module read, and emulate core
The data output pins on sheet data in the chip event information output module sending emulation chip, root
The output data of relevant position are sent according to the pin coordinate attributes information in chip attribute information；
Functional units design management module includes:
Definition simulation calculating device, emulation controller, emulation memory, simulation input device, simulation data set
Standby, emulation general register, emulation data register, emulation address register, emulation instruction register and
Emulation sequence timer is copying parts；
Systematic function part design management module, according to described computer composition and architecture, from chip device
Part storehouse is called m emulation chip, and this m emulation chip is spliced, form a kind of described emulation
Functional part, systematic function part design configuration file, and arrange and preserve the configuration of described functional units design
File, described functional units design configuration file comprises type belonging to copying parts, all m emulation
The chip connection status attribute of chip, wherein by multiplex roles winding displacement emulation chip pin is connected every
Two emulation chips have a chip connection status attribute, and each described chip connection status attribute comprises logical
Cross multiplex roles winding displacement by emulation chip pin be connected the title of two emulation chips, the title of various pin,
Pin number, the coordinate attributes of pin and the two emulation chip are connected to the original position on multiplex roles winding displacement
Pin and multiplex roles winding displacement occupy pin widths；
Functional part memory module, comprises functional part component inventory, sets by loading functional part for storage
The copying parts of meter configuration file generation and copying depositor, join by loading functional units design
Put the described chip connection status attribute of m emulation chip described in file acquisition, thus generate copying portion
Part and copying depositor also carry out classification storage management according to classification；
Copying component task management module, generates imitative by loading copying part design configuration file
True functional part and copying depositor, and defeated to the data of copying parts and copying depositor
Enter, data process and data output is managed, by calling comprise in copying parts various successively
The emulation chip of type carries out data process, thus realizes data flowing on copying parts；
Overall design management module includes:
Phantom machine design management module, according to computer composition and system structure, from copying parts
Component inventory calls m1 copying parts, is connected by multi-interface data path and form on the system bus
Phantom machine, and by composition each copying unit type of phantom machine, quantity and in working area
Two-dimensional position coordinate, and the connection status attribute between each copying parts is saved in phantom machine
In design configurations file；
This connection status attribute described is referred to as functional part connection status attribute, specifically includes by multi-interface data
Path, multi-interface data type of passage, the emulation merit that is connected on system bus by multi-interface data path
The interface coordinate of the multi-interface data path of energy parts or other multi-interface data paths and connection thereof, described system
System bus is the simple concatenation of multi-interface data path；
Phantom machine memory module, for storage by loading phantom machine design configurations file generated
Phantom machine, by loading phantom machine design configurations file, reads and forms described phantom machine
The type of all functional parts, quantity and the two-dimensional position coordinate in working area, generate in working area
All of copying parts, then set up emulation according to the connection status attribute between each copying parts
Data path between functional part connects, and copying parts are constituted a complete phantom machine；
Phantom machine task management module includes:
Phantom machine design of microinstruction module, for the machine instruction set of design simulation model machine, described machine
Device instruction set refer to phantom machine complete data entry operation, data output operation, data access operation,
The command history of the processes such as data operation operation, instruction skip operation so that the standby reality of phantom facility should
With the complete function in meaning, described data entry operation, data output operation, data access operation, number
It is referred to as the execution of machine instruction according to processes such as arithmetic operation, instruction skip operations, described machine instruction is carried out
Sequentially permutation and combination can make phantom machine complete volume of data and process task, described machine instruction suitable
Sequence permutation and combination is referred to as machine instruction sequence；
Microprogram performs control module, produces control signal for microinstruction sequence carries out biological function explore, enters
And the interface triggering copying parts enables relation, coordinate each copying parts and complete the data of stage
Operation, is finally completed the function of corresponding microcommand；
Wherein, emulation chip workbox module, functional units design management module and overall design management module
All run in client computer.
In present embodiment, chip device storehouse be basic component inventory, logic gate component storehouse, digital device storehouse,
Multiplex roles winding displacement storehouse.
In present embodiment, functional part component inventory be copying component warehouse, emulation registers warehouse,
Emulation time series pulse signals generator warehouse and emulation connect bus warehouse.
In present embodiment, chip-stored module is according to the chip of n chip in chip workbox configuration file
Title, various pin name, pin number, pin coordinate attributes and realize chip functions menu generate
Chip, according to the affiliated type of n emulation chip in chip workbox configuration file by described n emulation core
Sheet stores respectively to the classification in chip device storehouse, thus completes the initialization in chip device storehouse.
In present embodiment, emulation chip attribute information include the title of emulation chip, emulation chip affiliated
Type, the title of various pin, the quantity of pin and pin coordinate attributes.
In present embodiment, chip connection status attribute information is comprised and is drawn by emulation chip by multiplex roles winding displacement
Foot be connected the title of two emulation chips, the title of various pin, pin number, the coordinate attributes of pin
The original position pin and the occupying of multiplex roles winding displacement that are connected on multiplex roles winding displacement with the two emulation chip are drawn
Foot width.
In present embodiment, functional part connection status attribute information specifically include by multi-interface data path,
Multi-interface data type of passage, the copying parts being connected on system bus by multi-interface data path
Or the interface coordinate of the multi-interface data path of other multi-interface data paths and connection thereof.
In present embodiment, described emulation chip comprises chip event information memory module, chip event information
Input module, chip event information modified module, chip event information output module and chip event information are aobvious
Show that module, described event comprise data (data) attribute and data come into force remaining time (remained) attribute,
Described event uses two tuples (data, remained) to represent, when data remaining times of coming into force is 0 removing
Data, after the data in chip event information memory module are read, data remaining times of coming into force is 0, only
There is the chip event information input module when the data redundancy entry-into-force time is 0 in chip event information memory module
New data could be written to chip event information memory module；
In present embodiment, described multi-interface data type of passage and interface coordinate definition thereof are as follows:
In present embodiment, data entry operation described in phantom machine design of microinstruction module, data are defeated
Go out operation, data access operation, data operation operates, the realization of instruction skip operation is according to control signal
Opening of the enable switch of trigger data interface, then directly reads the data of storage, described number in relief area
It is divided into following a few step to complete according to input operation:
If data remaining times of coming into force is 0 in the relief area that the output port of S1 simulation input device is corresponding,
Then data input switch state status of simulation input device is read the buffering that data-out port is corresponding
Qu Zhong, and to arrange data remaining times of coming into force be 1, represents this simulation input device by two tuples (status, 1)
Incoming event, if data remaining times of coming into force not is 0 in relief area, enters waiting state, periodically
Monitoring described data to come into force remaining time, until this buffer data comes into force, remaining time is 0, completes preliminary
Data read in operation；
S2, data are successfully read in the relief area corresponding to the output port of simulation input device, will simultaneously
The enable switch of the data-out port of simulation input device is opened, if now relief area on system bus
Data remaining times of coming into force is 0, then incoming event two tuple (status, 1) in simulation input device can be led to
Cross in the data buffer storage that data-out port enters on system bus, otherwise enter waiting state, until system
In bus, data remaining time of coming into force of buffering is 0, is come into force by the buffer data in simulation input device simultaneously
Remaining time subtracts 1, and closes the enable switch of the output interface of simulation input device, completes data and reads from peripheral hardware
Get the process of system bus, described process by emulate microprogram control unit to simulation input device send defeated
Go out port and enable control signal triggering；
S3 is as in figure 2 it is shown, read imitative by the input time in the data buffer zone on described system bus
In true data depositor R0, first judge buffering corresponding with Data Input Interface in emulation data register R0
Whether district's data redundancy time is 0, if the data redundancy time of this emulation data register is 0, opens imitative
Two tuples (status, 1) of relief area on system bus are read by the enable switch of true register data input interface
Enter in the data buffer zone of data input correspondence of emulation data register R0, otherwise enter waiting state, directly
To reading successfully, then being come into force by buffer data on system bus subtracts 1 remaining time, is then shut off emulating number
Close according to the enable switch of the data input switch of depositor, complete final data and read from simulation input device
Getting the process of emulation data register, described process is by emulating microprogram control unit to emulation data register
Input interface enable control signal trigger；
S4, basis and the data path C1 on the output interface being connected to simulation input device, interface coordinate (x1,
Y1), the interface coordinate (x2, y2) that data path C1 is connected with system bus, with emulation data register R0
Data path C2 interface coordinate (x3, y3) being connected, the interface coordinate that data path C2 is connected with system bus
(x4, y4), it is possible to determine one from simulation input device to system bus, then from system bus to emulation merit
Can a data flow path between depositor R0: (x1, y1), (x2, y2), system bus, (x4, y4),
(x3,y3)；
In present embodiment, selective laser sintering module produces control signal according to microprogram, and then triggers emulation
The interface of functional part enables, and completes the data manipulation of stage, completes the microprogram generation in each stage
Control signal sequence is referred to as the control field of microcommand, and a machine instruction can a point multistep complete, the most corresponding
A plurality of microcommand, the parsing of microcommand takes direct control method, binary each represent copying and connect
The enabler flags of mouth, also indicates the address field taking out down hop microcommand, the referred to as lower location word of microcommand
Section, a plurality of microcommand completing multistep function is referred to as microprogram.
In present embodiment, microprogram control unit comprises control memorizer, microinstruction register, micro-address are posted
Storage and micro-address form parts.
In present embodiment, machine instruction set includes a plurality of machine instruction；Control memorizer and there is memory space
Attribute, memory space is made up of data buffer zone sequence, can be used to store and realizes all machine instructions
Microinstruction sequence, each data buffer zone controlling memorizer has only ground in this emulation controller
Location identifier attribute, controls each data buffer zone of memorizer for connecing from the input of these emulation memory data
Obtain and store a microcommand in Kou, control storage in all data buffer zones of memorizer and realize whole machine
All microcommands of device instruction, every microcommand is stored in the control memorizer of microprogram control unit, shared
Memory space there is address designator attribute and memory space length attribute, address designator attribute for control
The numbering of the data buffer zone of memorizer processed, described numbering is referred to as micro-address, and memory space length attribute is for accounting for
By the data buffer zone quantity controlling memorizer；
Deposit in micro address register is that next pending microcommand place controls the address in memorizer
Identifier attribute, micro-address forms parts and is used for producing micro-address of next microcommand, and by this micro-address
It is stored in described micro address register；Microinstruction register comprises several data buffer zones, and size is equal to
Article one, microcommand occupies the length attribute of memory space in controlling memorizer, according to micro-address search microprogram
The address designator attribute of microcommand of storage in controller, takes out this buffer contents and is put into microcommand and deposits
In the data buffer zone of device, detailed process is described as follows:
S1, defined variable i, and initialize i=1；
S2, from emulation memory read i-th machine instruction, if i=1, then address formed parts pair
This machine instruction decodes, and to initialize micro address register, otherwise directly reads micro address register and looks into
Look for and control the microcommand that memorizer acquisition is corresponding；
S3, the microcommand feeding microinstruction register storage that will take out, read two from the control field of microprogram
System bit position is used for producing the enable control signal controlling each copying unit interface, reads from lower location field
Perform the address of down hop microcommand and be stored in micro address register；
S4, i=i+1, it is judged that whether microprogram has reached the last item microcommand, if it is takes out in turn
Next machine instruction turns S1 until all machine instructions perform to terminate, if not up to the last item microcommand,
Then turn S2 and perform next microcommand；
A kind of computer that the present invention proposes forms the Virtual Experiment Platform Based implementation method with system structure, and it is special
Levy and be, comprise the following steps:
S1, emulation chip workbox module is set, comprises management of software ic module, chip-stored module and chip
Task management module, management of software ic module creation revisable chip workbox configuration file initialization are stored in n
The attribute information of individual emulation chip, include along attribute information: the title of emulation chip, the institute of emulation chip
Belong to type, various pin name, pin number, pin coordinate attributes and realize the menu of chip functions,
Chip-stored module is used for loading chip workbox configuration file, thus generates n emulation chip, and according to
In chip workbox configuration file, described n emulation chip is stored by the affiliated type of n emulation chip respectively
In described chip device storehouse, chip task management module is for transporting the data input of emulation chip, data
Calculate and data output is managed；
S2, arrange functional units design management module, comprise systematic function part design management module, function
Parts memory module and copying component task management module, systematic function part design management module according to
Described computer composition and architecture, call m emulation chip from chip device storehouse, imitative by this m
True chip splices, and forms a kind of described copying parts, systematic function part design configuration file,
And arrange and preserve described functional units design configuration file, functional part memory module is for storing by adding
Carry copying parts and copying depositor that functional units design configuration file generates, by loading merit
Energy part design configuration file obtains the described chip connection status attribute of described m emulation chip, thus raw
Become copying parts and copying depositor and carry out classification storage management, copying portion according to classification
The data of copying parts and copying depositor are inputted by part task management module, data process sum
It is managed according to output, enters by calling the various types of emulation chips comprised in copying parts successively
Row data process, thus realize data flowing on copying parts；
S3, arrange overall design management module, comprise phantom machine design management module, phantom machine
Memory module and phantom machine task management module, phantom machine design management module is according to calculating unit
Become and system structure, from copying component devices storehouse, call m1 copying parts, pass through multiplex roles
Data path connect on the system bus composition phantom machine, and by composition phantom machine respectively emulate merit
Can unit type, between quantity and the two-dimensional position coordinate in working area, and each copying parts
Connection status attribute is saved in phantom machine design configurations file, and phantom machine memory module is used for depositing
Store up the phantom machine by loading phantom machine design configurations file generated, phantom machine task management
Module comprises phantom machine design of microinstruction module and microprogram performs control module, the micro-finger of phantom machine
Order design module performs control module for micro-for the machine instruction set of design simulation model machine, microprogram
Job sequence carries out biological function explore and produces control signal, and then the interface triggering copying parts enables relation,
Coordinate each copying parts and complete the data manipulation of stage, be finally completed the function of corresponding microcommand.
In present embodiment, copying parts are the set of emulation chip, have data input, data fortune
Calculate and data output attribute, i.e. there is the attribute of emulation chip, can be by copying parts and emulation core
Sheet carries out being spliced into bigger copying parts according to join algorithm, therefore by emulation bigger described in composition
The unit of functional part is referred to as chip, and join algorithm generates copying parts as follows:
S1, defined variable i, and initialize i=1；
S2, copying component devices library module are imitated by loading functional units design configuration file acquisition i-th
The connection status of true chip is supplied to the chip event information input module of i-th emulation chip；
S3, the chip event information input module of i-th emulation chip obtain and oneself according to i-th connection status
The k that body is connectediIndividual emulation chip, and by kiThe output information of the chip event information output module of individual emulation chip
It is stored in the chip event information memory module of i-th emulation chip；
S4, the chip event information modified module of i-th emulation chip are deposited from the event information of this i-th chip
After storage module reading data message and processing, chip event information that operation result is restored storage mould
In block；
S5, the chip event information output module of i-th emulation chip are read from chip event information memory module
Take operation result the output information as self；
S6, the value of i+1 is assigned to i, and judges whether sum (n1+n2+ ...+ni)≤m sets up, if becoming
Vertical, then perform S2, otherwise, represent the generation having completed copying parts, wherein, ni represents i-th
Emulation chip or copying parts comprise the quantity of emulation chip；
Preferably, copying parts have one or more operational data input interfaces, have 1 or many
Individual control signal input interface, has one or more operational data output interfaces, has defeated with operational data
Incoming interface, operational data output interface and the data buffer zone of control signal input interface equal number, each
Copying unit interface all forms mapping relations one by one, referred to as buffer interface with a data buffer zone and reflects
Penetrate relation, corresponding number can be found from copying unit interface by these buffer interface mapping relations
According to relief area；
In present embodiment, data buffer zone according to storage data type can be divided into data input buffer district,
Data output buffer and control signal relief area；
In present embodiment, emulation data path includes 1 data storage buffer and n copying portion
Part interface, wherein, Data Input Interface, data output interface and the control signal of n=copying parts are defeated
The summation of incoming interface quantity.
In present embodiment, the foundation of data interaction is defined as interface and connects rules of interaction, and it includes that interface is even
Connect rules of interaction 1 and interface connects rules of interaction 2；
Interface connection rules of interaction 1:
(1) each is connected by Data Input Interface, data output interface and control signal input interface
The copying parts being connected on data path, each operational data input interface therein, according to each fortune
Calculate the enable switch of Data Input Interface；
(2) if the enable switch of this operational data input interface is for open mode, this operational data inputs
Data doublet in relief area on system bus can be replicated by interface according to buffer interface mapping relations
In the data input buffer district corresponding to operational data input interface；
(3) otherwise, do not perform；
Interface connection rules of interaction 2:
(1) each is connected by Data Input Interface, data output interface and control signal input interface
The copying parts being connected on data path, each operational data output interface therein, can be according to computing
Enable switch in data output interface；
(2) if the enable of output interface switchs for open mode constantly, this operational data output interface can root
According to buffer interface mapping relations, by the number on the data output buffer corresponding to operational data output interface
It is sent in the data storage buffer on system bus according to two tuples；
(3) otherwise, do not perform.
Overall design management module includes: phantom machine design management module, phantom machine memory module
With phantom machine task management module.Phantom machine design management module is adjusted from copying part library
With m1 copying parts, copying parts are the set of emulation chip, have the attribute of emulation chip.
Phantom machine design management module, according to computer composition and system structure, from copying parts
Component inventory calls m1 copying parts, is connected by multi-interface data path and form on the system bus
Phantom machine, and by composition each copying unit type of phantom machine, quantity and in working area
Two-dimensional position coordinate, and the connection status attribute between each copying parts is saved in phantom machine
In design configurations file, this connection status attribute described is referred to as functional part connection status attribute, specifically includes
By multi-interface data path, multi-interface data type of passage, to be connected to system by multi-interface data path total
Copying parts on line or the interface of the multi-interface data path of other multi-interface data paths and connection thereof
Coordinate, described system bus is the simple concatenation of multi-interface data path；
It should be noted that in present embodiment, phantom machine memory module is by loading phantom machine
Design configurations file, read composition the type of all functional parts of described phantom machine, quantity and
Two-dimensional position coordinate in working area, generates all of copying parts, then according to each in working area
Connection status attribute between copying parts is set up the data path between copying parts and is connected, will
Copying parts constitute a complete phantom machine, and phantom facility are for von Karman computer
The basic function composition of framework.
Phantom machine task management module includes that phantom machine design of microinstruction module and microprogram perform control
Molding block.In present embodiment, design of microinstruction module is used for the machine instruction set of design simulation model machine,
Machine instruction set includes a plurality of machine instruction；
Machine instruction is emulation controller for producing control signal and being delivered to other through emulation data path and imitate
In true functional part, it is used for the enable to other copying parts and has controlled, to realize machine instruction
Function.
The function of machine instruction is divided into what multistep completed, and the corresponding microcommand of each step, is to use microcommand
Sequence realizes, and an element of microinstruction sequence is referred to as microcommand, and microinstruction sequence is stored in emulation shred
In sequence controller, often perform a machine instruction and be converted to perform one section of microinstruction sequence, referred to as microprogram.
Emulation microprogram control unit comprises control memorizer, microinstruction register, micro address register and micro-
Address forms parts.
Controlling memorizer and have the attribute of memory space, memory space is made up of data buffer zone sequence, permissible
Being used for storing the microinstruction sequence realizing all machine instructions, each data buffer zone controlling memorizer exists
Having only address designator attribute in this emulation controller, each data buffer zone controlling memorizer is used
In obtaining and store a microcommand from this emulation memory Data Input Interface, control all of memorizer
In data buffer zone, storage realizes all microcommands of whole machine instruction.
Address designator attribute includes storing position attribution and memory space length attribute, and storage position attribution is
Controlling the numbering of the data buffer zone of memorizer, memory space length attribute is the data taking and controlling memorizer
Number.
Deposit in micro address register is that next pending microcommand place controls the address in memorizer
Identifier attribute, micro-address i.e. microcommand is the numbering of data buffer zone, address designator in controlling memorizer
Attribute is equal to controlling the numbering of a data buffer zone in memorizer.
Micro-address forms parts and is used for producing micro-address of next microcommand, and this micro-address is stored in institute
State in micro address register.
Microinstruction register comprises several data buffer zones, and size is controlling memorizer equal to a microcommand
In occupy the length attribute of memory space, according to the microcommand of storage in micro-address search microprogram control unit
Address designator attribute, takes out this buffer contents and is put in the data buffer zone of microinstruction register.
For the realization of every machine instruction function, microprogram control unit carries out biological function explore to microinstruction sequence
Produce control signal, and then the interface triggering copying parts enables relation, coordinates each copying parts
Completing the data manipulation of stage, be finally completed the function of corresponding microcommand, this process can be expressed as according to micro-
The operational data input interface of curriculum offering each copying parts of control field of instruction, operational data are defeated
The Map Interface selected state in control signal relief area corresponding to outgoing interface and control signal input interface and
The non-selected state of Map Interface, then connects rules of interaction 1 according to interface and interface connects rules of interaction 2 and enters
Row operation, is completed data and is completed at each copying parts, copying depositor by emulation data path
And emulation sequence timer between mutual.
In present embodiment, the time completing machine instruction is referred to as the machine cycle, to complete to take in the machine cycle
Instruction process, process of fetching data and execution process, the time that these three processes spend be called the fetching cycle,
Peek cycle and the cycle of execution.
The fetching cycle, the peek cycle and perform the cycle time length by emulating sequence timer control,
Emulation sequence timer can be periodically by the fortune of this emulation sequence timer in time interval T
Calculate data output interface, connect rules of interaction 2 according to interface and send time sequential pulse numerical value, then start each
The execution of individual microcommand.
Execution process is to be determined by the control field of microcommand, and the content of control field includes all of emulation merit
The Map Interface choosing of the chip selection signal interface of energy parts, copying depositor and emulation sequence timer
Middle state and the non-selected status information of Map Interface, and the binary system then generated according to field direct compilation regulation
Sequence, for controlling copying parts, copying depositor and the computing of emulation sequence timer
The sheet of Data Input Interface or operational data output interface selects state.
Under each period of time T of emulation sequence timer, microprogram control unit is from controlling memorizer
Read microprogram, go to control other copying parts by the control field in microcommand and copying is deposited
The sheet choosing of device enables, and finds next microcommand that will perform by the lower location field of microcommand, until
Complete the execution process of all microcommands corresponding to a machine instruction.
Above, the only present invention preferably detailed description of the invention, but protection scope of the present invention is not limited to
This, any those familiar with the art is in the technical scope that the invention discloses, according to the present invention
Technical scheme and inventive concept equivalent or change in addition, all should contain in protection scope of the present invention
Within.
Claims (10)
1. computer composition and a Virtual Experiment Platform Based for system structure, described computer includes: arithmetical unit, controller, memorizer, input equipment, outut device, general register, data register, address register, command register, sequence timer, data path；It is characterized in that, including: emulation chip workbox module, functional units design management module, overall design management module；
Emulation chip workbox module includes:
Management of software ic module, for creating chip workbox configuration file, and add and amendment chip workbox configuration file, described chip workbox configuration file comprises n emulation chip attribute, described emulation chip attribute includes: the title of emulation chip, the affiliated type of emulation chip, various pin name, pin number, pin coordinate attributes and the menu realizing chip functions, described pin name and described pin coordinate attributes common definition emulation chip pin, described emulation chip pin can be divided into data-out pin according to the characteristic completing function, data output pins, control signal input pin and control signal output pin；
Chip-stored module, including chip device storehouse, for loading chip workbox configuration file, thus generate n emulation chip, and according to the affiliated type of n emulation chip in chip workbox configuration file, described n emulation chip is respectively stored in described chip device storehouse；
nullChip task management module，For the data of emulation chip are inputted、Data operation and data output are managed，Described emulation chip comprises chip event information memory module、Chip event information input module、Chip event information modified module、Chip event information output module and chip event information display module，On emulation chip, data-out pin is for receiving the output data in the data output pins on other coupled emulation chips，The input data of relevant position are received according to the pin coordinate attributes information in chip attribute，Obtained and store by chip event information input module in chip event information memory module，For chip event information output module、Chip event information modified module and chip event information display module read，The data output pins on emulation chip data in the chip event information output module sending emulation chip，The output data of relevant position are sent according to the pin coordinate attributes information in chip attribute information；
Functional units design management module includes:
Definition simulation calculating device, emulation controller, emulation memory, simulation input device, simulation data equipment, emulation general register, emulation data register, emulation address register, emulation instruction register and emulation sequence timer are copying parts；
nullSystematic function part design management module，According to described computer composition and architecture，M emulation chip is called from chip device storehouse，And this m emulation chip is spliced，Form a kind of described copying parts，Systematic function part design configuration file，And arrange and preserve described functional units design configuration file，Described functional units design configuration file comprises type belonging to copying parts、The chip connection status attribute of all m emulation chips，Wherein by a multiplex roles winding displacement, each two emulation chip that emulation chip pin is connected had a chip connection status attribute，Each described chip connection status attribute comprises the title of two emulation chips being connected by emulation chip pin by multiplex roles winding displacement、The title of various pins、Pin number、Original position pin that the coordinate attributes of pin and the two emulation chip are connected on multiplex roles winding displacement and multiplex roles winding displacement occupy pin widths；
Functional part memory module, comprise functional part component inventory, the copying parts generated by loading functional units design configuration file for storage and copying depositor, obtain the described chip connection status attribute of described m emulation chip by loading functional units design configuration file, thus generate copying parts and copying depositor and carry out classification storage management according to classification；
Copying component task management module, copying parts and copying depositor is generated by loading copying part design configuration file, and data input, data process and the data output to copying parts and copying depositor is managed, carry out data process by calling the various types of emulation chips comprised in copying parts successively, thus realize data flowing on copying parts；
Overall design management module includes:
Phantom machine design management module, according to computer composition and system structure, m1 copying parts are called from copying component devices storehouse, composition phantom machine on the system bus is connected by multi-interface data path, and composition each copying unit type of phantom machine, connection status attribute between quantity and the two-dimensional position coordinate in working area, and each copying parts are saved in phantom machine design configurations file；
This connection status attribute described is referred to as functional part connection status attribute, specifically including the interface coordinate of multi-interface data path by multi-interface data path, multi-interface data type of passage, the copying parts being connected on system bus by multi-interface data path or other multi-interface data paths and connection thereof, described system bus is the simple concatenation of multi-interface data path；
Phantom machine memory module, for storage by loading the phantom machine of phantom machine design configurations file generated, by loading phantom machine design configurations file, read the composition type of all functional parts of described phantom machine, quantity and the two-dimensional position coordinate in working area, all of copying parts are generated in working area, then set up the data path between copying parts according to the connection status attribute between each copying parts to connect, copying parts are constituted a complete phantom machine；
Phantom machine task management module includes:
Phantom machine design of microinstruction module, machine instruction set for design simulation model machine, described machine instruction set refers to that phantom machine completes data entry operation, data output operation, data access operation, data operation operates, the command history of the processes such as instruction skip operation, make the complete function on the standby actual application value of phantom facility, described data entry operation, data output operation, data access operation, data operation operates, the processes such as instruction skip operation are referred to as the execution of machine instruction, described machine instruction carries out order permutation and combination can make phantom machine complete volume of data process task, the order permutation and combination of described machine instruction is referred to as machine instruction sequence；
Microprogram performs control module, produces control signal for microinstruction sequence carries out biological function explore, and then the interface triggering copying parts enables relation, coordinates each copying parts and completes the data manipulation of stage, is finally completed the function of corresponding microcommand；
Wherein, emulation chip workbox module, functional units design management module and overall design management module all run in client computer.
Computer the most according to claim 1 composition and the Virtual Experiment Platform Based of system structure, it is characterised in that chip device storehouse is basic component inventory, logic gate component storehouse, digital device storehouse, multiplex roles winding displacement storehouse；
Preferably, functional part component inventory is that copying component warehouse, emulation registers warehouse, emulation time series pulse signals generator warehouse and emulation connect bus warehouse；
Preferably, chip-stored module is according to the chip title of n chip, various pin name, pin number, pin coordinate attributes in chip workbox configuration file and the menu generation chip realizing chip functions, according to the affiliated type of n emulation chip in chip workbox configuration file, described n emulation chip is stored respectively to the classification in chip device storehouse, thus complete the initialization in chip device storehouse；
Preferably, emulation chip attribute information includes the title of emulation chip, the affiliated type of emulation chip, the title of various pin, the quantity of pin and pin coordinate attributes.
Computer the most according to claim 1 composition and the Virtual Experiment Platform Based of system structure, it is characterized in that, what chip connection status attribute information comprised the original position pin that is connected on multiplex roles winding displacement of the title of two emulation chips, the title of various pin, pin number, the coordinate attributes of pin and the two emulation chip being connected by emulation chip pin by multiplex roles winding displacement and multiplex roles winding displacement occupies pin widths；
Preferably, functional part connection status attribute information specifically includes the interface coordinate of the multi-interface data path by multi-interface data path, multi-interface data type of passage, the copying parts being connected on system bus by multi-interface data path or other multi-interface data paths and connection thereof.
Computer the most according to claim 1 composition and the Virtual Experiment Platform Based of system structure, it is characterized in that, described emulation chip comprises chip event information memory module, chip event information input module, chip event information modified module, chip event information output module and chip event information display module, described event comprises data attribute and data come into force remaining time (remained attribute, described event uses two element group representations, it is 0 remaining time clears data when data come into force, after data in chip event information memory module are read, data remaining times of coming into force is 0, only when in chip event information memory module, the data redundancy entry-into-force time is 0, new data could be written to chip event information memory module by chip event information input module.
Computer the most according to claim 1 composition and the Virtual Experiment Platform Based of system structure, it is characterised in that described multi-interface data type of passage and interface coordinate definition thereof are as follows:
。
Computer the most according to claim 1 composition and the Virtual Experiment Platform Based of system structure, it is characterized in that, the operation of data entry operation described in phantom machine design of microinstruction module, data output operation, data access operation, data operation, the realization of instruction skip operation are opening of the enable switch according to control signal trigger data interface, then directly reading the data of storage in relief area, described data entry operation is divided into following a few step to complete:
S1, if data remaining times of coming into force is 0 in the relief area that the output port of simulation input device is corresponding, then data input switch state status of simulation input device is read in the relief area that data-out port is corresponding, and to arrange data remaining times of coming into force be 1, with two tuple (status, 1) incoming event of this simulation input device is represented, if data remaining times of coming into force not is 0 in relief area, enter waiting state, periodically monitor described data to come into force remaining time, until this buffer data comes into force, remaining time is 0, complete preliminary data and read in operation；
S2, data are successfully read in the relief area corresponding to the output port of simulation input device, the enable of the data-out port of simulation input device is switched simultaneously and open, if now on system bus, the data of relief area remaining times of coming into force is 0, the then incoming event two tuple (status in simulation input device, 1) can enter in the data buffer storage on system bus by data-out port, otherwise enter waiting state, until the data buffered in system bus come into force, remaining time is 0, buffer data in simulation input device is come into force simultaneously and subtract 1 remaining time, and close the enable switch of the output interface of simulation input device, complete data and read the process of system bus from peripheral hardware, described process is enabled control signal triggering by emulating microprogram control unit to the output port that simulation input device sends；
nullS3、Input time in data buffer zone on described system bus is read in emulation data register R0，First judge whether corresponding with Data Input Interface in emulation data register R0 buffer data remaining time is 0，If the data redundancy time of this emulation data register is 0，Open the enable switch of emulation registers Data Input Interface，By two tuple (status of relief area on system bus,1) read in the data buffer zone of data input correspondence of emulation data register R0，Otherwise enter waiting state，Until reading successfully，Then buffer data on system bus is come into force and subtract 1 remaining time，The enable switch of the data input switch being then shut off emulation data register cuts out，Complete final data and read the process of emulation data register from simulation input device，Described process is enabled control signal triggering by emulating microprogram control unit to the input interface of emulation data register；
S4, according to the data path C1 on the output interface being connected to simulation input device, interface coordinate (x1, y1), interface coordinate (the x2 that data path C1 is connected with system bus, y2), the data path C2 interface coordinate (x3 being connected with emulation data register R0, y3), interface coordinate (the x4 that data path C2 is connected with system bus, y4), it is assured that one from simulation input device to system bus, a data flow path from system bus to copying depositor R0 again: (x1, y1), (x2, y2), system bus, (x4, y4), (x3, y3).
Computer the most according to claim 1 composition and the Virtual Experiment Platform Based of system structure, it is characterized in that, selective laser sintering module produces control signal according to microprogram, and then the interface triggering copying parts enables, complete the data manipulation of stage, the control signal sequence of the microprogram generation completing each stage is referred to as the control field of microcommand, article one, machine instruction can a point multistep complete, with regard to corresponding a plurality of microcommand, direct control method is taked in the parsing of microcommand, binary each represent the enabler flags of copying interface, also indicate the address field taking out down hop microcommand, it is referred to as the lower location field of microcommand, the a plurality of microcommand completing multistep function is referred to as microprogram；
Preferably, microprogram control unit comprises control memorizer, microinstruction register, micro address register and micro-address formation parts；
Preferably, machine instruction set includes a plurality of machine instruction；nullControl memorizer and there is the attribute of memory space，Memory space is made up of data buffer zone sequence，Can be used to store the microinstruction sequence realizing all machine instructions，Each data buffer zone controlling memorizer has only address designator attribute in this emulation controller，Control each data buffer zone of memorizer for obtaining and store a microcommand from this emulation memory Data Input Interface，Control storage in all data buffer zones of memorizer and realize all microcommands of whole machine instruction，Every microcommand is stored in the control memorizer of microprogram control unit，Shared memory space has address designator attribute and memory space length attribute，Address designator attribute is the numbering of the data buffer zone controlling memorizer，Described numbering is referred to as micro-address，Memory space length attribute is the data buffer zone quantity taking and controlling memorizer；
Deposit in micro address register is that next pending microcommand place controls the address designator attribute in memorizer, micro-address forms parts for producing micro-address of next microcommand, and this micro-address is stored in described micro address register, microinstruction register comprises several data buffer zones, size occupies the length attribute of memory space in controlling memorizer equal to a microcommand, according to the address designator attribute of the microcommand of storage in micro-address search microprogram control unit, take out this buffer contents to be put in the data buffer zone of microinstruction register, detailed process is described as follows:
S1, defined variable i, and initialize i=1；
S2, reading i-th machine instruction from emulation memory, if i=1, then address forms parts and decodes this machine instruction, to initialize micro address register, otherwise directly reads micro address register and searches and control memorizer and obtain corresponding microcommand；
S3, the microcommand feeding microinstruction register storage that will take out, it is used for from the control field reading binary system bit position of microprogram producing the enable control signal controlling each copying unit interface, reads from lower location field and perform the address of down hop microcommand and be stored in micro address register；
S4, i=i+1, it is judged that whether microprogram has reached the last item microcommand, if it is take out next machine instruction in turn and turn S1 until all machine instructions perform to terminate, if not up to the last item microcommand, then turn S2 and perform next microcommand.
8. the implementation method of the Virtual Experiment Platform Based of the computer composition as described in any one of claim 1-7 and system structure, it is characterised in that comprise the following steps:
S1, emulation chip workbox module is set, comprise management of software ic module, chip-stored module and chip task management module, management of software ic module creation revisable chip workbox configuration file also initializes the attribute information being stored in n emulation chip, include along attribute information: the title of emulation chip, the affiliated type of emulation chip, various pin name, pin number, pin coordinate attributes and the menu realizing chip functions, chip-stored module is used for loading chip workbox configuration file, thus generate n emulation chip, and according to the affiliated type of n emulation chip in chip workbox configuration file, described n emulation chip is respectively stored in described chip device storehouse, chip task management module is for inputting the data of emulation chip, data operation and data output are managed；
nullS2、Functional units design management module is set，Comprise systematic function part design management module、Functional part memory module and copying component task management module，Systematic function part design management module is according to described computer composition and architecture，M emulation chip is called from chip device storehouse，This m emulation chip is spliced，Form a kind of described copying parts，Systematic function part design configuration file，And arrange and preserve described functional units design configuration file，Functional part memory module is for storing by loading copying parts and the copying depositor that functional units design configuration file generates，The described chip connection status attribute of described m emulation chip is obtained by loading functional units design configuration file，Thus generate copying parts and copying depositor and carry out classification storage management according to classification，The data of copying parts and copying depositor are inputted by copying component task management module、Data process and data output is managed，Data process is carried out by calling the various types of emulation chips comprised in copying parts successively，Thus realize data flowing on copying parts；
nullS3、Overall design management module is set，Comprise phantom machine design management module、Phantom machine memory module and phantom machine task management module，Phantom machine design management module is according to computer composition and system structure，M1 copying parts are called from copying component devices storehouse，Composition phantom machine on the system bus is connected by multi-interface data path，And by each copying unit type of composition phantom machine、Quantity and the two-dimensional position coordinate in working area，And the connection status attribute between each copying parts is saved in phantom machine design configurations file，Phantom machine memory module is for storing the phantom machine by loading phantom machine design configurations file generated，Phantom machine task management module comprises phantom machine design of microinstruction module and microprogram performs control module，Phantom machine design of microinstruction module is for the machine instruction set of design simulation model machine，Microprogram performs control module and produces control signal for microinstruction sequence carries out biological function explore，And then the interface triggering copying parts enables relation，Coordinate each copying parts and complete the data manipulation of stage，It is finally completed the function of corresponding microcommand.
9. computer composition as claimed in claim 8 and the Virtual Experiment Platform Based implementation method of system structure, it is characterized in that, copying parts are the set of emulation chip, there is data input, data operation and data output attribute, i.e. there is the attribute of emulation chip, can carry out being spliced into bigger copying parts according to join algorithm by copying parts and emulation chip, therefore the unit of bigger copying parts described in composition being referred to as chip, join algorithm generates copying parts as follows:
S1, defined variable i, and initialize i=1；
S2, copying component devices library module are supplied to the chip event information input module of i-th emulation chip by the connection status loading functional units design configuration file acquisition i-th emulation chip；
S3, the chip event information input module of i-th emulation chip obtain the k being connected with self according to i-th connection statusiIndividual emulation chip, and by kiThe output information of the chip event information output module of individual emulation chip is stored in the chip event information memory module of i-th emulation chip；
After S4, the chip event information modified module of i-th emulation chip read data message from the event information memory module of this i-th chip and process, operation result is restored in chip event information memory module；
S5, the chip event information output module of i-th emulation chip read operation result the output information as self from chip event information memory module；
S6, the value of i+1 is assigned to i, and judges whether sum (n1+n2+ ...+ni)≤m sets up, if setting up, then perform S2, otherwise, represent the generation having completed copying parts, wherein, ni represents the quantity that i-th emulation chip or copying parts comprise emulation chip；
Preferably, copying parts have one or more operational data input interfaces, there is one or more control signal input interfaces, there is one or more operational data output interfaces, have and operational data input interface, operational data output interface and the data buffer zone of control signal input interface equal number, each copying unit interface and a data buffer zone form mapping relations one by one, it is referred to as buffer interface mapping relations, corresponding data buffer zone can be found from copying unit interface by these buffer interface mapping relations；
Preferably, data buffer zone can be divided into data input buffer district, data output buffer and control signal relief area according to the data type of storage；
Preferably, emulation data path includes 1 data storage buffer and n copying unit interface, wherein, the Data Input Interface of n=copying parts, data output interface and the summation of control signal input interface quantity.
10. computer composition as claimed in claim 8 and the Virtual Experiment Platform Based implementation method of system structure, it is characterized in that, data interaction between copying parts connects rules of interaction according to being defined as interface, and it includes that interface connects rules of interaction 1 and interface connects rules of interaction 2；
Interface connection rules of interaction 1:
(1) the copying parts that each is connected on data path by Data Input Interface, data output interface and control signal input interface, each operational data input interface therein, switch according to the enable of each operational data input interface；
(2) if the enable switch of this operational data input interface is for open mode, data doublet in relief area on system bus can be copied in the data input buffer district corresponding to operational data input interface by this operational data input interface according to buffer interface mapping relations；
(3) otherwise, do not perform；
Interface connection rules of interaction 2:
(1) the copying parts that each is connected on data path by Data Input Interface, data output interface and control signal input interface, each operational data output interface therein, can switch according to the enable in operational data output interface；
(2) if the enable of output interface switchs for open mode constantly, data doublet on data output buffer corresponding to operational data output interface can be sent in the data storage buffer on system bus by this operational data output interface according to buffer interface mapping relations；
(3) otherwise, do not perform.
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