CN114676064A - General test system and method for hardware language code - Google Patents

Abstract

The invention discloses a hardware language code-oriented general test system and a method, comprising an FPGA development board and a controller; the FPGA development board comprises a test input excitation module, a tested module, a test output detection module, a test synchronization module and a test data sampling module; the method comprises the steps that a tested module obtains a hardware language code which can realize a test application scene and is compiled by a user through the tested module or a callable auxiliary module; under the label synchronization of the test synchronization module and the control of the test input excitation module and the test output detection module by the label, running and monitoring the hardware language code of the tested module to realize the test process, and outputting the test result and the test progress to the controller; and the controller judges whether the test passes according to the test result and the test progress and outputs a final test result. The system and method enable efficient and universal testing of hardware language code.

Description

General test system and method for hardware language code

Technical Field

The invention belongs to the field of program code testing, and particularly relates to a general test system and a general test method for hardware language codes.

Background

Testing code is a necessary process for software and hardware development processes. Currently, many online evaluation platforms for software languages exist, such as PAT (Programming abstract Test, leetecode question-reading website, and cowboy web question-reading website of university at zhejiang, and these online evaluation platforms can provide tests for software in various software languages, such as C/C + +, Java, Python, and JavaScript.

At present, Jutge, HDLbit and the like exist as online evaluation platforms aiming at hardware programming languages (hardware languages), software simulation verification for Verilog languages is provided, and only circuits with small scale can be verified without physical verification. At present, there are many methods for implementing a remote FPGA experimental platform, for example: the technical scheme includes that the technical scheme disclosed by the technical scheme can not provide a test mode meeting certain specifications, wherein the test mode is a remote FPGA experimental platform built by a lightweight server provided by CN111666685A, the Intel Soc FPGA remote online configuration and debugging method provided by CN111427839A, or the FPGA cloud laboratory platform specially designed for teaching provided by CN 111445364A.

At present, an on-line test platform aiming at hardware language can be downloaded to an FPGA development board to automatically test specific codes. The existing remote FPGA teaching platform can simply and automatically evaluate the experiment in the course, but can not provide a test scheme for the problems encountered in the actual production, but can not be well expanded, namely only the specific experiment can be evaluated. For example, a nationally-large FPGA extensible cloud experimental platform ZyCube, in which each cloud node is composed of an ARM processor and a tightly-coupled reconfigurable structure, can provide manual operation hardware and software programming experience for students, but cannot automatically evaluate experimental results of the students, and a teacher checks and runs codes of each student is a task with a large workload.

An existing remote FPGA experiment platform is a WeLab remote experiment platform of the university of Jiangsu. The system has an excellent experiment operation interface, but the main purpose of the system is to enable students to understand the principle of computer composition, a plurality of preset hardware circuit experiments exist in the system, and a user can click and download the experiments and then observe experiment phenomena through a virtual panel. The CPU designed in the system can be programmed to observe the data change. However, the autonomous hardware design by students has limitations, so that the hardware codes of the students cannot be verified to some extent.

The existing hardware code physical real machine testing method is more complex compared with a software code testing method, the problems of collaborative design of hardware and software, software and hardware interaction, synchronization among different devices, data communication and the like need to be comprehensively considered, and the method often has specificity, namely, a set of testing scheme only aims at a chip of a certain specific task and is lack of flexibility and reusability.

The most common method for testing the existing hardware module is software simulation, but the executed code on a real machine after the simulation is passed is unlikely to pass, and even under the premise of ensuring that the physical development board has no hardware problem, the problem on physical timing is also existed, for example, if the hardware code needs to call a physical peripheral (for example, read data in a memory), all details of the physical device are unlikely to be completely simulated by only software simulation.

Disclosure of Invention

In view of the above, the present invention aims to provide a general test system and method for hardware language codes, which realize efficient and general test of hardware language codes.

In order to achieve the above object, an embodiment provides a general test system for hardware language codes, including an FPGA development board and a controller; the FPGA development board comprises a test input excitation module, a tested module, a test output detection module, a test synchronization module and a test data sampling module;

the test input excitation module is used for outputting a clock signal, an input control signal and test input data to the tested module according to a test application scene;

the tested module is designed by a user to obtain a designed hardware language code, tests the hardware language code based on a clock signal, an input control signal and test input data, and outputs a test state, an output control signal and test output data to the test output detection module;

the output detection module is used for comparing the test output data with the correct output data, outputting the comparison result to the controller as a test result, and analyzing the test state to obtain the test progress and outputting the test progress to the controller;

the test synchronization module is used for synchronously marking test input data and test output data, so that data management and control and data comparison are facilitated;

the test data sampling module is used for sampling test input data, test output data and corresponding correct output data, forming test data and outputting the test data to the controller;

the controller is used for controlling the test process of the FPGA development board for realizing the hardware language codes, judging whether the test passes according to the received test result and the test progress, and outputting the final test result.

In one embodiment, the test synchronization module synchronously marks the test input data input at the current moment and the corresponding test output data through the test tag so as to correspond the test input data with the corresponding test output data;

and the test synchronization module synchronously marks the test input data input at the next moment and the corresponding test output data through the next group of labels so as to correspond the test input data and the corresponding test output data.

In one embodiment, the test input excitation module is configured to generate a test tag at a current time, and output the test tag to the test synchronization module when test input data is input to the module to be tested at the current time;

the test synchronization module is used for forwarding the received test label to the test output detection module;

the test output detection module is used for marking the test output data obtained by the test input data through hardware language code execution calculation by using the received test label, and is also used for generating a next group of labels at the next moment and sending the next group of labels to the test synchronization module after the test of the test input data at the current moment is finished;

the test synchronization module is also used for forwarding the received next group of labels to the test input excitation module;

and the test input excitation module is used for marking the test input data at the next moment according to the received next group of labels.

In one embodiment, the test input excitation module is further configured to perform frequency division and time delay processing on the clock signal and the input control signal according to a test requirement, and the processed clock signal and the processed input control signal are input to the module under test.

In one embodiment, the FPGA development board further comprises a plurality of callable auxiliary modules, and a single callable auxiliary module has a single auxiliary function or provides a file required by the FPGA development board for adaptation so as to assist the tested module in writing hardware language codes.

In one embodiment, the FPGA development board further comprises a reset module, the reset module is controlled by the controller to output a reset signal, and the reset signal comprises a system reset signal, a reset signal to be tested and a timing reset signal; the system reset signal is used for controlling the start of the execution test function of the universal test system, the reset signal to be tested is used for controlling the start of the test case, and the timing reset signal is used for controlling the start of timing.

In one embodiment, the FPGA development board further comprises a clock module, and the clock module is used for providing clock signals with multiple frequencies for the test process so as to drive the test to be smoothly performed.

In order to achieve the above object, an embodiment of the present invention further provides a general test method for hardware language codes, where the general test method adopts the general test system, and includes the following steps:

the method comprises the steps that a tested module obtains a hardware language code which can realize a test application scene and is compiled by a user through the tested module or a callable auxiliary module;

after receiving the test task, the controller burns the executable file into the FPGA development board and controls the reset module to output a reset signal to start testing;

under the label synchronization of the test synchronization module and the control of the test input excitation module and the test output detection module by the label, running and monitoring the hardware language code of the tested module to realize the test process, and outputting the test result and the test progress to the controller;

the test data sampling module samples and stores test input data, test output data and correct output data in the test process;

after the test is finished, the test data sampling module transmits the stored data to the controller;

and the controller judges whether the test passes according to the test result and the test progress and outputs a final test result.

Compared with the prior art, the invention has the beneficial effects that at least:

the universal test system provided by the embodiment provides a new scheme for evaluating the hardware programming capability of students for school teachers, the students can write hardware language codes only according to the requirements of test questions through the remote universal test system, the universal test system can verify the written hardware language codes through a physical hardware platform, the teachers do not need to manually distinguish the codes or compile and download the codes one by one, and the teachers can design key data in advance, so that careless omission in manual judgment is avoided;

wherein, for the key data, it is understood that: each hardware code module, to determine whether it is correct or not, may not be able to run all the inputtable data, because the amount of data may be large, for example, a 32-bit adder may not be able to calculate all the values, therefore, on a common software test platform, some boundary data, for example, 0+0, 0+1, 0-1, 2147483647+1 of the adder, is often run, which is the key data, and different hardware modules have different key data.

The general test system provided by the embodiment provides a new hardware development mode for enterprises, a product manager only needs to provide a use specification and a plurality of use examples for a new product, then a developer designs the new product according to the specification through a module to be tested of the general test system according to the specification, and tests of the new product are realized through other modules.

The universal test system provided by the embodiment provides the editing function of the hardware language code and the test function of the hardware language code, and realizes the efficient and universal test of the hardware language code.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a schematic structural diagram of a general test system for hardware language code provided by an embodiment;

FIG. 2 is a flowchart of a general test method for hardware-oriented language code provided by an embodiment;

FIG. 3 is a signal diagram provided by an embodiment;

fig. 4 and 5 are code simulation results provided by experimental examples.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the detailed description and specific examples, while indicating the scope of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.

Fig. 1 is a schematic structural diagram of a general test system for hardware language code provided by an embodiment. As shown in fig. 1, the universal test system provided by the embodiment includes an FPGA development board and an FPGA development board controller; the FPGA development board comprises a test input excitation module, a tested module, a test output detection module, a test synchronization module, a test data sampling module, a reset module, a clock module and a plurality of auxiliary modules capable of being called. The following detailed description is made for the function of each module:

the reset module is used for outputting a reset signal to the test input excitation module, the reset signal is used for representing a test starting signal and is provided by the reset module and the controller on the FPGA development board through the GPIO port, namely the controller controls the reset module to output the reset signal through the GPIO port, in the embodiment, the reset signal comprises a system reset signal, a reset signal to be tested and a timing reset signal; the system reset signal is used for controlling the start of the execution test function of the universal test system, the reset signal to be tested is used for controlling the start of the test case, and the timing reset signal is used for controlling the start of timing.

The clock module is used for outputting clock signals with various frequencies for the test process so as to drive the test to be smoothly carried out, and the clock signals output by the clock module are transmitted to the test input excitation module.

The test input excitation module is used for outputting a clock signal, an input control signal and test input data to the tested module according to a test application scene. The input control signal is used for sending a control instruction to the tested module, and the control instruction comprises starting a test, positioning a next group of test data, testing which function and the like, and the test input data is used for testing the implementation function of the hardware language code edited by the tested module and can be input from the outside. According to the requirements of a test application scene, namely according to the realization function of a hardware language code, the test input excitation module is also used for carrying out frequency division and time delay processing on a clock signal and an input control signal, and the processed clock signal and the processed input control signal are input to the tested module. For example, when it is necessary to measure the number of clock cycles that the module under test takes to complete a certain function, the module under test reset needs to be after the timer reset, and furthermore, it needs to clock test the highest frequency at which the module under test can normally operate at a different frequency.

The tested module is used for user design to obtain a designed hardware language code, namely, a user (a student or a designer) designs the hardware language code through an interface provided by the tested module to design a test application scenario. The tested module is also used for testing the hardware language code based on the clock signal, the input control signal and the test input data, and outputting the test state, the output control signal and the test output data to the test output detection module. The test state marks the validity of the test output data, namely, the test output data is intermediate result data or final result data, and the test output data refers to data obtained by performing calculation on the test input data through a written hardware language code. The output control signal is used for informing whether the current output of the subsequent module is effective or not, and informing the test output detection module to read the effective output and ignore the intermediate irrelevant data in the test.

The output detection module is used for comparing the test output data with the correct output data, outputting the comparison result to the controller as a test result, and analyzing the test state to obtain the test progress and outputting the test progress to the controller. For example, when the test application function is an addition formula, the addition formula can be written by the tested module to form a hardware language code to realize an addition function, and the correct output data is a result calculated by the addition formula.

Because the test state indicates the state of the test output data, namely, the intermediate result or the final result, when the analysis test state indicates that the test output data is the intermediate result data, the test progress indicates that the test is not finished, and when the analysis test state indicates that the test output data is the final result data, the test progress indicates that the test is finished.

The test synchronization module is used for synchronously marking the test input data and the test output data, so that the test samples and the test results comprising the test input data can be in one-to-one correspondence in the test process, and the data management and control and the data comparison are facilitated. In an embodiment, a test synchronization module synchronously marks test input data input at the current moment and corresponding test output data through a test tag so as to correspond the test input data with the corresponding test output data, specifically, a test input excitation module is used for generating the test tag at the current moment, and outputting the test tag to the test synchronization module when the test input data is input to a module to be tested at the current moment; the test synchronization module is used for forwarding the received test label to the test output detection module; the test output detection module is used for marking the test output data obtained by executing calculation on the test input data through the hardware language code by using the received test label.

In an embodiment, the test synchronization module synchronously marks the test input data and the corresponding test output data input at the next time through the next group of tags, so as to correspond the test input data and the corresponding test output data. Specifically, the test output detection module is configured to generate a next group of tags at a next time and send the next group of tags to the test synchronization module after the test of the test input data at the current time is finished; the test synchronization module is used for forwarding the received next group of labels to the test input excitation module; and the test input excitation module is used for marking the test input data at the next moment according to the received next group of labels.

The test data sampling module is used for sampling test input data, test output data and corresponding correct output data, forming test data and outputting the test data to the controller.

The controller is used for controlling the test process of the FPGA development board for realizing the hardware language codes, judging whether the test passes according to the received test result and the test progress, and outputting the final test result.

In an embodiment, the single callable auxiliary module has a single auxiliary function or provides a file required by the adaptation of the FPGA development board, such as a pin constraint file, to assist the tested module in writing the hardware language code. Wherein the single auxiliary function includes an alternative multiplexer, a 3-8 decoder, and the like.

FIG. 2 is a flowchart of a general test method for hardware-oriented language code provided by an embodiment; FIG. 3 is a signal diagram provided by the embodiment. The general test method provided by the embodiment applies the general test system, as shown in fig. 2 and fig. 3, and includes the following steps:

step 1, compiling a tested module;

in the embodiment, a tested module interface is provided for a user to perform functional writing, the user uses a callable auxiliary module defined in a test subject to perform hardware language code design on a tested module so as to realize the design writing of hardware language codes, and the tested module acquires that the user writes the hardware language codes capable of realizing a test application scene through a single tested module or the tested module and at least 1 callable auxiliary module;

step 2, preparation work before testing

In the embodiment, after the controller receives the test task, the executable file is burned to the FPGA development board, and the reset module is controlled to output the reset signal so as to start the test.

Step 3, testing process of tested module monitored by label

In the embodiment, when the test is started, under the label synchronization of the test synchronization module and under the control of the label, the test input excitation module and the test output detection module run and monitor the hardware language code of the tested module to realize the test process, and output the test result and the test progress to the controller.

Specifically, the test input excitation module generates a test tag at the current moment when receiving the reset signal, and outputs the test tag to the test synchronization module when inputting test input data to the tested module at the current moment, wherein the test synchronization module is used for forwarding the received test tag to the test output detection module; the tested module executes a testing process based on input testing input data, a clock signal and an input control signal, outputs a module state, an output control signal and testing output data to the testing output detection module, and the testing output detection module of the output detection module marks the testing output data obtained by executing calculation on the testing input data through a hardware language code by using a received testing label; after the test of the test input data at the current moment is finished, generating a next group of labels at the next moment and sending the next group of labels to the test synchronization module; the test synchronization module forwards the received next group of labels to the test input excitation module; and the test input excitation module marks the test input data at the next moment according to the received next group of labels.

And 4, testing the sampling process of the data.

In an embodiment, the test data sampling module may use a highest frequency clock signal provided by the clock module as a sampling clock, sample and store test input data, test output data, and correct output data in the test process, and after the test is finished, the test data sampling module transmits the stored data to the controller through the GPIO according to a certain format.

Step 5, judging whether the test is passed or not

In the embodiment, the controller judges whether the test passes according to the test result and the test progress, and outputs the final test result.

The communication test system and the communication test method provided by the embodiment can test the hardware language code on the FPGA development board to complete the verification of the real machine physical layer. The test system and the test method can be oriented to teaching scenes, and realize the test of the automatic real-machine physical verification of the hardware language code designed by the tested module for students.

The universal test system and the method provided by the embodiment also aim at the practical problems encountered in engineering, the hardware function design is carried out according to the provided test system, the test release can be carried out on the remote universal test system, and technicians in a company can develop and verify through the test system, so that the hardware development efficiency is improved.

The universal test system and the universal test method provided by the embodiment do not need to consider the pin constraint problem of a hardware platform, and aim at different FPGA development boards, hardware constraints are automatically matched through the auxiliary module which can be called, so that designers can concentrate on core logic function design.

The general test system provided by the embodiment is an online evaluation system for a hardware code language, and can also perform software simulation on Verilog codes through other tools such as open source software verilator on gitub, and can also complete evaluation of code logicality through simulation, but the software simulation cannot completely simulate the timing sequence on hardware in a fidelity manner, that is, the software simulation cannot necessarily work correctly physically through 100%.

Unlike conventional hardware testing schemes (which produce chips and then perform testing), the system and method provided by the embodiments are directed to FPGAs, which have programmable characteristics, thereby improving flexibility.

Examples of the experiments

Test questions for each 4-16 decoder, but involve two 8-bit output data. Such a scenario may occur when a single physical chip pin is not enough, and the high bits of the code need to exist as a chip select signal, for example, a 5-32 decoder may be designed as 4 3-8 decoders, and the highest two bits are used as the select signal of the several 3-8 decoders.

With the general test system provided by the above embodiment, the code simulation result is shown in fig. 4, and the simulation result only shows part of the critical ports, where the test output detection module is configured to detect whether the test output data of the module under test is the same as the standard correct output data, and indicate by the ans flag, if ans is 1, it indicates that the test data is correct, otherwise, it indicates that the data is incorrect. And if the signal is high, the controller starts data transmission, a clock signal is sent to the FPGA through a testClk in the top port, and the FPGA outputs data through the testData signal.

FIG. 4 depicts the results of a test for correct code. Fig. 5 shows a situation that a test result is incorrect, and a correct module code to be tested is modified, and the hardware code testing method provided by the embodiment can accurately find an incorrect position and ensure the accuracy of the test result.

The above-mentioned embodiments are intended to illustrate the technical solutions and advantages of the present invention, and it should be understood that the above-mentioned embodiments are only the most preferred embodiments of the present invention, and are not intended to limit the present invention, and any modifications, additions, equivalents, etc. made within the scope of the principles of the present invention should be included in the scope of the present invention.

Claims (8)

1. A general test system facing hardware language codes is characterized by comprising an FPGA development board and a controller; the FPGA development board comprises a test input excitation module, a tested module, a test output detection module, a test synchronization module and a test data sampling module;

the test input excitation module is used for outputting a clock signal, an input control signal and test input data to the tested module according to a test application scene;

the tested module is designed by a user to obtain a designed hardware language code, tests the hardware language code based on a clock signal, an input control signal and test input data, and outputs a test state, an output control signal and test output data to the test output detection module;

the output detection module is used for comparing the test output data with the correct output data, outputting the comparison result to the controller as a test result, and analyzing the test state to obtain the test progress and outputting the test progress to the controller;

the test synchronization module is used for synchronously marking test input data and test output data, so that data management and control and data comparison are facilitated;

the test data sampling module is used for sampling test input data, test output data and corresponding correct output data, forming test data and outputting the test data to the controller;

the controller is used for controlling the test process of the FPGA development board for realizing the hardware language codes, judging whether the test passes according to the received test result and the test progress, and outputting the final test result.

2. The universal test system for hardware language codes according to claim 1, wherein the test synchronization module synchronously marks the test input data input at the current time and the corresponding test output data through the test tag to correspond the test input data and the corresponding test output data;

and the test synchronization module synchronously marks the test input data input at the next moment and the corresponding test output data through the next group of labels so as to correspond the test input data and the corresponding test output data.

3. The hardware language code-oriented general test system according to claim 2, wherein the test input excitation module is configured to generate a test tag at a current time, and output the test tag to the test synchronization module when test input data is input to the module under test at the current time;

the test synchronization module is used for forwarding the received test label to the test output detection module;

the test output detection module is used for marking the test output data obtained by the test input data through hardware language code execution calculation by using the received test label, and is also used for generating a next group of labels at the next moment and sending the next group of labels to the test synchronization module after the test of the test input data at the current moment is finished;

the test synchronization module is also used for forwarding the received next group of labels to the test input excitation module;

and the test input excitation module is used for marking the test input data at the next moment according to the received next group of labels.

4. The universal test system for hardware language codes according to claim 1, wherein the test input excitation module is further configured to perform frequency division and delay processing on the clock signal and the input control signal according to the test requirement, and the processed clock signal and the processed input control signal are input to the module under test.

5. The universal test system for hardware language codes according to any one of claims 1 to 5, wherein the FPGA development board further comprises a plurality of callable auxiliary modules, and a single callable auxiliary module has a single auxiliary function or provides files required by the FPGA development board for adaptation so as to assist the tested module in writing the hardware language codes.

6. The hardware language code-oriented general test system according to claim 1, wherein the FPGA development board further comprises a reset module, the reset module is controlled by the controller to output a reset signal, and the reset signal comprises a system reset signal, a reset signal to be tested, and a timing reset signal; the system reset signal is used for controlling the start of the execution test function of the universal test system, the reset signal to be tested is used for controlling the start of the test case, and the timing reset signal is used for controlling the start of timing.

7. The hardware language code-oriented general test system according to claim 1, wherein the FPGA development board further comprises a clock module, and the clock module is configured to provide clock signals with multiple frequencies for the test process to drive the test to be performed smoothly.

8. A universal test method for hardware language codes, which adopts the universal test system of any one of claims 1-7, comprising the following steps:

the method comprises the steps that a tested module obtains a hardware language code which can realize a test application scene and is compiled by a user through the tested module or a callable auxiliary module;

after receiving the test task, the controller burns the executable file into the FPGA development board and controls the reset module to output a reset signal to start testing;

under the label synchronization of the test synchronization module and the control of the test input excitation module and the test output detection module by the label, running and monitoring the hardware language code of the tested module to realize the test process, and outputting the test result and the test progress to the controller;

the test data sampling module samples and stores test input data, test output data and correct output data in the test process;

after the test is finished, the test data sampling module transmits the stored data to the controller;

and the controller judges whether the test passes according to the test result and the test progress and outputs a final test result.

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