CN101253575B - Sampled-data circuits using zero crossing detection - Google Patents
Sampled-data circuits using zero crossing detection Download PDFInfo
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Abstract
A sampled-data analog circuit includes a level-crossing detector (30). The level-crossing detector controls sampling switches (s22n, s23n, s22p, s23p) to provide a precise sample of the output voltage when the level-crossing detector senses the predetermined level crossing of the input signal. The level-crossing detection may be a zero-crossing detection. An optional common-mode feedback circuit (400) can keep the output common-mode voltage substantially constant.
Description
Priority information
The sequence number that the application requires on June 16th, 2006 to submit to according to 35U.S.C. § 119 (e) is that 11/454,275 novel application of U.S. utility and the sequence number submitted on July 1st, 2005 are the right of priority of 60/595,414 U.S. Provisional Patent Application.The sequence number that the application also requires on July 11st, 2005 to submit to according to 35U.S.C. § 119 (e) is the right of priority of 60/595,493 U.S. Provisional Patent Application.The sequence number that on June 16th, 2006 submitted to is 11/454, the sequence number that the novel application of 275 U.S. utility, on July 1st, 2005 submit to is 60/595, the sequence number of submitting in 414 U.S. Provisional Patent Application and on July 11st, 2005 is that the full content of 60/595,493 U.S. Provisional Patent Application is incorporated herein by reference.
Invention field
The present invention relates generally to switched-capacitor circuit, relate in particular to the switched-capacitor circuit of the integrated circuit of making according to the convergent-divergent semiconductor technology.
Background of invention
Most of sampled data mimic channels such as switching capacity filter, analogue-to-digital converters and δ-σ modulator need operational amplifier with processing signals.Think over switched-capacitor integrator example shown in Figure 2.At first, Closing Switch S
11And S
13Thereby, at sampling capacitor C
S1Up-sampling input voltage V
InThen, cut-off switch S
11And S
13And Closing Switch S
12And S
14This operation is with sampling capacitor C
S1On electric charge transfer to integrating condenser C
I1On.The output voltage V of first integrator 1100
OutGenerally sample by another sampled-data circuits, for example, another switched-capacitor integrator.In circuit shown in Figure 2, by switch S
21, S
22, S
23, S
24And the second sampling capacitor C
S2The circuit of forming constitutes the part of second switch capacitance integrator.By Closing Switch S
21And S
23, at the second sampling capacitor C
S2The output voltage V of up-sampling first integrator 10
Out
An example of sequential chart shown in Fig. 3.Clock signal has two non-overlapped phase place Ф
1And Ф
2With phase place Ф
1Be applied to switch S
11, S
13, S
21And S
23, and with phase place Ф
2Be applied to switch S
12, S
14, S
22And S
24With this sequential, circuit postpones to carry out noninverting discrete integration with full-time clock.The output V of integrator
OutWith virtual ground node 100, V
1The waveform at place is also shown in Figure 3.Different clock phase arrangements obtain different responses from integrator.For example, if with Ф
1Be applied to switch S
11, S
13, S
22And S
24, and with Ф
1Be applied to switch S
12, S
14, S
21And S
23, then circuit postpones to carry out noninverting integration with the half clock.
For the accurate integration of input signal, must be with V
1Drive to as much as possible near ground connection.In order to realize this purpose, operational amplifier must provide enough open-loop gain and low noise.In addition, for quick computing, the operational amplifier 10 of Fig. 2 must fast and stable.
In Fig. 3, be illustrated in by closed S
12And S
14With sampling capacitor C
S1After the interference when switching to node 100, voltage V
1Stable to ground connection.Except that high open-loop gain with stabilization time fast, operational amplifier must provide big output swing (output swing) for big dynamic range.Along with the upgrading of technology, becoming more and more is difficult to realize these characteristics by operational amplifier.Making the difficult principal element of design change of operational amplifier is low supply voltage and low device gain.
As mentioned above, if the node among Fig. 2 100 is accurately maintained ground connection, then can obtain precise output voltage.Yet in sampled-data circuits, the unique time point that needs accurate output voltage is the moment of output voltage by another sample circuit sampling.Therefore, voltage that will node 100 places is maintained ground connection always.
Therefore, expectation provides a kind of sampled-data circuits of being kept suitable level at output voltage by the moment of another sample circuit sampling at virtual ground node place.In addition, expectation provides a kind of sampled-data circuits of being kept suitable level and differential signal path being provided for all sampled-data circuits at virtual ground node place by the moment of another sample circuit sampling at output voltage.In addition, expectation provides a kind of sampled-data circuits that reduces power supply, substrate and common-mode noise influence by the symmetric difference signal Processing.Also expectation provides a kind of by increase the sampled-data circuits of range of signal in conjunction with differential signal path.
Summary of the invention
One aspect of the present invention is a switched-capacitor circuit.This switched-capacitor circuit comprises: the level cross detecting device that is used for generating the level cross detection signal when input signal intersects with predetermined level; A plurality of capacitors; And the sampling switch that is coupled to the level cross detecting device in the operation.When level cross detection signal indication level cross, sampling switch transfers to and ending.
Another aspect of the present invention is a switched-capacitor circuit.This switched-capacitor circuit comprises: the level cross detecting device that is used for generating the level cross detection signal when input signal intersects with first predetermined level; Be used for when input signal intersects with second predetermined level, generating the second level cross detecting device of the second level cross detection signal; A plurality of capacitors; And the sampling switch that is coupled to the second level cross detecting device in the operation.When second level cross detection signal indication input signal intersected with second predetermined level, described sampling switch transferred to and ending.
Another aspect of the present invention is a switched-capacitor circuit.This switched-capacitor circuit comprises: have first switched capacitor network of input end with the receiving circuit input voltage; Has the level cross detecting device that generates the level cross detection signal when output terminal and input end intersect with predetermined level with the signal at input end; And the second switch capacitance network that is coupled to the level cross detecting device in the operation.When the difference of first and second input signals was intersected with predetermined level, the second switch capacitance network transferred to and ending.
Another aspect of the present invention is the method for sampled analog signal.This method is used the switched capacitor network samples input voltage; The node voltage that determines when switched capacitor network intersects with predetermined level; And when the node voltage of determining switched capacitor network intersects with predetermined level, provide the output voltage sampling of switched capacitor network.
Another aspect of the present invention is the method for sampled analog signal.This method is used the switched capacitor network samples input voltage; The node voltage that determines when switched capacitor network intersects with first predetermined level; The node voltage that determines when switched capacitor network intersects with second predetermined level; And when the node voltage of determining switched capacitor network intersects with second predetermined level, provide the output voltage sampling of switched capacitor network.
Another aspect of the present invention is the differential switch condenser network.This differential switch condenser network comprises: the level cross detecting device that is used for generating the level cross detection signal when the difference of first and second input signals is intersected with predetermined level; A plurality of capacitors; And the sampling switch that is coupled to the level cross detecting device in the operation.When level cross detection signal indication level cross, sampling switch transfers to and ending.
Another aspect of the present invention is the differential switch condenser network.This differential switch condenser network comprises: the level cross detecting device that is used for generating the level cross detection signal when the difference of first and second input signals is intersected with first predetermined level; Be used for when the difference of first and second input signals is intersected with second predetermined level, generating the second level cross detecting device of the second level cross detection signal; A plurality of capacitors; And the sampling switch that is coupled to the level cross detecting device in the operation.When the second level cross detection signal indicated the difference of first and second input signals to intersect with second predetermined level, described sampling switch transferred to and ending.
Another aspect of the present invention is the differential switch condenser network.This differential switch condenser network comprises: have input end to receive first switched capacitor network of first input voltage; Has input end to receive the second switch capacitance network of second input voltage; Have output terminal and input end when the difference of described first and second input signals is intersected with predetermined level, to generate the level cross detecting device of level cross detection signal; And the 3rd switched capacitor network that is coupled to the level cross detecting device in the operation.When the difference of first and second input signals was intersected with predetermined level, the 3rd switched capacitor network transferred to and ending.
Another aspect of the present invention is the method for sampled analog signal.This method sampling input voltage; The difference that determines when first and second signals is intersected with predetermined level; And when intersecting with predetermined level, the difference of determining first and second signals provide output voltage to sample.
Another aspect of the present invention is the method for sampled analog signal.This method sampling input voltage; The difference that determines when first and second signals is intersected with first predetermined level; The difference that determines when first and second signals is intersected with second predetermined level; And the sampling that output voltage is provided when the difference of determining first and second signals is intersected with second predetermined level.
The accompanying drawing summary
The present invention can be embodied as the arrangement of various assemblies and assembly and the arrangement of various step and step.Accompanying drawing only is should not be interpreted as limitation of the present invention for the purpose that preferred embodiment is described, in the accompanying drawing:
Fig. 1 illustrates zero-crossing detector;
Fig. 2 illustrates switched-capacitor integrator;
Fig. 3 illustrates the sequential chart of the switched-capacitor integrator of Fig. 2;
Fig. 4 illustrates the noninverting integrator according to notion of the present invention;
Fig. 5 illustrates the sequential chart of the noninverting integrator of Fig. 4;
Fig. 6 illustrates the noninverting integrator as the waveform generator of current source according to notion of the present invention;
Fig. 7 illustrates another the noninverting integrator according to notion of the present invention;
Fig. 8 illustrates the sequential chart of the noninverting integrator of Fig. 7;
Fig. 9 illustrates another the noninverting integrator according to notion of the present invention;
Figure 10 illustrates another the noninverting integrator according to notion of the present invention;
Figure 11 illustrates the sequential chart of the noninverting integrator of Figure 10;
Figure 12 illustrates another the noninverting integrator according to notion of the present invention;
Figure 13 illustrates another the noninverting integrator according to notion of the present invention;
Figure 14 illustrates the sequential chart of the noninverting integrator of Figure 13;
Figure 15 illustrates the noninverting integrator with differential signal path according to notion of the present invention;
Figure 16 illustrates the sequential chart of the noninverting integrator of Figure 15;
Figure 17 illustrates according to another of notion of the present invention has the noninverting integrator of differential signal path;
Figure 18 illustrates according to another of notion of the present invention has the noninverting integrator of differential signal path;
Figure 19 illustrates the sequential chart of the noninverting integrator of Figure 18;
Figure 20 illustrates according to another of notion of the present invention has the noninverting integrator of differential signal path;
Figure 21 illustrates according to another of notion of the present invention has the noninverting integrator of differential signal path;
Figure 22 illustrates the sequential chart of the noninverting integrator of Figure 21.
Detailed description of the present invention
The present invention will be described in conjunction with the preferred embodiments, yet, will understand and not plan to limit the invention to embodiment as herein described.On the contrary, be intended to cover all selections, modification and the equivalent technique scheme that can be included in the spirit and scope of the present invention that limit by appended claims.
For general understanding of the present invention, can be with reference to the accompanying drawings.In the accompanying drawing, identical Reference numeral is used to indicate element identical or of equal value in whole accompanying drawing.It shall yet further be noted that each accompanying drawing of the present invention is shown may not drawn in proportion, and deliberately not to scale (NTS) is drawn some zone, thereby feature of the present invention and notion suitably are shown.
It should be noted that in each accompanying drawing the common mode voltage of ground connection symbolic representation system.For example, have 2.5V and-system of 2.5V power supply in, the common mode voltage of system can be a ground connection.In the system with single 2.5V power supply, the common mode voltage of system can be 1.25V.
As mentioned above, if the node among Fig. 2 100 accurately is maintained ground connection, then can obtain precise output voltage.Yet in sampled-data circuits, the unique time point that needs accurate output voltage is the moment of output voltage by another sample circuit sampling.Therefore, voltage that will node 100 places is maintained ground connection always.
Fig. 4 illustrates the noninverting integrator according to notion of the present invention.More specifically, as an example, figure 4 illustrates noninverting integrator with the delay of half clock.
As shown in Figure 4, with clock phase Ф
1Be applied to switch S
11, S
13, S
22And S
24, and with another phase place Ф
2Be applied to switch S
12, S
14And S
21Zero-crossing detector 30 is used for the time point that detection node 100 and ground connection are intersected.Switch S
23Output control by zero-crossing detector 30.The output of zero-crossing detector 30 is used for determining to gather output voltage V
OutThe time point of sampling.If waveform generator 20 is with capacitor C
S1And C
I1In electric charge then the voltage at node 100 places and the mode of zero crossing generate as output voltage V in normal working range
OutVoltage waveform.
In sequential chart shown in Figure 5, the waveform that is generated by waveform generator 20 is illustrated as the slope.Voltage V when node 100 places
1At time t
1During with zero crossing, the output V of zero-crossing detector 30
ZCBecome low, with switch S
23Transfer OFF to.At this moment, output voltage V
OutAt C
S2Up-sampling.
Because as sampling V
2The time V
1Very near zero, so precise output voltage is at C
S2Up-sampling.During next clock period, repeat similar operation, and at time t
2Sampling and outputting voltage.
Notice that zero-crossing detector 30 selectively has the overflow detected characteristics, this feature is determined capacitor C
S1And C
I1In electric charge when beyond normal working range.Can be implemented in Ф by logical circuit
2Become the output V that makes zero-crossing detector 30 when hanging down
ZCBecome low.At V
1Fail in the incident with zero crossing, at Ф
2Falling edge sampling.Simultaneously, logical circuit produces the sign of indication overflow.
In the above embodiments and each embodiment described below, use zero-crossing detector to replace comparer.Generally, comparator design is become relatively two any input voltages.Comparer can be embodied as cascade amplifier, regenerative latch (regenerative latch) or both combinations.Comparer can be used for detecting zero voltage level or predetermined voltage level intersects.
The input waveform that it should be noted that described each embodiment is not arbitrarily, but determinacy and repeatability.Therefore, described each embodiment determines the moment that zero voltage level or predetermined voltage level are intersected, rather than the relative amplitude of input signal.For this deterministic input, zero-crossing detector is more effective.
The example of zero-crossing detector that is used to detect the forward input signal is shown in Figure 1.At first, node 1 and node 2 are precharged to V respectively
DDAnd ground connection.Apply slope input voltage V according to zero cross circuit
INAt the time place of input node and threshold crossings, node 1 promptly discharges, and node 2 is pulled up to V
DDBecause the zero-crossing detector among Fig. 1 is a dynamic circuit, thus the DC power consumption do not had, thus allow extremely low power and operation fast.For the zero cross detection of negative-going signal, can use complementary circuit with PMOS input transistors.
As shown in Figure 6, noninverting integrator comprises the waveform generator as current source 200.As shown in Figure 6, with clock phase Ф
1Be applied to switch S
11, S
13, S
22And S
24, and with another phase place Ф
2Be applied to switch S
12, S
14And S
21Zero-crossing detector 30 is used for the time point that detection node 100 and ground connection are intersected.Switch S
23Output control by zero-crossing detector 30.The output of zero-crossing detector 30 is used for determining to gather output voltage V
OutThe time point of sampling.
200 couples of capacitor C of current source
S2With the C that is connected in series
S1And C
I1Charge, generate the slope.At Ф
2Section start, will export and be short-circuited to known voltage V simply
NEG, its value is chosen to the voltage V that guarantees node 100
1Be in the normal working range with zero crossing and signal.
As shown in Figure 7, noninverting integrator comprises waveform generator 20, and it preferably produces a plurality of sections in waveform, and changes the rate of change of output voltage.First section of may command is so that have the highest rate of change, and section subsequently has the rate of change that reduces gradually.The zero crossing that is detected by zero-crossing detector 30 makes waveform advance to next section.The output signal V of zero-crossing detector 30
ZC2Remain height, in back segment, detect zero crossing at waveform.
The sequential chart of a clock period shown in Fig. 8.At Ф
2Section start, waveform generator 20 produces acclivities.Voltage V is shown
1At time t
1Place and zero crossing.An output V of zero-crossing detector 30
ZC1At limited delay t
D1Change its state afterwards.
Postpone t
D1Represent the limited delay of typical zero-crossing detector 30.The change of this state makes waveform advance to next section.
Because the t of zero-crossing detector 30
D1, voltage V
1The a small amount of mistake is flushed to more than the ground connection.Second section of waveform generator is to downslope, allows at time t
2Another zero crossing at place.Postpone t second
D2Afterwards, the output V of zero-crossing detector 30
ZC2Become lowly, make switch S
23Transfer OFF to, the locking output voltage V
OutSampling.
The delay t of second zero crossing
D2Not necessarily and the delay t that is associated with first zero crossing
D1Identical.Postpone t
D2Output voltage to sampling provides little overshoot.The influence of overshoot is illustrated as the systematic offset in the sampled charge.In most of sampled-data circuits, this systematic offset is out of question.
Along with waveform segment advances, zero-crossing detector 30 preferably becomes more accurate in detecting zero crossing.First detection needn't be very accurate as Rough Inspection.Therefore, the degree of accuracy that detection can be lower is carried out quickly.Last zero cross detection in the period demand is determined the degree of accuracy of output voltage.For this reason, last zero cross detection must be the most accurate.
Degree of accuracy, speed and power consumption can be traded off between zero cross detection one by one, to realize optimum overall performance.For example, first detects with less degree of accuracy and more has noise ground to carry out, but it is lower to carry out comparatively fast (the delay of lacking) and power.And last detection is more accurate and more undisturbedly carry out, and consumes more power and slow (long delay) simultaneously.
The example of two sections waveform generators that constitute by two current sources (210 and 220) shown in Fig. 9.As shown in Figure 9, with clock phase Ф
1Be applied to switch S
11, S
13, S
22And S
24, and with another phase place Ф
2Be applied to switch S
12, S
14And S
21Zero-crossing detector 30 is used for the time point that detection node 100 and ground connection are intersected.Switch S
23Output control by zero-crossing detector 30.The output of zero-crossing detector 30 is used for determining to gather output voltage V
OutThe time point of sampling.
As shown in figure 10, noninverting integrator comprises the level cross detecting device 300 with a plurality of threshold values.As shown in figure 10, with clock phase Ф
1Be applied to switch S
11, S
13, S
22And S
24, and with another phase place Ф
2Be applied to switch S
12, S
14And S
21Level cross detecting device 300 is used for a time point that intersects of detection node 100 and a plurality of predetermined levels as described below.Switch S
23Output control by level cross detecting device 300.The output of level cross detecting device 300 is used for determining to gather output voltage V
OutThe time point of sampling.
Threshold value is a predetermined voltage level.The threshold value of level cross detecting device 300 can be adjusted to and make the overshoot minimum.
For example, can make that being used for first threshold value that detects is the negative overshoot that is slightly less than first section expectation.This makes downward-sloping time minimization in second section.Equally, can make that the threshold value that is used for second section is second a section positive overshoot, so that offset the influence of overshoot.Perhaps, it is more negative to be used for first section the overshoot of threshold value comparable expectation during first section.This allows second section is positive slopes rather than negative slope as shown in figure 11.
Advantageously make the detection during the back segment become the most accurate detection.The height of the degree of accuracy that makes the detection during the back segment during than other section.This can be longer or power consumption is higher realizes by making delay during the back segment.
As shown in figure 12, noninverting integrator comprises the level cross detecting device, and it has two zero-crossing detectors---zero-crossing detector 1 (310) and zero-crossing detector 2 (320).As shown in figure 12, with clock phase Ф
1Be applied to switch S
11, S
13, S
22And S
24, and with another phase place Ф
2Be applied to switch S
12, S
14And S
21Zero-crossing detector 1 (310) and zero-crossing detector 2 (320) are used for a time point that intersects of detection node 100 and a plurality of predetermined levels as described below.Switch S
23Output control by zero-crossing detector 2 (320).The output of zero-crossing detector 2 (320) is used for determining to gather output voltage V
OutThe time point of sampling.
Select the threshold value of zero-crossing detector 1 (310) and zero-crossing detector 2 (320), overshoot is minimized.For example, can be used in the amount that be slightly less than first section in the overshoot of expectation of threshold value for bearing of zero-crossing detector 1 (310).This makes downward-sloping time minimization in second section.Equally, the threshold value that can be used in zero-crossing detector 2 (320) is the overshoot in positive second section, so that offset the influence of overshoot.Perhaps, it is more negative to be used for the overshoot of threshold value comparable expectation during first section of zero-crossing detector 1 (310).This allows zero-crossing detector 2 (320) is positive slopes rather than negative slope.
In other words, zero-crossing detector 1 (310) carries out rough detection, and zero-crossing detector 2 (320) carries out the essence detection.Therefore, advantageously make zero-crossing detector 2 (320) have higher degree of accuracy.
As shown in figure 13, noninverting integrator comprises the level cross detecting device, and it has two zero-crossing detectors---zero-crossing detector 1 (310) and zero-crossing detector 2 (320).As shown in figure 13, with clock phase Ф
1Be applied to switch S
11, S
13, S
22And S
24, and with another phase place Ф
2Be applied to switch S
12, S
14And S
21Zero-crossing detector 1 (310) and zero-crossing detector 2 (320) are used for a time point that intersects of detection node 100 and a plurality of predetermined levels as described below.Switch S
23Output control by zero-crossing detector 2 (320).The output of zero-crossing detector 2 (320) is used for determining to gather output voltage V
OutThe time point of sampling.
2 (320) two detecting devices of zero-crossing detector 1 (310) and zero-crossing detector have the zero threshold value of nominal.These two detection thresholds are by the voltage V of the input that is applied to zero-crossing detector 1 (310) and zero-crossing detector 2 (320) respectively
Tr1And V
Tr2Determine.Zero-crossing detector 1 (310) carries out rough detection, and zero-crossing detector 2 (320) carries out the essence detection.Therefore, advantageously make zero-crossing detector 2 (320) have higher degree of accuracy.
Notice that the above embodiments can be used as self-timed system.In this structure, do not apply the clock phase Ф of constant frequency
1And Ф
2, and clock phase is to derive from the output of zero-crossing detector 1 (310) and zero-crossing detector 2 (320).Figure 14 shows self-timing operation.
As shown in figure 14, in the end the section during phase place Ф
2End limit by detecting output.At Ф
2End after, clock phase Ф
1Beginning limit by short delay the such as logical delay.The short delay generally is necessary to guarantee the non-overlapping clock phase place.Clock phase Ф
1End determine by the zero cross detection of previous stage or next stage in a similar fashion.
Notice that each above-mentioned embodiment can be used for pipelined analog-digital quantizer, algorithm simulation-digital quantizer, switched capacitor amplifier, δ-σ modulator or self-timing algorithm simulation-digital quantizer.
It shall yet further be noted that each above-mentioned embodiment has single-ended signal path, therefore, expectation provides differential signal path.Each following embodiment provides differential signal path.
Figure 15 illustrates another example of the noninverting integrator of the half clock delay shown in having.In Figure 15, two signal paths are arranged, true path and complementary path.The true signal path comprises capacitor (C
S1p, C
I1pAnd C
S2p) and switch (S
11p, S
12p, S
13p, S
14p, S
21p, S
22p, S
23pAnd S
24p).The complementary signal path comprises capacitor (C
S1n, C
I1nAnd C
S2n) and switch (S
11n, S
12n, S
13n, S
14n, S
21n, S
22n, S
23nAnd S
24n).With clock phase Ф
1Be applied to switch S
11p, S
13p, S
22p, S
24p, S
11n, S
13n, S
22nAnd S
24n, and with another clock phase Ф
2Be applied to switch S
12p, S
14p, S
21p, S
12n, S
14nAnd S
21nZero-crossing detector 300 is used for the time point that detection node 110 and node 120 voltages cross one another.Sampling switch S
23pAnd S
23nOutput control by zero-crossing detector 300.The output of zero-crossing detector 300 is used for determining to gather output voltage V
OutpAnd V
OutnThe time point of sampling.
If waveform generator 20 is with capacitor C
S1p, C
I1p, C
S1nAnd C
I1nIn electric charge then node 110 and voltage difference (V of 120 in normal range of operation
1p-V
1n) locate to generate the differential voltage waveform with the mode of zero crossing at output node (130 and 140).In sequential chart shown in Figure 16, by the V that is used for of waveform generator 20 generations
OutpAnd V
OutnWaveform be shown forward slope and negative ramp respectively.
Zero-crossing detector 300 selectively has the overflow detected characteristics, and this feature is determined capacitor C
S1p, C
I1p, C
S1nAnd C
I1nIn electric charge beyond normal working range.Can be implemented in Ф by logical circuit
2Become the output V that makes zero-crossing detector 300 when hanging down
ZCBecome low.
At V
1Fail in the incident with zero crossing, at Ф
2Falling edge sampling.Simultaneously, logical circuit produces the sign of indication overflow.
Figure 17 illustrates another example of the noninverting integrator of the half clock delay shown in having.In Figure 17, two signal paths are arranged, true path and complementary path.The true signal path comprises capacitor (C
S1p, C
I1pAnd C
S2p) and switch (S
11p, S
12p, S
13p, S
14p, S
21p, S
22p, S
23pAnd S
24p).The complementary signal path comprises capacitor (C
S1n, C
I1nAnd C
S2n) and switch (S
11n, S
12n, S
13n, S
14n, S
21n, S
22n, S
23nAnd S
24n).With clock phase Ф
1Be applied to switch S
11p, S
13p, S
22p, S
24p, S
11n, S
13n, S
22nAnd S
24n, and with another clock phase Ф
2Be applied to switch S
12p, S
14p, S
21p, S
12n, S
14nAnd S
21nZero-crossing detector 300 is used for the time point that detection node 110 and node 120 voltages cross one another.Sampling switch S
23pAnd S
23nOutput control by zero-crossing detector 300.The output of zero-crossing detector 300 is used for determining to gather output voltage V
OutpAnd V
OutnThe time point of sampling.
If waveform generator 20 is with capacitor C
S1p, C
I1p, C
S1nAnd C
I1nIn electric charge then node 110 and voltage difference (V of 120 in normal working range
1p-V
1n) locate to generate the differential voltage waveform with the mode of zero crossing at output node (130 and 140).
Waveform generator can comprise a pair of current source (210 and 220), as shown in figure 17.220 couples of capacitor C of current source
S2pWith capacitor connected in series C
S1pAnd C
I1pCharging generates the forward slope.210 couples of capacitor C of current source
S2nWith capacitor connected in series C
S1nAnd C
I1nCharging generates negative ramp. Current source 210 and 220 nominal equal and opposite in direction opposite in signs.At Ф
2Section start, will export V
OutpAnd V
OutnBe short-circuited to known voltage V respectively simply
NEGAnd V
POS, its value is chosen to and guarantees voltage V
1p-V
1nBe in the normal working range with zero crossing and signal.
Figure 18 illustrates another example of the noninverting integrator of the half clock delay shown in having.In Figure 18, two signal paths are arranged, true path and complementary path.The true signal path comprises capacitor (C
S1p, C
I1pAnd C
S2p) and switch (S
11p, S
12p, S
13p, S
14p, S
21p, S
22p, S
23pAnd S
24p).The complementary signal path comprises capacitor (C
S1n, C
I1nAnd C
S2n) and switch (S
11n, S
12n, S
13n, S
14n, S
21n, S
22n, S
23nAnd S
24n).With clock phase Ф
1Be applied to switch S
11p, S
13p, S
22p, S
24p, S
11n, S
13n, S
22nAnd S
24n, and with another clock phase Ф
2Be applied to switch S
12p, S
14p, S
21p, S
12n, S
14nAnd S
21nZero-crossing detector 300 is used for the time point that detection node 110 and node 120 voltages cross one another.Sampling switch S
23pAnd S
23nOutput control by zero-crossing detector 300.The output of zero-crossing detector 300 is used for determining to gather output voltage V
OutpAnd V
OutnThe time point of sampling.
If waveform generator 20 is with capacitor C
S1p, C
I1p, C
S1nAnd C
I1nIn electric charge then node 110 and voltage difference (V of 120 in normal working range
1p-V
1n) locate to generate the differential voltage waveform with the mode of zero crossing at output node (130 and 140).
In Figure 18, waveform generator 20 can produce a plurality of sections in waveform, and changes the rate of change of output voltage.For the optimum operation, first section of may command is so that have the highest rate of change, and section subsequently has the rate of change that reduces gradually.Waveform generator 20 comprises common mode feedback circuit alternatively, with common mode output voltage (V
1p+ V
1n)/2 remain substantially constant.The zero crossing that detects by zero-crossing detector 300 makes waveform advance to next section.The output signal V of zero-crossing detector 300
ZC2Remain height, in back segment, detect zero crossing at waveform.
Figure 19 illustrates clock period of sequential chart of the multistage circuit of Figure 18.At Ф
2Section start, waveform generator 20 produces V
OutpAcclivity and to V
OutnTo downslope.Show voltage V
1p-V
1nAt time t
1Place and zero crossing.The output V of zero-crossing detector 300
ZC1At limited delay t
D1The back changes its state.Postpone t
D1The limited delay that expression is associated with zero-crossing detector 300.This state variation makes waveform advance to next section.
Because the t of zero-crossing detector 300
D1, voltage V
1p-V
1nOvershoot is greater than zero one less amount.Second section of waveform generator 20 is to be used for V
OutpTo downslope and be used for V
OutnAcclivity, to allow time t
2Another zero crossing at place.Postpone t second
D2Afterwards, the output V of zero-crossing detector 300
ZC2Become lowly, make switch S
23Transfer OFF to, the locking output voltage V
OutpAnd V
OutnSampling.
The delay t of second zero crossing
D2The delay t that can and be associated with first zero crossing
D1Different.Postpone t
D2Output voltage to sampling provides a spot of overshoot.The influence of overshoot can be shown the systematic offset in the sampled charge.In most of sampled-data circuits, this systematic offset is out of question.
Along with waveform segment advances, zero-crossing detector 300 preferably becomes more accurate in detecting zero crossing.First detection needn't be very accurate as rough detection.Therefore, the degree of accuracy that detection can be lower is carried out quickly.Last zero cross detection in the period demand is determined the degree of accuracy of output voltage.For this reason, last zero cross detection must be the most accurate.
Degree of accuracy, speed and power consumption can be traded off between zero cross detection one by one, to realize optimum overall performance.For example, first detects with less degree of accuracy and more has noise ground to carry out, but it is lower to carry out comparatively fast (the delay of lacking) and power.Last detection is more accurate and more undisturbedly carry out the power that consumption is bigger and slow (long delay) simultaneously.
Figure 20 illustrates another example of the noninverting integrator of the half clock delay shown in having.In Figure 20, two signal paths are arranged, true path and complementary path.The true signal path comprises capacitor (C
S1p, C
I1pAnd C
S2p) and switch (S
11p, S
12p, S
13p, S
14p, S
21p, S
22p, S
23pAnd S
24p).The complementary signal path comprises capacitor (C
S1n, C
I1nAnd C
S2n) and switch (S
11n, S
12n, S
13n, S
14n, S
21n, S
22n, S
23nAnd S
24n).With clock phase Ф
1Be applied to switch S
11p, S
13p, S
22p, S
24p, S
11n, S
13n, S
22nAnd S
24n, and with another clock phase Ф
2Be applied to switch S
12p, S
14p, S
21p, S
12n, S
14nAnd S
21nZero-crossing detector 300 is used for the time point that detection node 110 and node 120 voltages cross one another.Sampling switch S
23pAnd S
23nOutput control by zero-crossing detector 300.The output of zero-crossing detector 300 is used for determining sampling and outputting voltage V
OutpAnd V
OutnThe time point of sampling.
If waveform generator 20 is with capacitor C
S1p, C
I1p, C
S1nAnd C
I1nIn electric charge then node 110 and voltage difference (V of 120 in normal working range
1p-V
1n) locate to generate the differential voltage waveform with the mode of zero crossing at output node (130 and 140).
In Figure 20, waveform generator can comprise a plurality of current sources. Current source 210 and 220 pairs are at true output V
OutpThe place generates the capacitor charging of two sections ramp waveforms. Current source 230 and 240 pairs are at complementary output V
OutnThe place generates the capacitor charging of two sections ramp waveforms.
At Ф
2Section start, will export V
OutpAnd V
OutnBe short-circuited to known voltage V respectively simply
NEGAnd V
POS, its value is chosen to and guarantees voltage V
1p-V
1nBe in the normal working range with zero crossing and signal.
During first section, current source 210 and 230 points to output V respectively
OutpAnd V
Outn, and during second section, current source 220 points to the output that generates two different slope degree of tilt with 240.This is the switch S of suitably being controlled by zero-crossing detector 300 by being provided with
16p, S
17p, S
16nAnd S
17nRealize.
Figure 21 illustrates another example of the noninverting integrator of the half clock delay shown in having.In Figure 21, two signal paths are arranged, true path and complementary path.The true signal path comprises capacitor (C
S1p, C
I1pAnd C
S2p) and switch (S
11p, S
12p, S
13p, S
14p, S
21p, S
22p, S
23pAnd S
24p).The complementary signal path comprises capacitor (C
S1n, C
I1nAnd C
S2n) and switch (S
11n, S
12n, S
13n, S
14n, S
21n, S
22n, S
23nAnd S
24n).With clock phase Ф
1Be applied to switch S
11p, S
13p, S
22p, S
24p, S
11n, S
13n, S
22nAnd S
24n, and with another clock phase Ф
2Be applied to switch S
12p, S
14p, S
21p, S
12n, S
14nAnd S
21nZero-crossing detector 300 is used for the time point that detection node 110 and node 120 voltages cross one another.Sampling switch S
23pAnd S
23nOutput control by zero-crossing detector 300.The output of zero-crossing detector 300 is used for determining to gather output voltage V
OutpAnd V
OutnThe time point of sampling.
Figure 21 also illustrates common mode feedback circuit 400.Common mode feedback circuit is similar to the common mode feedback circuit in the conventional fully differential operational amplifier.Common mode amplifier 400 is with output common mode voltage (V
Outp+ V
OutnDifference between the output common mode voltage of)/2 and expectation is amplified.The output of common mode amplifier 400 provide negative feedback with Control current source 210 and 220 so that output common mode voltage is kept constant.
Perhaps, the output controllable current source 230 and 240 of common mode amplifier 400.Can during all or arbitrary section, use common-mode feedback.Preferably only during first section, use common-mode feedback, keep current source 220 constant simultaneously and with current source 240 couplings.
Figure 22 illustrates another example of the noninverting integrator of the half clock delay shown in having.In Figure 22, two signal paths are arranged, true path and complementary path.The true signal path comprises capacitor (C
S1p, C
I1pAnd C
S2p) and switch (S
11p, S
12p, S
13p, S
14p, S
21p, S
22p, S
23pAnd S
24p).The complementary signal path comprises capacitor (C
S1n, C
11nAnd C
S2n) and switch (S
11n, S
12n, S
13n, S
14n, S
21n, S
22n, S
23nAnd S
24n).With clock phase Ф
1Be applied to switch S
11p, S
13p, S
22p, S
24p, S
11n, S
13n, S
22nAnd S
24n, and with another clock phase Ф
2Be applied to switch S
12p, S
14p, S
21p, S
12n, S
14nAnd S
21nZero-crossing detector 300 is used for the time point that detection node 110 and node 120 voltages cross one another.Sampling switch S
23pAnd S
23nOutput control by zero-crossing detector 300.The output of zero-crossing detector 300 is used for determining to gather output voltage V
OutpAnd V
OutnThe time point of sampling.
In Figure 22, capacitor C
CMpAnd C
CMnInput at common mode amplifier 10 produces V
OutpAnd V
OutnCommon mode voltage V
OCMOS transistor M
1And M
2Be used as current source to produce electric current I respectively
1pAnd I
2pThe output control transistor M of common mode amplifier 10
1And M
2Grid.The negative feedback of gained impels the common mode output voltage V
OCBecome the common mode voltage of expectation.
Perhaps, the output may command of common mode amplifier 10 produces electric current I respectively
1nAnd I
2nCurrent source.Can all the section or arbitrary section during use common-mode feedback.Preferably only during first section, use common-mode feedback, simultaneously with electric current I
2pKeep constant and and electric current I
2nCoupling.
Although illustrated and described each example of the present invention and embodiment, those skilled in the art will recognize specific description and accompanying drawing that the spirit and scope of the present invention are not limited to this paper, but extend to various modifications and variations.
Claims (19)
1. switched-capacitor circuit comprises:
The level cross detecting device, it has input end and output terminal, is used for generating when the input end signal of described level cross detecting device intersects with predetermined level the level cross detection signal;
A plurality of capacitors are coupled to described level cross detecting device in its operation;
Sampling switch is coupled to the output terminal of described level cross detecting device in its operation; And
Waveform generator is coupled to the input end of described a plurality of capacitor and described level cross detecting device in its operation, produces the input end that predetermined waveform is applied to described level cross detecting device.
2. switched-capacitor circuit as claimed in claim 1 is characterized in that, described predetermined waveform is a ramp waveform.
3. switched-capacitor circuit as claimed in claim 1 is characterized in that, described level cross detecting device is a zero-crossing detector.
4. switched-capacitor circuit as claimed in claim 1 is characterized in that, described waveform generator produces a plurality of predetermined waveforms.
5. switched-capacitor circuit as claimed in claim 4 is characterized in that described waveform generator provides one of described a plurality of predetermined waveforms, with the voltage mistake of compensation by the limited delay generation that is associated with described level cross detecting device.
6. switched-capacitor circuit comprises:
The first level cross detecting device has input end and output terminal, is used for generating when the input end signal of described level cross detecting device intersects with first predetermined level first level cross detection signal;
The second level cross detecting device has input end and output terminal, is used for generating when the input end signal of described level cross detecting device intersects with second predetermined level second level cross detection signal;
A plurality of capacitors are coupled to the described first level cross detecting device and the second level cross detecting device in its operation;
Sampling switch is coupled to the output terminal of the described second level cross detecting device in its operation; And
Waveform generator, be coupled to the described input end of described a plurality of capacitor and described first level cross detecting device and the described second level cross detecting device in its operation, produce the input end that predetermined waveform is applied to the described first level cross detecting device and the second level cross detecting device.
7. switched-capacitor circuit as claimed in claim 6 is characterized in that, described predetermined waveform is a ramp waveform.
8. switched-capacitor circuit as claimed in claim 6 is characterized in that, the described first and second level cross detecting devices are zero-crossing detectors.
9. switched-capacitor circuit as claimed in claim 6 is characterized in that, described waveform generator produces a plurality of predetermined waveforms.
10. switched-capacitor circuit as claimed in claim 9, it is characterized in that, described waveform generator provides one of described a plurality of predetermined waveforms, with the voltage mistake of compensation by the limited delay generation that is associated with the second level cross detecting device with the described first level cross detecting device.
11. a switched-capacitor circuit comprises:
First switched capacitor network has the input end of receiving circuit input voltage;
The level cross detecting device has output terminal and input end, generates the level cross detection signal when intersecting with predetermined level with the signal at the input end of described level cross detecting device;
The second switch capacitance network is coupled to the output terminal of described level cross detecting device in its operation; And
Waveform generator is coupled to the input end of described second switch capacitance network and described level cross detecting device in its operation, produces the input end that predetermined waveform is applied to described level cross detecting device.
12. switched-capacitor circuit as claimed in claim 11 is characterized in that, described predetermined waveform is a ramp waveform.
13. switched-capacitor circuit as claimed in claim 11 is characterized in that, described level cross detecting device is a zero-crossing detector.
14. switched-capacitor circuit as claimed in claim 11 is characterized in that described waveform generator produces a plurality of predetermined waveforms.
15. switched-capacitor circuit as claimed in claim 14 is characterized in that, described waveform generator provides one of described a plurality of predetermined waveforms, with the voltage mistake of compensation by the limited delay generation that is associated with described level cross detecting device.
16. a method that is used for the sampled analog signal, described method comprises:
(a) use the switched capacitor network samples input voltage;
(b) determine when that the node voltage of described switched capacitor network and predetermined level intersect; And
(c) when the node voltage of determining described switched capacitor network intersects with described predetermined level, provide the output voltage sampling of described switched capacitor network.
17. method as claimed in claim 16 is characterized in that, described predetermined level is a zero voltage level.
18. a method that is used for the sampled analog signal, described method comprises:
(a) use the switched capacitor network samples input voltage;
(b) determine when that the node voltage of described switched capacitor network and first predetermined level intersect;
(c) determine when that the node voltage of described switched capacitor network and second predetermined level intersect; And
(d) when intersecting with described second predetermined level, the node voltage of determining described switched capacitor network provides the sampling of the output voltage of described switched capacitor network.
19. method as claimed in claim 18 is characterized in that, described first and second predetermined levels are zero voltage level.
Applications Claiming Priority (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US59541405P | 2005-07-01 | 2005-07-01 | |
| US60/595,414 | 2005-07-01 | ||
| US59549305P | 2005-07-11 | 2005-07-11 | |
| US60/595,493 | 2005-07-11 | ||
| US11/454,275 US7486115B2 (en) | 2005-07-01 | 2006-06-16 | Sampled-data circuits using zero crossing detection |
| US11/454,275 | 2006-06-16 | ||
| PCT/US2006/026445 WO2007006027A1 (en) | 2005-07-01 | 2006-06-30 | Sampled-data circuits using zero crossing detection |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101253575A CN101253575A (en) | 2008-08-27 |
| CN101253575B true CN101253575B (en) | 2010-11-03 |
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ID=39956067
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2006800315715A Active CN101253575B (en) | 2005-07-01 | 2006-06-30 | Sampled-data circuits using zero crossing detection |
| CN2006800315518A Expired - Fee Related CN101253574B (en) | 2005-07-01 | 2006-06-30 | Sampled-data circuits using zero crossing detection |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2006800315518A Expired - Fee Related CN101253574B (en) | 2005-07-01 | 2006-06-30 | Sampled-data circuits using zero crossing detection |
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| CN115643137B (en) * | 2017-05-22 | 2024-06-07 | 康杜实验室公司 | Apparatus and method for multi-stage sampler with greater gain |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN87104460A (en) * | 1987-06-25 | 1988-04-27 | 哈尔滨电工学院 | Digital feedback double sampling high precision analog-digital converter |
| CN1061851A (en) * | 1991-09-18 | 1992-06-10 | 黑龙江省电力工业局 | Three phase if harmonic analysis circuit |
| US6167748B1 (en) * | 1998-08-31 | 2001-01-02 | Lockheed Martin Energy Research Corporation | Capacitively readout multi-element sensor array with common-mode cancellation |
| CN1396710A (en) * | 2001-07-09 | 2003-02-12 | 三星电子株式会社 | Device for testing phase difference by zero cross character of input signal and its phaselocked loop circuit |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4429282A (en) * | 1982-02-08 | 1984-01-31 | Bell Telephone Laboratories, Incorporated | Offset-nulled sample-and-hold amplifier |
| US4800333A (en) * | 1986-12-29 | 1989-01-24 | General Electric Company | Switched-capacitor watthour meter circuit having reduced capacitor ratio |
| GB2247124B (en) * | 1987-10-28 | 1992-07-01 | Burr Brown Corp | Demodulator circuit |
| US5121061A (en) * | 1990-08-16 | 1992-06-09 | Milton Roy Company | Phase correction for streaming current signal |
| KR100370095B1 (en) * | 2001-01-05 | 2003-02-05 | 엘지전자 주식회사 | Drive Circuit of Active Matrix Formula for Display Device |
-
2006
- 2006-06-30 CN CN2006800315715A patent/CN101253575B/en active Active
- 2006-06-30 CN CN2006800315518A patent/CN101253574B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN87104460A (en) * | 1987-06-25 | 1988-04-27 | 哈尔滨电工学院 | Digital feedback double sampling high precision analog-digital converter |
| CN1061851A (en) * | 1991-09-18 | 1992-06-10 | 黑龙江省电力工业局 | Three phase if harmonic analysis circuit |
| US6167748B1 (en) * | 1998-08-31 | 2001-01-02 | Lockheed Martin Energy Research Corporation | Capacitively readout multi-element sensor array with common-mode cancellation |
| CN1396710A (en) * | 2001-07-09 | 2003-02-12 | 三星电子株式会社 | Device for testing phase difference by zero cross character of input signal and its phaselocked loop circuit |
Non-Patent Citations (1)
| Title |
|---|
| US 6167748 B1,全文. |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101253575A (en) | 2008-08-27 |
| CN101253574A (en) | 2008-08-27 |
| CN101253574B (en) | 2012-08-22 |
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