CN101236541A - Centralized control interrupt controller and its interrupt control method - Google Patents
Centralized control interrupt controller and its interrupt control method Download PDFInfo
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Abstract
The invention relates to an interrupt controller for centralized control and an interrupt control method. The method of the invention comprises the following steps that: the interrupt controller receives and stores secondary interrupt signals which are transmitted by one or a plurality of interrupt sources and generates a primary interrupt signal for each interrupt source; one primary interrupt signal is then selected from primary interrupt signals, stored and reported to a higher body; an interrupt processing device responds to interrupt after receiving the primary interrupt signal, and then responded secondary interrupt signals and primary interrupt signals are eliminated. The interrupt controller of the invention comprises a primary interrupt register, a primary interrupt selection circuit, a plurality of secondary interrupt processing circuits and a plurality of primary interrupt generation circuits. The invention can realize centralized control for interrupt of the interrupt sources.
Description
Technical field
The present invention relates to interrupt control technique, relate in particular to a kind of central controlled interruptable controller and interrupt control method thereof.
Background technology
In the system that contains CPU (Central Processor Unit), cooperative work of software and hardware is very important.Event occurs when needing software to handle when hardware, and common method is to use interrupt mode notice software.
The common interrupt control method of prior art be to secondary and the interruption below the secondary in each inside modules, and interruptable controller only is responsible for collecting and is interrupted and send to specific CPU interrupting.As shown in Figure 1, whether the enable signal of the one-level look-at-me that each interrupt source is reported up and each interrupt source is sent into door and is done AND-operation earlier, have this one-level look-at-me to report to CPU with decision.Have when interrupting producing to the interruptable controller report simultaneously as a plurality of interrupt sources, interruptable controller is therefrom chosen some interrupt source according to the priority rule of setting (as fixed priority) and is reported to CPU.After CPU obtains look-at-me, from interruptable controller, can obtain interrupt source information.CPU removes to obtain interrupting information reaching or above grade two there to each interrupt source again, and handles accordingly according to these information.
This interruptable controller is simple in structure, is fit to have only a processor, and the less single system of interrupt source uses.Yet based on the system of this interruptable controller, each interrupt source all needs oneself to have a sub-Interrupt Control System, when which interruption is reported interruptable controller with decision.Different devisers has different understanding to system break and can not take the interruption situation of other interrupt source into account, has so just reduced the efficient of system.In addition, for a plurality of processors, or different processor all can't be handled when needing multi-form look-at-me.
Summary of the invention
The technical problem to be solved in the present invention provides and a kind ofly can realize central controlled interruptable controller and interrupt control method thereof.
In order to address the above problem, the invention provides a kind of central controlled interrupt control method, may further comprise the steps:
(a) after interruptable controller is received the secondary look-at-me of one or more interrupt sources transmissions, described secondary look-at-me is temporary, and for sending one-level look-at-me of each interrupt source generation of described secondary look-at-me;
(b) described interruptable controller is selected an one-level look-at-me again from described one-level look-at-me, and the Interrupt Process device is kept in and reported to this one-level look-at-me of selecting;
(c) after described Interrupt Process device is received the one-level look-at-me that reports, call the interrupt service routine response and interrupt, remove secondary look-at-me and the one-level look-at-me that has responded afterwards.
Further, above-mentioned interrupt control method also can have following characteristics:
It still is quick interruption form as the regular interrupt form that step (a) disposes the current one-level look-at-me of using earlier before, and interrupt vector table also is set when using the regular interrupt form simultaneously;
The described interruptable controller of step (b) sends the regular interrupt form or interrupts the one-level look-at-me of form fast to described Interrupt Process device according to described configuration, when adopting the regular interrupt form, interruptable controller also is provided with corresponding interrupt vector, and the Interrupt Process device reads the entry address that described interrupt vector is obtained corresponding interrupt service routine.
Further, above-mentioned interrupt control method also can have following characteristics:
Described Interrupt Process device has a plurality of, and described interruptable controller comprises a plurality of sub-controllers, and each sub-controller is corresponding with an Interrupt Process device, sends the one-level look-at-me to this corresponding Interrupt Process device.
Further, above-mentioned interrupt control method also can have following characteristics:
At least one Interrupt Process device in the described Interrupt Process device can send soft interrupt signal by the sub-controller to other Interrupt Process device correspondence, calls out soft interruption between a plurality of Interrupt Process devices.
Further, above-mentioned interrupt control method also can have following characteristics:
The described interruptable controller of step (a) is temporarily stored in described secondary look-at-me in the secondary interrupt status register;
The described interruptable controller of step (b) is temporarily stored in described one-level look-at-me in the one-level interrupt register;
In the step (c), when described Interrupt Process device calls interrupt service routine response interruption, secondary look-at-me in current all secondary interrupt status registers is locked, after removing the secondary look-at-me, remove described locking again, allow described secondary interrupt status register to keep in new look-at-me.
Further, above-mentioned interrupt control method also can have following characteristics:
In the step (c), as as described in before Interrupt Process device locking back and the release, interrupt source is sent new secondary look-at-me, then described interruptable controller interrupts this secondary look-at-me in the shadow register as the temporary secondary to correspondence of shadow look-at-me, after release, again that described shadow look-at-me is temporary in the secondary interrupt status register of correspondence.
Further, above-mentioned interrupt control method also can have following characteristics:
The look-at-me that the described interruptable controller of step (b) sends to the Interrupt Process device adopts a kind of or a kind of according to configuration selection from following form in the following form: high level is effective, low level is effective, and rising edge is effective, negative edge is effective, high impulse is effective and low pulse is effective.
Further, above-mentioned interrupt control method also can have following characteristics:
The described interruptable controller of step (b) is to select an one-level look-at-me that current priority is the highest from the one-level look-at-me of each interrupt source, the priority of the one-level look-at-me of each interrupt source is configured by register, and each secondary look-at-me and/or one-level look-at-me have a corresponding enable signal.
Further, above-mentioned interrupt control method also can have following characteristics:
The described secondary look-at-me of step (a) adopts impulse form, and described interruptable controller also detects the lasting duration of the secondary look-at-me of receiving from interrupt source, is reaching when setting duration just as effectively the secondary look-at-me is temporary.
Central controlled interruptable controller provided by the invention comprises that one-level interrupt register, one-level are interrupted the selection circuit, some groups of secondary Interrupt Process circuit, some one-levels are interrupted generative circuit, wherein:
Described every group of secondary Interrupt Process circuit comprises one or more secondary Interrupt Process circuit, is used to receive one or more secondary look-at-mes of same interrupt source and keep in;
The output of described every group of secondary Interrupt Process circuit is connected to a described one-level and interrupts generative circuit, and the one-level look-at-me that described one-level interruption generative circuit is used to export corresponding to this group secondary look-at-me interrupts selecting circuit to described one-level;
Described one-level interruption selection circuit is used for selecting an one-level look-at-me from the one-level look-at-me of each interrupt source and also this one-level look-at-me is temporarily stored in the described one-level interrupt register;
Described one-level interrupt register is used for temporary one-level look-at-me and reports the Interrupt Process device.
Further, above-mentioned interruptable controller also can have following characteristics:
Described secondary Interrupt Process circuit comprises secondary interrupt trap circuit and secondary interruption status register circuit, and a plurality of secondary interruption status register circuits of an interrupt source have been formed the secondary interrupt status register of this interrupt source, wherein:
Described secondary interrupt trap circuit is used to receive the locking signal of interrupting from the secondary look-at-me of the impulse form of interrupt source and secondary, reach at the lasting duration of secondary look-at-me and to set duration and locking signal when invalid, just to described secondary interruption status register circuit output secondary look-at-me;
Described secondary interruption status register circuit is used to receive the secondary look-at-me from secondary interrupt trap circuit, described secondary look-at-me is kept in and is outputed to corresponding one-level and interrupt generative circuit; And be received in effective interrupt clear signal between lockup period, when described clear signal is effective, remove temporary secondary look-at-me;
Described one-level is interrupted generative circuit and is used for each secondary look-at-me of input is carried out exporting after the inclusive-OR operation.
Further, above-mentioned interruptable controller also can have following characteristics:
Described secondary Interrupt Process circuit comprises that also a secondary interrupts the shadow register circuit, and a plurality of secondarys of an interrupt source interrupt the secondary interruption shadow register that the shadow register circuit has been formed this interrupt source, wherein:
Described secondary interrupt trap circuit also is used for reaching at the lasting duration from the secondary look-at-me of interrupt source sets duration and described locking signal when effective, just interrupts shadow register circuit output secondary look-at-me to described secondary;
Described secondary interruption shadow register circuit is used to receive secondary look-at-me and the described locking signal from secondary interrupt trap circuit, when described locking signal is effective, as receive that the secondary look-at-me is then temporary as the shadow look-at-me, and after locking signal is invalid, remove temporary shadow look-at-me;
Described secondary interrupt status register also receives the shadow look-at-me of interrupting the shadow register circuit from described secondary, after removing the secondary look-at-me, as exists the shadow look-at-me then it to be kept in and outputs to corresponding one-level interruption generative circuit.
Further, above-mentioned interruptable controller also can have following characteristics:
Described secondary interrupt trap circuit further comprises: capturing unit, be used to receive secondary look-at-me from the impulse form of interrupt source, and only output continues the secondary look-at-me that duration reaches the setting duration; Lock cell is used for when locking signal is effective, and the shielding capturing unit outputs to the secondary look-at-me of secondary interruption status register circuit, when locking signal is invalid, just allows capturing unit output secondary look-at-me to secondary interruption status register circuit;
Described secondary interruption status register circuit further comprises: collecting unit is used to receive the secondary look-at-me of secondary interrupt trap circuit output and shadow look-at-me and the output that secondary interrupts the output of shadow register circuit; The level holding unit is used for when the look-at-me of collecting unit output impulse form it is temporary, and keeps before being eliminated and exports this look-at-me; Clearing cell is used for the interrupt clear signal of received pulse form, and the look-at-me that the level holding unit is temporary is removed;
Described secondary interrupts the shadow register circuit and further comprises: lock cell, be used for when locking signal is effective, allow capturing unit output secondary look-at-me to the level holding unit, level holding unit output shadow look-at-me is to secondary interruption status register circuit; When locking signal is invalid, shield described capturing unit and output to the secondary look-at-me that secondary interrupts level holding unit in the shadow register circuit, and secondary interrupts the shadow look-at-me that level holding unit in the shadow register circuit outputs to secondary interruption status register circuit; The level holding unit, being used for when the secondary look-at-me of lock cell output impulse form it being kept in is the shadow look-at-me, and this shadow look-at-me of output arrives secondary interruption status register circuit before being eliminated; Clearing cell, be used for locking signal by effectively become invalid after, the clear signal of an impulse form of output is interrupted the temporary shadow look-at-me of level holding unit in the shadow register circuit with secondary and is removed.
Further, above-mentioned interruptable controller also can have following characteristics:
Described interruptable controller also comprises two and door, the output of described one-level interrupt register is connected to described two and door, one of them is input as quick interruption enable signal with another of door, and the look-at-me that should export quick interruption form with door is to described Interrupt Process device; Another is input as the regular interrupt enable signal with another of door, should with the look-at-me of door output regular interrupt form and interrupt vector to described Interrupt Process device.
Further, above-mentioned interruptable controller also can have following characteristics:
Described interruptable controller comprises a plurality of sub-controllers, each sub-controller includes the one-level interrupt register, one-level interrupts selecting circuit, some groups of secondary Interrupt Process circuit, some one-levels to interrupt generative circuit, is used for sending the one-level look-at-me to each self-corresponding Interrupt Process device.
Further, above-mentioned interruptable controller also can have following characteristics:
Described two of being connected with one-level interruption selection circuit also comprise a format conversion circuit afterwards with door, be used for the format conversion of the one-level look-at-me of one-level interrupt register output is other form, described form be that high level is effective, low level is effective, rising edge is effective, negative edge is effective, high impulse is effective and low pulse effectively in a kind of.
Further, above-mentioned interruptable controller also can have following characteristics:
Described Interrupt Process device is CPU, and the part or all of look-at-me in the described interruptable controller all has corresponding enable signal.
Further, above-mentioned interruptable controller also can have following characteristics:
Described one-level interrupts selecting circuit to be used for selecting an one-level look-at-me that current priority is the highest from the one-level look-at-me of each interrupt source, and the priority of the one-level look-at-me of each interrupt source is configured by register.
As from the foregoing, the present invention can have following characteristics:
1) interruptable controller receives the secondary look-at-me of each interrupt source, and generates corresponding one-level look-at-me according to different interrupt source, i.e. interrupt control centralized management.Each secondary look-at-me and one-level look-at-me can enable respectively.
2) each interrupt source can have a plurality of secondary look-at-me inputs, has solved the not enough problem of number of interruptions to a certain extent.
3) the secondary look-at-me of each interrupt source has the fixed priority of other secondary look-at-me relatively, and the one-level look-at-me priority of each interrupt source is configured by register by software.When several one-level look-at-mes produce simultaneously, determine that according to priority which one-level look-at-me is current interruption.When several priority of interrupt are identical, determine that according to interrupt number which one-level look-at-me is current interruption.
4) all support regular interrupt (IRQ) and interrupt (FIQ), regular interrupt support vector table fast for each CPU.
5) various forms is supported in the interruption that produces.
6) adopt locking-unlocking mechanism and shadow register to guarantee that the interruption of each interrupt source report does not repeat, and does not lose.
7) support interrupt retransmissions mechanism.
8) support to cry mutually between each CPU soft interruption.
Description of drawings
Fig. 1 is the synoptic diagram of existing interruptable controller.
Fig. 2 is the synoptic diagram of embodiment of the invention Interrupt Control System.
Fig. 3 is the functional block diagram of a sub-controller of the interruptable controller among Fig. 2.
Fig. 4 is the concrete structure figure of secondary Interrupt Process circuit among Fig. 3.
Fig. 5 is the signal waveforms of secondary interrupt trap circuit among Fig. 4.
Fig. 6 is the waveform synoptic diagram that causes the secondary look-at-me to be lost.
Fig. 7 is the usage oscillogram of embodiment of the invention locking-unlocking mechanism and shadow register.
Fig. 8 is the corresponding relation synoptic diagram of embodiment of the invention secondary interrupt status register and priority.
Fig. 9 is that embodiment of the invention interruptable controller produces the workflow diagram that interrupts at a certain CPU.
Embodiment
In a system, sometimes can there be a more than CPU.In this case, most ways are to adopt a plurality of interruptable controllers.And interruptable controller of the present invention can carry out centralized control at the system of two or more CPU, the non-interfering interruption that focuses on to a plurality of CPU.
Be example with two CPU below, in conjunction with the accompanying drawings the specific embodiment of the present invention elaborated.
Fig. 2 is the synoptic diagram of present embodiment Interrupt Control System.Comprise an interruptable controller and connected two CPU, i.e. CPU1 and CPU2.Interruptable controller comprises two sub-controllers, corresponds respectively to CPU1 and CPU2, is called CPU1 sub-controller and CPU2 sub-controller.The CPU1 sub-controller be input as the secondary look-at-me of giving CPU1, the CPU2 sub-controller be input as the secondary look-at-me of giving CPU2.Simultaneously, the interruptable controller of present embodiment is supported soft interruption, and each CPU can call out the soft interruption of other CPU by this interruptable controller, promptly gives the soft interruption that also has other CPU to call out to this CPU of each sub-controller.In the present embodiment, each CPU can have two kinds of one-level look-at-me forms, and one is regular interrupt (IRQ), and another is to interrupt (FIQ) fast.This interruptable controller support sends this two kinds of one-level look-at-mes to each CPU, and promptly to output to the one-level look-at-me of corresponding CPU can be regular interrupt (IRQ) and interrupt vector thereof to each sub-controller, also can be quick interruption (FRQ).
Each sub-controller structure among Fig. 2 is identical, and Fig. 3 is the structural representation of interruptable controller sub-controller, has omitted clock signal among the figure.
As shown in the figure, each sub-controller comprises some groups of secondary Interrupt Process circuit, and every group of secondary Interrupt Process circuit is used for a plurality of secondary look-at-mes from same interrupt source are handled, and generates an one-level look-at-me.As shown in the figure, all comprise relevant locking signal such as the INT1-MASK of the corresponding one-level look-at-me of this group in the input of each the secondary Interrupt Process circuit in same group, INT2-MASK ..., INTm-MASK.Other input signal of each secondary Interrupt Process circuit comprises from a secondary look-at-me of interrupt source and the enable signal enable of this secondary look-at-me.As the secondary look-at-me that is input to each secondary Interrupt Process circuit in first group is respectively INT12-1 ..., INT12-n1; Be input in the secondary of each secondary Interrupt Process circuit in second group to signal is respectively INT22-1 ..., INT22-n2, or the like.
In each sub-controller, the output of a plurality of secondary Interrupt Process circuit on the same group is connected to the one-level interruption generative circuit that a disjunction gate constitutes, this disjunction gate output one is corresponding to the one-level look-at-me of this group secondary look-at-me, the one-level look-at-me that each group generates is imported one-level again and is interrupted selecting circuit, this one-level interrupts selecting circuit to be connected with the one-level interrupt register, when having effectively interruption, the one-level look-at-me that current priority is the highest outputs to the one-level interrupt register, this one-level interrupt register is used for buffer memory one-level look-at-me, its output is connected to two and door, one of them is input as the FIQ enable signal with another of door, should with door output FIQ look-at-me to the corresponding CPU of this sub-controller; Another is input as the IRQ enable signal with another of door, should with door output IRQ look-at-me and IRQ interrupt vector to the corresponding CPU of this sub-controller.
Fig. 4 is the concrete structure figure of present embodiment secondary Interrupt Process circuit, comprises with lower unit: secondary interrupt trap circuit, secondary interrupt shadow register circuit and secondary interruption status register circuit.A plurality of secondarys of an interrupt source interrupt the secondary interruption shadow register that the shadow register circuit has been formed this interrupt source, and a plurality of secondary interruption status register circuits of an interrupt source have been formed the secondary interrupt status register of this interrupt source.
Because when Interrupt Process, need clear the interruption, if from the secondary look-at-me of interrupt source with high level signal as look-at-me, then need interruptable controller to go to interrupt clearly to interrupt source, all very inconvenient on control and circuit, so present embodiment has adopted pulse signal.In interruptable controller, be converted into high level signal, so just can only in interruptable controller, finish interrupt operation clearly.In addition, the burr signal that produces for fear of circuit causes wrong report to be interrupted, present embodiment also requires should continue certain time length from the secondary look-at-me of interrupt source, will comprise two rising edges or the negative edge (present embodiment is to get two clock period) of time clock at least.Therefore be provided with secondary interrupt trap circuit.
Secondary interrupt trap circuit further comprises: capturing unit, be used to receive secondary look-at-me from the impulse form of interrupt source, and only output continues the secondary look-at-me that duration reaches the setting duration; Lock cell is used for when locking signal is effective, and the shielding capturing unit outputs to the secondary look-at-me of secondary interruption status register circuit, when locking signal is invalid, just allows capturing unit output secondary look-at-me to secondary interruption status register circuit.
As shown in Figure 4, secondary interrupt trap circuit comprises a d type flip flop D11, two and door A11, A12 and a not gate N11.Wherein D11 and A11 constitute capturing unit, and A12 and N11 constitute lock cell.From the secondary look-at-me int of interrupt source be input to d type flip flop D11 input end D and with the input end of door A11, this D11 output signal int_a to another input end of door A11, with door A11 signal int and int_a are made secondary look-at-me int_valid after output is caught after the AND operation.Corresponding locking signal mask be input to not gate N11 anti-phase after and with the output signal int_valid of door A11 as and the input signal of door A12, be connected to secondary interruption status register circuit with the output of door A12.
From figure as can be seen, capturing function is mainly realized by trigger D11 with door A11.When interrupt source is sent normal secondary look-at-me here, signal int, int_a, the waveform of int_valid and OUT as shown in Figure 5, wherein the OUT signal is the secondary look-at-me of secondary interruption status register circuit output.As can be seen, do not comprise two rising edge clocks or negative edge clock period if the secondary look-at-me continues duration, then just do after the AND operation not can output pulse signal for int and int_a, thereby can not produce effective secondary look-at-me.
Further, because the secondary look-at-me of each interrupt source all is pooled in the interruptable controller, therefore CPU may need a plurality of secondary look-at-mes of single treatment, thereby the interrupt response of causing and processing time are long, and this moment, the secondary interrupt status register can not write down new secondary look-at-me again.Therefore present embodiment adopts locking-unlocking mechanism in interruptable controller; promptly when CPU responds certain one-level look-at-me; CPU is by the corresponding lock register of configuration; the secondary interrupt status register that notice interruptable controller protection is current guarantees that the secondary look-at-me is merely able to be removed by software and no longer writes down the new secondary look-at-me that the interrupt source before the release is sent.After the CPU handling interrupt, remove lock register again and carry out release.
As shown in Figure 4.The output signal mask of lock register (not shown) (high level is effective) is carrying out AND operation with door A12 with the output signal int_valid of door A11 behind not gate N11, when signal mask is effective, signal int_valid conductively-closed, when signal mask was invalid, signal int_valid was output to secondary interruption status register circuit.So can realize the function of above-mentioned locking-unlocking.
After software responses and handling interrupt program, need to remove this secondary look-at-me, and clear priority of interrupt is the highest.If there is this moment this secondary look-at-me to produce again, can cause losing of secondary look-at-me, this situation is as shown in Figure 6.In order to address this problem, present embodiment interrupts the interruption that the temporary lock-out state of shadow register receives with secondary.Promptly this interrupt source before the release is sent the secondary look-at-me, no longer send into the secondary interrupt status register, and it is temporary to send into corresponding secondary interruption shadow register.Again that secondary look-at-me temporary in all shadow registers is temporary to the secondary interrupt status register after the release, guarantee to interrupt can not losing.The oscillogram of locking-unlocking mechanism and shadow register as shown in Figure 7.
Secondary interrupts the shadow register circuit and further comprises lock cell, level holding unit and clearing cell.Wherein, lock cell is used for when locking signal is effective, allows capturing unit output secondary look-at-me to the level holding unit, and level holding unit output shadow look-at-me is to secondary interruption status register circuit; When locking signal was invalid, the shielding capturing unit outputed to the secondary look-at-me of level holding unit, and the level holding unit outputs to the shadow look-at-me of secondary interruption status register circuit; It is the shadow look-at-me that the level holding unit is used for when the secondary look-at-me of lock cell output impulse form it being kept in, and this shadow look-at-me of output arrives secondary interruption status register circuit before being eliminated; Clearing cell be used for locking signal by effectively become invalid after, the clear signal of an impulse form of output, the shadow look-at-me that the level holding unit is temporary is removed.
A kind of example of the physical circuit of secondary interruption shadow register circuit as shown in Figure 4, wherein lock cell is by forming with door A21 and A24, the level holding unit is by d type flip flop D23, with door A22, A23, not gate N21 and or the door O21, clearing cell comprises d type flip flop D21, D22, with door A25 and not gate N22, N23.In the secondary interrupt trap circuit with the secondary look-at-me of door A11 output after doing AND operation with door A21 and enable signal enable and locking signal mask, output to respectively not gate N21 and or the door O21, or the door O21 another be input as with the door A22 output, be used for the output of trigger D23 and not gate N21 is done and computing with door A22.Or the door output of O21 and shadow clear signal clear-shadow with door A23 in do with computing after output to trigger D23 again.Can analyze by above circuit, when with positive pulse of door A21 output, a warp or a door O21 output to trigger D23, the output of trigger D23 becomes high level at next rising edge, after becoming low level with door A21 output, the output of its anti-phase back and trigger D23 mutually " with " after output to or door O21, therefore or door O21 to export be high level still, thereby make the output of trigger D23 also keep also high level.In this process, shadow clear signal clear-shadow is always high level.In clearing cell, locking signal mask is after trigger D21 postpones, with signal after N22 is anti-phase with door A25 mutually " with ", obtaining continuing duration is the positive pulse signal that a clock period, final position align with the locking signal negative edge, this signal again through trigger D22 postpone and with door N23 anti-phase after, obtaining postponing a clock period, continuing duration than above-mentioned positive pulse signal is the undersuing of a clock period, and this signal is the effective shadow clear signal of low level clear-shadow.This signal outputs to and a door A23, and when this signal was low level, trigger D23 became low level at next rising edge clock, as among the trigger D23 temporary have the shadow look-at-me then this shadow look-at-me will be eliminated.The shadow look-at-me of trigger D23 output with door A24 and locking signal mask with after output to secondary interruption status register circuit, therefore after the release be locking signal mask become invalid after, should this shadow look-at-me that outputs to secondary interruption status register circuit can be masked with door.
Secondary interruption status register circuit further comprises collecting unit, is used to receive secondary look-at-me or the shadow look-at-me and the output of secondary interrupt trap circuit and the output of secondary interruption shadow register circuit; The level holding unit is used for when the look-at-me of collecting unit output impulse form it is temporary, and keeps before being eliminated and exports this look-at-me; Clearing cell is used to receive the interrupt clear signal clear of CPU, and the look-at-me that the level holding unit is temporary is removed.
A kind of example of the physical circuit of secondary interruption status register circuit as shown in Figure 4, collecting unit by or door O31 and form with door A31, or door O31 receive secondary look-at-me and shadow look-at-me and export look-at-me to and door A31, when enable signal enable is effective, export with door A31 look-at-me.The level holding unit is by d type flip flop D31, with door A32, A33, not gate N32 and or door O32 form, its structure is identical with secondary interruption shadow register circuit with principle of work, just repeats no more.Clearing cell is made up of not gate N31, is used for the interrupt clear signal clear of positive pulse is converted to undersuing to remove the look-at-me of trigger D31.
Should be noted that those skilled in the art can understand, the variation of the concrete logical circuit of realization above-mentioned functions is very various, is that high level or low level are effectively also relevant with signal, and the present invention is not limited to any concrete circuit form.
In the present embodiment, priority is divided into two kinds of fixed priority and configurable priority.If more than one, interruptable controller number has distributed fixed priority for each secondary look-at-me according to the secondary look-at-me to each interrupt source to the secondary look-at-me of interruptable controller report.CPU searches and handles according to the order of this priority when searching the secondary look-at-me.Secondary look-at-me from same interrupt source has corresponding secondary interrupt status register in interruptable controller.Different position in the corresponding secondary interrupt status register of secondary look-at-me meeting of different priorities, and each is corresponding to a secondary interruption status register circuit, as shown in Figure 8.The quantity of secondary look-at-me is relevant with secondary interrupt status register width.Even the secondary interrupt status register is 32, then allows 32 secondary look-at-mes at most.In like manner, the quantity of one-level interrupt source signal is also relevant with the width of one-level interrupt register.
The one-level of present embodiment interrupts selecting that circuit can adopt that application number is 200610089193.8, denomination of invention is the structure of the Chinese patent application of " a kind of method and apparatus of searching highest priority interrupt from a plurality of effective interruptions ".This scheme can realize the flexible configuration of one-level look-at-me priority, and the quick selection of highest priority interrupt.But the present invention is not limited to this.The one-level look-at-me of the limit priority of selecting is input to the one-level interrupt register.
Because the interruptable controller of present embodiment is supported the interrupt vector function for the one-level look-at-me of the IRQ form of each CPU.After producing the one-level look-at-me, interruptable controller will deposit the pairing interrupt vector of this one-level look-at-me in the interrupt vector register (not shown) in by searching interrupt vector table.Interrupt vector table when system initialization by in the internal memory that CPU allocates in the interrupt vector table register of interruptable controller or interruptable controller can be visited.Interrupt vector be in the software at the software entry address of the service routine of this one-level look-at-me, when interrupting being received by CPU, CPU directly carries out the service routine of relevant position by the interrupt vector that reads in the interrupt vector register.And when adopting quick interruption form, CPU directly carries out next bar instruction and carries out Interrupt Process, and without redirect.
Because the interruption sub-controller of present embodiment supports IRQ to interrupt simultaneously and FIR interrupts, CPU makes FIQ enable signal or IRQ enable signal effective by the configuration register (not shown), can control sub-controller and export FIQ or IRQ look-at-me to CPU.Sometimes, the required interruption form of each CPU difference, it is effective to mainly contain high level, and low level is effective, several forms such as rising edge is effective, negative edge is effective, high impulse is effective and low pulse is effective.What the one-level look-at-me was posted device output is that high level effectively interrupts, need be when CPU sends the interruption of other form if interrupt sub-controller, need Fig. 3 with increase a format conversion circuit behind the door and carry out format conversion.Because when pulse was effective, CPU had the risk that does not obtain interruption.Therefore, the format conversion circuit of present embodiment also has the function that automatic repeating transmission pulse form is interrupted.In case and CPU has responded interrupt request, the automatic retransmission mechanism of this time interruption can be temporarily locked, can not cause the generation of multiple interrupt.
It still is quick interruption form as the regular interrupt form that the interrupt control method of present embodiment needs to dispose the current one-level look-at-me of using earlier, goes back configure interrupt vector table simultaneously when using the regular interrupt form;
The flow process of present embodiment method such as a mistake! Do not find Reference source.Shown in, may further comprise the steps:
After S100, interruptable controller receive the secondary look-at-me of one or more interrupt sources transmissions, described secondary look-at-me is temporary, and for sending one-level look-at-me of each interrupt source generation of secondary look-at-me;
The secondary look-at-me adopts impulse form, and interruptable controller detects the lasting duration of the secondary look-at-me of receiving from interrupt source, is reaching when setting duration just as effectively the secondary look-at-me is temporary.
S110, described interruptable controller select a highest one-level look-at-me of current priority again from described one-level look-at-me, CPU is kept in and reported to this one-level look-at-me of selecting;
When reporting CPU, interruptable controller sends the regular interrupt form or interrupts the one-level look-at-me of form fast to CPU according to configuration, and when adopting the regular interrupt form, CPU reads the entry address that described interrupt vector table obtains corresponding interrupt service routine.And the form of look-at-me can adopt high level effective, and low level is effective, and rising edge is effective, negative edge is effective, high impulse is effective or low pulse is effective.
After S120, CPU receive the one-level look-at-me, judge whether corresponding secondary look-at-me, if having, execution in step S130, otherwise, execution in step S140;
Because system has a test mode sometimes, can need judge whether that the secondary look-at-me produces this moment by directly configuration one-level interrupt register generation interruption, search as arriving in the corresponding secondary interrupt status register.
S130, CPU call the interrupt service routine response and interrupt, and with current all secondary look-at-mes locking, before release, the secondary look-at-me that interrupt source is sent is temporary interrupts shadow register to corresponding secondary;
When response was interrupted, CPU was according to priority handled to low order by height the interruption that produces one by one according to secondary look-at-me priority.
S140, CPU removes secondary look-at-me and one-level look-at-me, remove the locking of secondary look-at-me then, after having removed the secondary look-at-me, secondary can be interrupted shadow look-at-me temporary in the shadow register and send in the secondary interrupt status register temporary.
In addition, when CPU has a plurality ofly, described interruptable controller comprises a plurality of sub-controllers, and each sub-controller is corresponding with a CPU, sends the one-level look-at-me to this corresponding CPU, and can cry soft interruption mutually between a plurality of CPU.
On the basis of the foregoing description, the present invention can also have other mapping mode.For example in another embodiment of the present invention, can have only a processor, correspondingly the structure of interruptable controller is equivalent to a sub-controller in the foregoing description, does not have the situation of crying soft interruption mutually in addition, and other structure all is identical with disposal route.And for example, under the less demanding occasion to real-time, above-mentioned interrupt control method also can realize with software.
Claims (18)
1, a kind of central controlled interrupt control method may further comprise the steps:
(a) after interruptable controller is received the secondary look-at-me of one or more interrupt sources transmissions, described secondary look-at-me is temporary, and for sending one-level look-at-me of each interrupt source generation of described secondary look-at-me;
(b) described interruptable controller is selected an one-level look-at-me again from described one-level look-at-me, and the Interrupt Process device is kept in and reported to this one-level look-at-me of selecting;
(c) after described Interrupt Process device is received the one-level look-at-me that reports, call the interrupt service routine response and interrupt, remove secondary look-at-me and the one-level look-at-me that has responded afterwards.
2, interrupt control method as claimed in claim 1 is characterized in that:
It still is quick interruption form as the regular interrupt form that step (a) disposes the current one-level look-at-me of using earlier before, and interrupt vector table also is set when using the regular interrupt form simultaneously;
The described interruptable controller of step (b) sends the regular interrupt form or interrupts the one-level look-at-me of form fast to described Interrupt Process device according to described configuration, when adopting the regular interrupt form, interruptable controller also is provided with corresponding interrupt vector, and the Interrupt Process device reads the entry address that described interrupt vector is obtained corresponding interrupt service routine.
3, interrupt control method as claimed in claim 1 is characterized in that:
Described Interrupt Process device has a plurality of, and described interruptable controller comprises a plurality of sub-controllers, and each sub-controller is corresponding with an Interrupt Process device, sends the one-level look-at-me to this corresponding Interrupt Process device.
4, interrupt control method as claimed in claim 3 is characterized in that:
At least one Interrupt Process device in the described Interrupt Process device can send soft interrupt signal by the sub-controller to other Interrupt Process device correspondence, calls out soft interruption between a plurality of Interrupt Process devices.
5, interrupt control method as claimed in claim 1 is characterized in that:
The described interruptable controller of step (a) is temporarily stored in described secondary look-at-me in the secondary interrupt status register;
The described interruptable controller of step (b) is temporarily stored in described one-level look-at-me in the one-level interrupt register;
In the step (c), when described Interrupt Process device calls interrupt service routine response interruption, secondary look-at-me in current all secondary interrupt status registers is locked, after removing the secondary look-at-me, remove described locking again, allow described secondary interrupt status register to keep in new look-at-me.
6, interrupt control method as claimed in claim 5 is characterized in that:
In the step (c), as as described in before Interrupt Process device locking back and the release, interrupt source is sent new secondary look-at-me, then described interruptable controller interrupts this secondary look-at-me in the shadow register as the temporary secondary to correspondence of shadow look-at-me, after release, again that described shadow look-at-me is temporary in the secondary interrupt status register of correspondence.
7, interrupt control method as claimed in claim 1 is characterized in that:
The look-at-me that the described interruptable controller of step (b) sends to the Interrupt Process device adopts a kind of or a kind of according to configuration selection from following form in the following form: high level is effective, low level is effective, and rising edge is effective, negative edge is effective, high impulse is effective and low pulse is effective.
8, interrupt control method as claimed in claim 1 is characterized in that:
The described interruptable controller of step (b) is to select an one-level look-at-me that current priority is the highest from the one-level look-at-me of each interrupt source, the priority of the one-level look-at-me of each interrupt source is configured by register, and each secondary look-at-me and/or one-level look-at-me have a corresponding enable signal.
9, as the described interrupt control method of arbitrary claim in the claim 1 to 8, it is characterized in that:
The described secondary look-at-me of step (a) adopts impulse form, and described interruptable controller also detects the lasting duration of the secondary look-at-me of receiving from interrupt source, is reaching when setting duration just as effectively the secondary look-at-me is temporary.
10, a kind of central controlled interruptable controller is characterized in that, this interruptable controller comprises that one-level interrupt register, one-level are interrupted the selection circuit, some groups of secondary Interrupt Process circuit, some one-levels are interrupted generative circuit, wherein:
Described every group of secondary Interrupt Process circuit comprises one or more secondary Interrupt Process circuit, is used to receive one or more secondary look-at-mes of same interrupt source and keep in;
The output of described every group of secondary Interrupt Process circuit is connected to a described one-level and interrupts generative circuit, and the one-level look-at-me that described one-level interruption generative circuit is used to export corresponding to this group secondary look-at-me interrupts selecting circuit to described one-level;
Described one-level interruption selection circuit is used for selecting an one-level look-at-me from the one-level look-at-me of each interrupt source and also this one-level look-at-me is temporarily stored in the described one-level interrupt register;
Described one-level interrupt register is used for temporary one-level look-at-me and reports the Interrupt Process device.
11, interruptable controller as claimed in claim 10 is characterized in that:
Described secondary Interrupt Process circuit comprises secondary interrupt trap circuit and secondary interruption status register circuit, and a plurality of secondary interruption status register circuits of an interrupt source have been formed the secondary interrupt status register of this interrupt source, wherein:
Described secondary interrupt trap circuit is used to receive the locking signal of interrupting from the secondary look-at-me of the impulse form of interrupt source and secondary, reach at the lasting duration of secondary look-at-me and to set duration and locking signal when invalid, just to described secondary interruption status register circuit output secondary look-at-me;
Described secondary interruption status register circuit is used to receive the secondary look-at-me from secondary interrupt trap circuit, described secondary look-at-me is kept in and is outputed to corresponding one-level and interrupt generative circuit; And be received in effective interrupt clear signal between lockup period, when described clear signal is effective, remove temporary secondary look-at-me;
Described one-level is interrupted generative circuit and is used for each secondary look-at-me of input is carried out exporting after the inclusive-OR operation.
12, interruptable controller as claimed in claim 11 is characterized in that:
Described secondary Interrupt Process circuit comprises that also a secondary interrupts the shadow register circuit, and a plurality of secondarys of an interrupt source interrupt the secondary interruption shadow register that the shadow register circuit has been formed this interrupt source, wherein:
Described secondary interrupt trap circuit also is used for reaching at the lasting duration from the secondary look-at-me of interrupt source sets duration and described locking signal when effective, just interrupts shadow register circuit output secondary look-at-me to described secondary;
Described secondary interruption shadow register circuit is used to receive secondary look-at-me and the described locking signal from secondary interrupt trap circuit, when described locking signal is effective, as receive that the secondary look-at-me is then temporary as the shadow look-at-me, and after locking signal is invalid, remove temporary shadow look-at-me;
Described secondary interrupt status register also receives the shadow look-at-me of interrupting the shadow register circuit from described secondary, after removing the secondary look-at-me, as exists the shadow look-at-me then it to be kept in and outputs to corresponding one-level interruption generative circuit.
13, interruptable controller as claimed in claim 12 is characterized in that:
Described secondary interrupt trap circuit further comprises: capturing unit, be used to receive secondary look-at-me from the impulse form of interrupt source, and only output continues the secondary look-at-me that duration reaches the setting duration; Lock cell is used for when locking signal is effective, and the shielding capturing unit outputs to the secondary look-at-me of secondary interruption status register circuit, when locking signal is invalid, just allows capturing unit output secondary look-at-me to secondary interruption status register circuit;
Described secondary interruption status register circuit further comprises: collecting unit is used to receive the secondary look-at-me of secondary interrupt trap circuit output and shadow look-at-me and the output that secondary interrupts the output of shadow register circuit; The level holding unit is used for when the look-at-me of collecting unit output impulse form it is temporary, and keeps before being eliminated and exports this look-at-me; Clearing cell is used for the interrupt clear signal of received pulse form, and the look-at-me that the level holding unit is temporary is removed;
Described secondary interrupts the shadow register circuit and further comprises: lock cell, be used for when locking signal is effective, allow capturing unit output secondary look-at-me to the level holding unit, level holding unit output shadow look-at-me is to secondary interruption status register circuit; When locking signal is invalid, shield described capturing unit and output to the secondary look-at-me that secondary interrupts level holding unit in the shadow register circuit, and secondary interrupts the shadow look-at-me that level holding unit in the shadow register circuit outputs to secondary interruption status register circuit; The level holding unit, being used for when the secondary look-at-me of lock cell output impulse form it being kept in is the shadow look-at-me, and this shadow look-at-me of output arrives secondary interruption status register circuit before being eliminated; Clearing cell, be used for locking signal by effectively become invalid after, the clear signal of an impulse form of output is interrupted the temporary shadow look-at-me of level holding unit in the shadow register circuit with secondary and is removed.
14, as the described interruptable controller of arbitrary claim in the claim 10 to 13, it is characterized in that:
Described interruptable controller also comprises two and door, the output of described one-level interrupt register is connected to described two and door, one of them is input as quick interruption enable signal with another of door, and the look-at-me that should export quick interruption form with door is to described Interrupt Process device; Another is input as the regular interrupt enable signal with another of door, should with the look-at-me of door output regular interrupt form and interrupt vector to described Interrupt Process device.
15, as the described interruptable controller of arbitrary claim in the claim 10 to 13, it is characterized in that:
Described interruptable controller comprises a plurality of sub-controllers, each sub-controller includes the one-level interrupt register, one-level interrupts selecting circuit, some groups of secondary Interrupt Process circuit, some one-levels to interrupt generative circuit, is used for sending the one-level look-at-me to each self-corresponding Interrupt Process device.
16, interruptable controller as claimed in claim 14 is characterized in that:
Described two of being connected with one-level interruption selection circuit also comprise a format conversion circuit afterwards with door, be used for the format conversion of the one-level look-at-me of one-level interrupt register output is other form, described form be that high level is effective, low level is effective, rising edge is effective, negative edge is effective, high impulse is effective and low pulse effectively in a kind of.
17, as the described interruptable controller of arbitrary claim in the claim 10 to 13, it is characterized in that: described Interrupt Process device is CPU, and the part or all of look-at-me in the described interruptable controller all has corresponding enable signal.
18, as the described interruptable controller of arbitrary claim in the claim 10 to 13, it is characterized in that:
Described one-level interrupts selecting circuit to be used for selecting an one-level look-at-me that current priority is the highest from the one-level look-at-me of each interrupt source, and the priority of the one-level look-at-me of each interrupt source is configured by register.
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