CN101221953B

CN101221953B - Multiport and multi-channel embedded dynamic ram and operating method thereof

Info

Publication number: CN101221953B
Application number: CN2007101707819A
Authority: CN
Inventors: 林殷茵; 陈邦明; 张佶
Original assignee: Individual
Current assignee: Individual
Priority date: 2007-11-22
Filing date: 2007-11-22
Publication date: 2011-06-22
Anticipated expiration: 2027-11-22
Also published as: CN101221953A

Abstract

The invention belongs to the integrated circuit technical field, in particular to an embedded dynamic random access memory with multiple ports and multiple channels and a memory operating method thereof. The memory comprises a plurality of memory cells; n transistors which are arranged in each memory cell (n is a natural number and larger than or equal to 2); a word line bit line pair arranged in each transistor, wherein, the bit line of each transistor can be connected with an input/output port; different transistors in the memory cell are positioned in the same floating body which is electrically isolated from surrounding; word line bit line pairs of different transistors are independent form each other, and can be selected synchronously or time-sharing, then, corresponding different transistors selected at the same time or time-sharing can read memory and refresh memory operation synchronously or time-sharing through corresponding ports. The refreshing operation and the reading operation are independent mutually, thereby improving the speed of reading operation of the embedded type dynamic random access memory, and meeting different power consumption requirements through regulating frequency of the refreshing operation.

Description

The embedded DRAM of multiport, many raceway grooves and method of operation thereof

Technical field

The invention belongs to microelectronics technology, be specifically related to a kind of multiport, many raceway grooves embedded DRAM and methods of storage operating thereof.

Background technology

Dynamic random access memory (DRAM) is to be used for the memory device of stored information.DRAM is had a preference in some applications, is because they can be quite at an easy rate with very high density manufacturing.Embedded DRAM (e DRAM) and other logical circuits are integrated in the chip jointly, can save a large amount of buffers and I/O pressure point, thereby higher speed can be arranged, littler area and lower power consumption.Owing between DRAM nuclear and the logical circuit built-in wide bit data bus is arranged, this a large amount of parallel processing capabilities make embedded DRAM can satisfy the requirement of the T byte/s data throughput in lucky position epoch.For standard DRAM, the data of reading from the unit will be passed through column selection, inner I/O line, main amplifier, output buffer arrival pressure point, arrive pcb board by package pins again, and the load capacitance that drive makes speed receive influence more than 50pf.To embedded DRAM, data are by the I/O pressure point in the chip, and the electric capacity that drive has only about 1pf, and speed is greatly improved, and can save a large amount of power consumptions.The structure of the embedded DRAM of report mainly contains at present: traditional 1T1C DRAM structure, single tube buoyancy aid (floating body) 1T/FB structure based on SOI, the single tube buoyancy aid of based single crystal silicon body (floating body) 1T/FB structure is based on the storage organization at random (T-RAM) of thyristor.

The memory cell of traditional dynamic random access memory typically comprises two elements, and just holding capacitor and access transistor constitute the structure of 1T1C.Fig. 1 is a traditional dynamic random access memory array structure, and wherein 100 to 108 is access transistors, and 109 to 111 is bit lines, and 112 to 114 is word lines, and 115 to 117 is the parasitic capacitances on the bit line, and 118 to 126 is holding capacitors.The memory cell that constitutes with operation access transistor 100 and holding capacitor 118 is the course of work of the traditional dynamic random access memory of example explanation below.In the write operation stage, data value is placed on the

bit line

109, and 112 of word lines are raised, according to the difference of data value, holding capacitor 118 or charging, perhaps discharge, particularly, writing data is 1 o'clock, holding capacitor 118 chargings, writing data is 0 o'clock, holding capacitor 118 discharges.In the read operation stage, bit line 109 when making word line 112 effectively, has been freeed redistributing of electric charge at first by precharge between bit line capacitance 115 and holding capacitor 118, at this moment the voltage on the bit line changes, and the direction of this variation has determined to be stored the value of data.1T1C structure dynamic random access memory is destructive, and the amount of charge that leaves in other words in the unit is modified during read operation, therefore finishes a read operation and must return to its original value more afterwards.So finishing read operation and then is exactly refresh operation afterwards.Carry out just carrying out after the refresh operation next step read-write operation.This 1T1C structure dynamic random access memory relies on holding capacitor storage data, so storage capacitance must be enough greatly to guarantee the reliability of storage, but the existence of big electric capacity is area occupied not only, and under the development trend that characteristic size is more and more littler in semiconductor technology, it is very difficult making big electric capacity, the obstacle that this has brought physics or technology to realize.

Fig. 2 is based on the single tube buoyancy aid 1T/FB profile of SOI, and it has removed the holding capacitor of conventional dynamic random asccess memory, uses buoyancy aid (floating body) stored charge.DRAM unit 200 comprises silicon substrate 201, buried oxidation layer 202, zoneofoxidation 203-204, N++ type source-drain area 205-206, N+ type source-drain area 207-208, P type floater area 209, gate oxidation 210, gate electrode 211, sidewall region 212-213.Buoyancy aid 209 is by gate oxidation 210, buried oxidation layer 202 and source drain depletion region 207-208 and substrate isolation.Partly exhaust buoyancy aid 209 and be used for stored charge, the threshold voltage V of modulation DRAM memory cell _TSource region 205 general ground connection.As Fig. 3 (a) when needs when DRAM memory cell 200 writes data 1, for drain region 206 applies high voltage, grid 211 connects moderate range voltage, make like this and have higher electric field in the drain region 206, channel electrons obtains enough energy at the drain terminal high field region, electronics---the hole is right by the ionization by collision generation, move to the buoyancy aid 713 than low potential in the hole, because the source---the body surplus is in a potential barrier, the hole will be deposited in buoyancy aid 209, has raised the electromotive force of buoyancy aid 209, because the inclined to one side effect of lining, when underlayer voltage raises (for P type substrate), can make threshold voltage reduce, so just be equivalent to finish and write 1 operation.As Fig. 3 (b) when needs when DRAM memory cell 200 writes data 0, for drain region 206 applies negative voltage, grid 211 connects moderate range voltage, because buoyancy aid 209 has the hole, makes substrate potential for just, so just caused the positively biased of substrate-drain region PN junction, under the effect of positive bias-voltage, be stored in hole in the buoyancy aid 209 and can break away from and wherein be injected into drain region 206, make the level of underlayer voltage before recovering, from and improved threshold voltage, so just be equivalent to write 0.Be that drain region 206 and grid 211 all apply moderate range voltage during read operation, source region 205 ground connection.Like this, when the data of DRAM cell stores were 1, source-drain area can flow through big relatively electric current, and when the data of DRAM cell stores were 0, source-drain area can flow through relatively little electric current.The data that electric current by relatively flowing through source-drain area and reference current are determined the DRAM cell stores.Leakage current and misoperation when not selected DRAM memory cell grid connects negative voltage with the reduction read-write in the array.This single tube buoyancy aid 1T/FB structure need be used SOI technology, makes production cost very high.In addition, though the floater effect in the SOI technology can realize that can increase the complexity of circuit and logical design, and in SOI technology, the leakage current characteristic of device is difficult to control.

Fig. 4 is based on the single tube buoyancy aid 1T/FB profile of monocrystalline silicon body.DRAM unit 400 comprises P-type silicon substrate 401, N-type buried layer 402, depletion region 403-404, shallow trench isolation region 405, heavy doping N++ type source region 406 and drain region 407, light dope N+ type source region 408 and drain region 409, p type floater area 410, gate oxide 411, gate electrode 415, sidewall region 421-422.N++ type source region and N+ type source region together form N type source region 411, and same N++ type drain region and N+ type drain region together form N type drain region 412..N-type buried region 402 is formed under the transistor as the back grid.Under suitable biasing, depletion region 404 is kept apart the floater area 410 of 1T/FBDRAM memory cell fully with substrate and other n type injection zones.Source region 411 general ground connection.As Fig. 5 (a) when needs when DRAM memory cell 400 writes data 1, for drain region 412 applies high voltage, grid 415 connects moderate range voltage, make like this and have higher electric field in the drain region 412, channel electrons obtains enough energy at the drain terminal high field region, electronics---the hole is right by the ionization by collision generation, move to the buoyancy aid 410 than low potential in the hole, because the source---the body surplus is in a potential barrier, the hole will be deposited in buoyancy aid 410, has raised the electromotive force of buoyancy aid 410, because the inclined to one side effect of lining, when underlayer voltage raises (for P type substrate), can make threshold voltage reduce, so just be equivalent to finish and write 1 operation.As Fig. 5 (b) when needs when DRAM memory cell 400 writes data 0, for drain region 412 applies negative voltage, grid 415 connects moderate range voltage, because buoyancy aid 410 has the hole, makes substrate potential for just, so just caused the positively biased of substrate-drain region PN junction, under the effect of positive bias-voltage, be stored in hole in the buoyancy aid 410 and can break away from and wherein be injected into drain region 412, make the level of underlayer voltage before recovering, from and improved threshold voltage, so just be equivalent to write 0.Be that drain region 412 and grid 415 all apply moderate range voltage during read operation, source region 411 ground connection.Like this, when the data of DRAM cell stores were 1, source-drain area can flow through big relatively electric current, and when the data of DRAM cell stores were 0, source-drain area can flow through relatively little electric current.The data that electric current by relatively flowing through source-drain area and reference current are determined the DRAM cell stores.Leakage current and misoperation when not selected DRAM memory cell grid connects negative voltage with the reduction read-write in the array.The single tube buoyancy aid 1T/FB structure of based single crystal silicon body has solved the problem based on the single tube buoyancy aid 1T/FB infrastructure cost costliness of SOI, but it is the same with single tube buoyancy aid 1T/FB structure based on SOI, all can only there be a bit lines and a word line to link drain region and grid respectively, when refreshing the DRAM unit, can not carry out read operation like this, that is to say, the DRAM unit refresh the reading speed that has limited the DRAM unit.

Fig. 6 (a) is based on the storage organization at random (T-RAM) of thyristor and SOI.Fig. 6 (b) is its equivalent circuit diagram.Comprise PNP pipe 614 and NPN pipe 615 as Fig. 6 (b) based on the storage organization at random 600 of thyristor, gating mos pipe 616, p+ injection region 603 in the emitter corresponding diagram 6 (a) of PNP pipe 614, n injection region 604 in the base stage corresponding diagram 6 (a) of PNP pipe 614, p injection region 605 in the collector electrode corresponding diagram 6 (a) of PNP pipe 614, n+ injection region 606 in the emitter corresponding diagram 6 (a) of NPN pipe 615, n+ injection region 607 in the source electrode corresponding diagram 6 (a) of MOS gate tube 616, p injection region 608 in the grid corresponding diagram 6 (a) of MOS gate tube 616, n+ injection region 609 in the drain electrode corresponding diagram 6 (a) of MOS gate tube 616, the collector electrode of PNP pipe 614 links to each other with the base stage of NPN pipe 615, the base stage of PNP pipe 614 links to each other with the collector electrode of NPN pipe 615, makes these two triodes form positive feedback.The emitter of NPN pipe 615 links to each other with MOS gate tube 616 source electrodes, and word line WL1 links to each other with MOS gate tube 616 grids, and word line WL2 links to each other by the base stage of coupling capacitance 613 with NPN pipe 615, and bit line BL links to each other with 616 drain electrodes of MOS gate tube.When needs write 1 for memory cell, at first make WL1 be in high level, bit line BL is in low level, then when the last voltage of WL2 is begun to rise by low level, make NPN manage 615 positively biased conductings by coupling capacitance 613, because NPN pipe 615 and PNP pipe 614 are formed the positive feedback network, cause the 614 also conductings of PNP pipe, so just finished and write 1 operation.When needs write 0 for memory cell, at first make WL1 be in high level, bit line BL is in high level, when powering on, WL2 presses off the beginning when beginning to descend then by high level, extract electric charge rapidly by coupling capacitance 613, make PNP pipe 614 and NPN pipe 615 close, so just finished and write 0 operation.During read operation, WL1 is that high level is opened MOS gate tube 616, and WL2 is always low level, obtains the data of memory cell by the size of judging the last electric current of BL.In random asccess memory work based on thyristor, for keeping data, memory cell need periodically activate WL and carry out refresh operation, but the same with other dynamic memory, and it can not carry out read operation and refresh operation independently of one another by two ports.This device is based on the SOI substrate simultaneously, also has the problem of cost height, complex circuit designs.

Summary of the invention

The objective of the invention is to propose a kind of multiport, many raceway grooves embedded DRAM and methods of storage operating thereof, make refresh operation and read operation separate, can be undertaken by different port while or timesharing, improving the speed of embedded DRAM read operation, and satisfy different power consumption demand by the frequency of adjusting refresh operation.

The multiport that the present invention proposes, the embedded DRAM of many raceway grooves comprise several memory cell; Each memory cell has n transistor, and (n is a natural number, n 〉=2, common n≤10), each transistor comprises source region, drain region, grid and the tagma between source region and drain region, source region between adjacent transistor and drain region interconnect or share, during each transistor turns, form conducting channel between this transistorized source and leakage;

Above-mentioned transistor can all be a MOS (metal-oxide-semiconductor) memory; Also can comprise and two kinds of transistors below are at least respectively arranged: a kind of is MOS (metal-oxide-semiconductor) memory, and a kind of is the floating gate type MOS (metal-oxide-semiconductor) memory with non-volatile memory function;

Each transistor in the memory cell has 1 pair of word line bit line right, i.e. 1 word line and 1 word line; Each transistorized bit line can link to each other with an input/output end port;

Different crystal pipe in the memory cell is arranged in same buoyancy aid, buoyancy aid and electricity isolation on every side; Described float structure can be the float structure that is formed in the monocrystalline substrate, also can be the float structure that is formed in SOI (the silicon on insulator) substrate.

The float structure that is formed in the monocrystalline substrate is as follows: form the buried layer with second conduction type below the semiconductor surface with first conduction type, the buried layer upper surface is positioned at following first degree of depth of semiconductor surface, the zone that has first conduction type above buried layer forms memory cell, isolated by shallow trench isolation region between the memory cell, the degree of depth of shallow trench isolation region is deeper than following first degree of depth of semiconductor surface; Comprise in each memory cell that (n is a natural number to n transistor, n 〉=2, common n≤10), each transistor comprises source region, drain region and the tagma between source region and drain region with second conduction type, between buried layer and tagma, between source region and tagma, form depletion region between drain region and tagma, depletion region and shallow trench isolation region surround and form the float structure of isolating with electricity all around;

The float structure that is formed in the SOI substrate is as follows: be positioned on the insulating barrier, have in the monocrystalline silicon thin film of first conduction type and form memory cell, comprise in each memory cell that (n is a natural number to n transistor, n 〉=2, common n≤10) transistor, each transistor comprises the source region with second conduction type, the drain region and be positioned at the source region and the drain region between the tagma, the transistorized source region and the drain region degree of depth that are positioned at the memory cell edge connect monocrystalline silicon thin film, other is not positioned at the transistorized source region at memory cell edge and the drain region degree of depth less than the monocrystalline silicon thin film degree of depth, insulating barrier, connect the source region of monocrystalline silicon thin film, the drain region surrounds formation and electric float structure of isolating all around with the depletion region that the tagma forms respectively;

In described buoyancy aid, inject charge carrier or extract charge carrier by at least one port, regulate transistorized threshold voltage, reach the purpose of write signal; Read or read the electric current of source transistor between leaking simultaneously by a plurality of ports by a port, by differentiating the size of electric current, reach the purpose of read output signal, big electric current is represented first data mode 1, and little electric current is represented the 2nd data mode 0; Regularly original signal in the memory cell is write back by at least one port, reached the purpose of refresh signal.

The word line bit line of different crystal pipe is to independently of one another, can be simultaneously or timesharing selected, and then simultaneously or timesharing choose corresponding different crystal pipe, can be simultaneously or the timesharing storage operation that reads and refresh by corresponding ports.

Two transistors are arranged in described dynamic random access memory, and promptly n can equal at 2 o'clock, and each unit comprises two MOS (metal-oxide-semiconductor) memory: the first transistor and transistor seconds; The source of the leakage of the first transistor or source and transistor seconds or leak links to each other or is shared, and links to each other with ground; The word line of the first transistor and transistor seconds connects the grid to the first transistor and transistor seconds respectively; The bit line of the first transistor and transistor seconds connects respectively to the leakage or the source of the source of the first transistor or leakage and transistor seconds, and is connected with the input/output end port of the first transistor and transistor seconds respectively.When described two transistors were two n channel metal-oxide field-effect transistors, methods of storage operating comprised:

Write 1: the bit line to the first transistor applies first voltage, and word line applies second voltage, and the value of first voltage is bigger than second voltage, causes hot carrier and injects, and makes the hole inject buoyancy aid, reduces transistorized threshold voltage; Perhaps for the bit line of the first transistor applies tertiary voltage, word line applies the 4th voltage, and the 4th voltage is negative voltage, causes grid and causes potential barrier reduction (GIDL), makes the hole inject buoyancy aid, reduces transistorized threshold voltage.

Write 0: for the bit line of the first transistor applies the 5th voltage, the 5th voltage is negative voltage, and word line applies the 6th voltage, causes the positively biased of buoyancy aid-drain region PN junction, extracts the hole in the buoyancy aid, improves transistorized threshold voltage.

Refresh: according to the original data of memory cell is that the word line of the first transistor and bit line apply and write 0 or write 1 required voltage, reaches the purpose of refresh of memory cells legacy data

Read: for the bit line and the word line of transistor seconds applies the 7th voltage and the 8th voltage respectively, read the electric current of transistor seconds by the port of transistor seconds, electric current that 1 and 0 state is corresponding big respectively and little electric current, thus tell different store statuss.

The word line bit line of choosing transistor seconds carries out read operation and the word line bit line of choosing the first transistor to memory cell, and that memory cell is carried out refresh operation is separate, when reading, can refresh, also can when not reading, refresh, the frequency that refreshes can be at a high speed, middling speed, at a slow speed.

Three transistors are arranged in the memory cell of described dynamic random access memory, and promptly n equals at 3 o'clock, can comprise 3 metal-oxide-semiconductor field effect t transistors in the described unit: the first transistor, transistor seconds and the 3rd transistor; The first transistor, transistor seconds and the 3rd transistorized grid are connected with the 3rd transistorized word line with the word line of the first transistor, the word line of transistor seconds respectively; The leakage of the first transistor or source and the 3rd transistorized source or leakage is connected or share, and be connected with ground; The source of transistor seconds or leak with the 3rd transistorized leakage or the source links to each other or shared; The leakage of the source of the first transistor or leakage, transistor seconds or source are connected with the 3rd transistorized bit line with the bit line of the first transistor, the bit line of transistor seconds respectively with the 3rd transistorized leakage or source, and are connected with the first transistor, transistor seconds, the 3rd transistorized input/output end port respectively.When described transistor was 3 n channel metal-oxide field effect transistor transistors, its methods of storage operating comprised:

Write 1: be that the 3rd transistorized bit line applies the 9th voltage, word line applies the 10th voltage, and the value of the 9th voltage is greater than the 10th voltage, electronics---the hole is right to utilize the ionization by collision generation, cause hot carrier and inject, make the hole inject floater area, reduce transistorized threshold voltage; Perhaps be the 3rd transistorized bit line ground connection, word line applies the 11st voltage, and the 11st voltage is negative voltage, causes grid and causes potential barrier reduction (GIDL), makes the hole inject floater area, reduces transistorized threshold voltage.

Write 0: be that the 3rd transistorized bit line applies the 12nd voltage, the 12nd voltage is negative sense, and word line applies forward the 13rd voltage, causes the positively biased of buoyancy aid-drain region PN junction, extracts the hole in the buoyancy aid, improves transistorized threshold voltage.

Refresh: according to the original data of memory cell, regularly be that the 3rd transistorized word line and bit line apply and write 0 or write 1 required voltage, reach the purpose of refresh of memory cells legacy data,

Read: can apply the 14th and the 15th voltage respectively for the bit line and the word line of the first transistor, port by the first transistor reads the size of current of the first transistor source between leaking, 1 or 0 state is the big and little electric current of correspondence respectively, thereby tells the data in the memory cell; Also can apply the 16th voltage and the 17th voltage respectively for the bit line and the word line of transistor seconds, the 16th voltage and the 17th voltage are higher than the transistor seconds source voltage terminal, port by transistor seconds reads the size of current of transistor seconds source between leaking, 1 or 0 state is the big and little electric current of correspondence respectively, thereby tells the data in the memory cell; Can also be simultaneously, the bit line of the first transistor and transistor seconds and word line read required voltage for applying, electric current between leak in the source of reading the first transistor and transistor seconds by the first transistor port and transistor seconds port simultaneously obtains the storage data from the first transistor port and transistor seconds port simultaneously.

Choosing the 3rd transistorized word line bit line that memory cell is carried out refresh operation and the word line bit line of choosing the first transistor and/or transistor seconds, that memory cell is carried out read operation is separate, and the frequency that refreshes can be at a high speed, middling speed, at a slow speed.

In the memory cell of described memory, n can equal 2, and the 1st transistor is MOS (metal-oxide-semiconductor) memory, and the 2nd transistor is the floating gate type MOS (metal-oxide-semiconductor) memory; The 1st transistor links to each other with the 2nd transistorized word line with the 1st transistor respectively with the 2nd transistorized grid; The 1st transistorized leakage or source link to each other with the 2nd transistorized source or leakage or share, and are connected with ground; The 1st transistorized source or leakage, the 2nd transistorized leakage or source are connected with the bit line of the 1st transistorized bit line, transistor seconds respectively, and are connected with the 2nd transistorized port with the 1st transistor respectively.When the 1st transistor and the 2nd transistor were the n channel transistor, the methods of storage operating of described memory comprised:

Write 1: be that the 2nd transistorized bit line applies the 18th voltage, word line applies the 19th voltage, and the value of the 18th voltage is greater than the 19th voltage, electronics---the hole is right to utilize the ionization by collision generation, cause hot carrier and inject, make the hole inject floater area, reduce transistorized threshold voltage; Perhaps be that the 2nd transistorized bit line applies the 20th voltage, word line applies the 21st voltage, and the 21st voltage is negative voltage, causes grid and causes potential barrier reduction (GIDL), makes the hole inject floater area, reduces transistorized threshold voltage.

Write 0: be that the 2nd transistorized bit line applies the 22nd voltage, the 22nd voltage is negative voltage, and word line applies the 23rd voltage, causes the positively biased of buoyancy aid-drain region PN junction, extracts the hole in the buoyancy aid, improves transistorized threshold voltage.

Refresh: according to the original data of memory cell is that the 2nd transistorized word line and bit line apply and write 0 or write 1 required voltage, reaches the purpose of refresh of memory cells legacy data,

Read: for the bit line and the word line of the first transistor applies the 24th voltage and the 25th voltage respectively, by reading the data in the size of current reading cells between the leakage of the first transistor source, electric current that 1 and 0 state is corresponding big respectively and little electric current, thus tell different store statuss.。

Deposit the 2nd transistor in by the first transistor reading of data before the power down, be temporary in the buffer legacy data is read in the back that powers on from the 2nd transistor after,, again data in the buffer are write back memory cell data erase in the 2nd transistor.

Choose the 1st transistorized word line bit line to carrying out read operation and choose the 2nd transistorized word line bit line separate to carrying out refresh operation, the frequency that refreshes can be at a high speed, middling speed, at a slow speed.

Description of drawings

Fig. 1 is a traditional dynamic random access memory array structure.

Fig. 2 is based on the single tube buoyancy aid 1T/FB vertical structure of SOI.

Fig. 3 (a) is to the schematic diagram based on the single tube buoyancy aid 1T/FB structure operation of SOI (b).

Fig. 4 is based on the single tube buoyancy aid 1T/FB vertical structure of monocrystalline silicon body.

Fig. 5 (a) is a schematic diagram to the single tube buoyancy aid 1T/FB structure operation of based single crystal silicon body (b).

Fig. 6 (a) (b) is based on the storage organization at random and the equivalent circuit diagram of thyristor respectively.

Fig. 7 (a) is respectively that the present invention proposes the memory cell vertical structure of a kind of dual-port, double channel embedded DRAM and the embodiment that is made of embedded DRAM several memory cell (b).Fig. 7 (c) is based on the dynamic random access memory embodiment of SOI substrate.

Fig. 8 (a) is respectively that the present invention proposes the memory cell vertical structure of a kind of three ports, triple channel embedded DRAM and the embodiment that is made of embedded DRAM several memory cell (b).

Fig. 9 (a) is respectively that the present invention proposes the memory cell vertical structure of another kind of dual-port, double channel embedded DRAM and the embodiment that is made of embedded DRAM several memory cell (b).

Number in the figure

100 to 108 is access transistors, 109 to 111 is bit lines, 112 to 114 is word lines, 115 to 117 is the parasitic capacitances on the bit line, 118 to 126 is holding capacitors, 200 is the DRAM unit, 201 is silicon substrate, 202 is buried oxidation layer, 203-204 is a zoneofoxidation, 205-206 is a N++ type source-drain area, 207-208 is a N+ type source-drain area, 209 is P type floater area, 210 is gate oxidation, and 211 is gate electrode, and 212-213 is a sidewall region, 400 is the DRAM unit, 401 is P-type silicon substrate, and 402 is N-type buried layer, and 403-404 is a depletion region, 405 is shallow trench isolation region, 406,407 are heavy doping N++ type source region and drain region, 408,409 is light dope N+ type source region and drain region, and 410 is p type floater area, 411 is gate oxide, 415 is gate electrode, and 421-422 is a sidewall region, and 600 is the storage organization at random based on thyristor, 601 to 602 is grid, 603 is the p+ injection region, and 604 is the n injection region, and 605 is the p injection region, 606 is the n+ injection region, 607 is the n+ injection region, and 608 is the p injection region, and 609 is the n+ injection region, 611 to 612 is word line, 613 is coupling capacitance, and 614 are the PNP pipe, and 615 are the NPN pipe, 616 are gating mos pipe, 701 is P-type silicon substrate, and 702 is N-type buried layer, and 703-704 is a depletion region, 705 is shallow trench isolation region, 706 and 707 are respectively the source region that heavy doping N++ type the first transistor and transistor seconds share and the drain region of the first transistor, and 708 and 709 are respectively the source region and the drain region of light dope N+ type the first transistor, and 710 are the drain region of heavy doping N++ type transistor seconds, 711 and 712 are respectively the source region and the drain region of light dope N+ type transistor seconds, 713 is p type floater area, and 714 is the gate electrode of the first transistor, and 715 is the gate electrode of transistor seconds, 716-717 is the sidewall region of the first transistor, 718-719 is the sidewall region of transistor seconds, the gate oxide of 720-721 the first transistor and transistor seconds, and 722 is buried oxidation layer, 801 is P-type silicon substrate, 802 is N-type buried layer, and 803-804 is a depletion region, and 805 is shallow trench isolation region, 806 and 807 are respectively the source region of heavy doping N++ type the first transistor and the 3rd transistors share and the drain region of the first transistor, 808 and 809 are respectively the source region and the drain region of light dope N+ type the first transistor, and 810 and 811 are respectively the zone of the source region of heavy doping N++ type transistor seconds and the 3rd transistorized drain region sharing and the drain region of transistor seconds, and 812 and 813 are respectively the source region and the drain region of light dope N+ type transistor seconds, 814 and 815 are respectively light dope N+ type the 3rd transistorized source region and drain region, 816 is p type floater area, and 817 is the gate electrode of the first transistor, and 818 is the gate electrode of transistor seconds, 819 is the 3rd transistorized gate electrode, 820-821 is the sidewall region of the first transistor, and 822-823 is the sidewall region of transistor seconds, and 824-825 is the 3rd transistorized sidewall region, 826-828 is a first transistor, transistor seconds and the 3rd transistorized gate oxide, 901 is P-type silicon substrate, and 902 is N-type buried layer, and 903-904 is a depletion region, 905 is shallow trench isolation region, 906 and 907 are heavy doping N++ type the first transistor and the source region of floating boom transistors share and the drain region of the first transistor, and 908 and 909 is the source region and the drain region of light dope N+ type the first transistor, and 910 are the transistorized drain region of heavy doping N++ type floating boom, 911 and 912 is transistorized source region of light dope N+ type floating boom and drain region, 913 is p type floater area, and 914 is the gate electrode of the first transistor, and 915 is the transistorized gate electrode of floating boom, 916-917 is the sidewall region of the first transistor, 918-919 is the transistorized sidewall region of floating boom, and 920-922 is the first transistor and the transistorized gate oxide of floating boom, and 923 is the transistorized floating boom of floating boom, 925 is buffer, and 926 is voltage selector.

Embodiment

Describe the present invention in the reference example more completely in conjunction with being shown in hereinafter, the invention provides preferred embodiment, but should not be considered to only limit to embodiment set forth herein.On the contrary, provide these embodiment, scope of the present invention is passed to those skilled in the relevant art fully so that this openly is completely and completely.

At this reference diagram is the schematic diagram of idealized embodiment of the present invention, and embodiment shown in the present should not be considered to only limit to the given shape in the zone shown in the figure.

The present invention relates to a kind of multiport, many raceway grooves embedded DRAM and method of operation thereof.Its characteristics are a plurality of transistors share buoyancy aids in the memory cell, refresh operation and read operation are separate, can be undertaken by different port while or timesharing, can improve the speed of embedded DRAM read operation and satisfy different power consumption demand by the frequency of adjusting refresh operation.

Accompanying drawing (1～6) is explained in the invention technical background.

Below semiconductor surface, form buried layer with second conduction type with first conduction type, the buried layer upper surface is positioned at following first degree of depth of semiconductor surface, the zone that has first conduction type above buried layer forms memory cell, isolated by shallow trench isolation region between the memory cell, the degree of depth of shallow trench isolation region is deeper than following first degree of depth of semiconductor surface; (n is a natural number to comprise n in each memory cell, n 〉=2) transistor, each transistor comprises source region, drain region and the tagma between source region and drain region with second conduction type, between buried layer and tagma, between source region and tagma, form depletion region between drain region and tagma, depletion region and shallow trench isolation region surround and form the float structure of isolating with electricity all around;

Fig. 7 (a) is the memory cell profile of the present invention embodiment of proposing a kind of embedded DRAM, the situation that two n channel metal-oxide field-effect transistors are arranged in memory cell 700, two raceway grooves, two ports are arranged, be specially: P-type silicon substrate 701, N-type buried layer 702,702 upper surfaces are first degree of depth below P type substrate 701 surfaces, form depletion region 703-704 between 701 and 702, shallow trench isolation region 705, the degree of depth of shallow trench isolation region 705 is deeper than following first degree of depth of semiconductor surface, promptly gos deep into 702 upper surfaces below.706 and 707 are respectively the source region and the drain region of the first transistor heavy doping N++ type, 708 and 709 are respectively the source region and the drain region of the first transistor light dope N+ type, 710 is the drain region of transistor seconds heavy doping N++ type, the source region of transistor seconds heavy doping N++ type and the first transistor N++ share in heavily doped source region 706,711 and 712 are respectively the source region and the drain region of transistor seconds light dope N+ type, 708 and 709 are respectively the source region and the drain region of the first transistor light dope N+ type, the gate electrode 714 of the first transistor, the gate electrode 715 of transistor seconds, the sidewall region 716-717 of the first transistor, the sidewall region 718-719 of transistor seconds, the gate oxide 720-721 of the first transistor and transistor seconds, the first transistor, form depletion region 704 between the source region of the N type of transistor seconds and drain region and P type substrate, STI 705, depletion region 703, depletion region 704 surrounds the floater area 713 with electricity isolation on every side.The source region 706 general ground connection that the first transistor and transistor seconds are shared.The first transistor and transistor seconds respectively have a pair of word line bit line right, wherein the first transistor bit line BL1 is connected to the drain region 707 of the first transistor, and link to each other with first port, transistor seconds bit line BL2 is connected to the drain region 709 of transistor seconds, and link to each other with second port, article one, word line WL1 is connected to the gate electrode 714 of the first transistor, and second word line WL2 is connected to the gate electrode 715 of transistor seconds.

When needs when memory cell writes data 1, bit line BL1 by the first transistor applies the 1st voltage to the drain region 707 of the first transistor, first voltage is high level, amplitude range can lie prostrate at 1.0-1.4, typically such as 1.2V, apply second voltage by the first transistor word line WL1 to the grid 714 of the first transistor, second voltage is moderate range, can lie prostrate at 0.4-0.8, representative value is such as 0.6V, source region 706 ground connection of the first transistor make like this to have higher electric field in the drain region 707 that channel electrons obtains enough energy at the drain terminal high field region, electronics---the hole is right by the ionization by collision generation, move to the buoyancy aid 713 than low potential in the hole, because the source---the body surplus is in a potential barrier, and the hole will be deposited in buoyancy aid 713, raised the electromotive force of buoyancy aid 713, because the inclined to one side effect of lining can make threshold voltage reduce when underlayer voltage raises (for P type substrate), so just be equivalent to finish and write 1 operation.

Can also write data 1 to memory cell by the following method, apply tertiary voltage by the first transistor bit line BL1 to the drain region 707 of the first transistor, the 3rd voltage is high level, amplitude range can lie prostrate at 1.0-1.4, typically such as 1.2V, apply the 4th voltage by the first transistor word line WL1 to the grid 714 of the first transistor, the 4th voltage is negative sense, such as-0.6V, source region 706 ground connection of the first transistor, cause grid and cause potential barrier reduction (GIDL), this moment, added drain terminal voltage can produce higher electric field in the grid leak overlapping region, thereby produce a dark depleted region, thereby and this high electric field can make the electronics generation tunnelling phenomenon in the drain region 707 produce electron hole pair, the hole flows to buoyancy aid 713 under effect of electric field, raised the electromotive force of buoyancy aid 713, because the inclined to one side effect of lining can make threshold voltage reduce when underlayer voltage raises (for P type substrate), so just be equivalent to finish and write 1 operation.

When needs when memory cell writes data 0, apply the 5th voltage by the first transistor bit line BL1 to the drain region 707 of the first transistor, the 5th voltage is negative sense, such as-1.2V, apply the 6th voltage by the first transistor word line WL1 to the grid 714 of the first transistor, the 6th voltage is moderate range, can lie prostrate at 0.4-0.8, representative value is such as 0.6V, source region 706 ground connection of the first transistor because buoyancy aid 713 has the hole, make substrate potential for just, so just caused the positively biased of substrate-drain region PN junction, under the effect of positive bias-voltage, be stored in hole in the buoyancy aid 713 and can break away from and wherein be injected into drain region 707, make the level of underlayer voltage before recovering, from and improved threshold voltage, so just be equivalent to write 0.

During data in needing read memory cell, apply the 7th voltage by transistor seconds bit line BL2 to the drain region 709 of transistor seconds, the 7th voltage is moderate range, can lie prostrate at 0.4-0.8, representative value is such as 0.6V, apply the 8th voltage by transistor seconds word line WL2 to the grid 715 of transistor seconds, the 8th voltage is moderate range, can lie prostrate at 0.4-0.8, representative value is such as 0.6V, source region 706 ground connection of transistor seconds, like this, when the data of cell stores are 1, because threshold voltage is less, source-drain area can flow through big relatively electric current, when the data of DRAM cell stores are 0, because threshold voltage is bigger, source-drain area can flow through relatively little electric current.The data that electric current by relatively flowing through source-drain area and reference current can be determined cell stores.Use the first transistor to carry out write operation in the present embodiment, use transistor seconds to carry out read operation, in fact can adopt the first transistor to carry out read operation yet, use transistor seconds to carry out write operation, this is not a limitation of the present invention.

The embedded DRAM of present embodiment is the same with other dynamic memory to need the regular data that memory cell is original to write back memory cell again, remedies the loss of the float hollow cave electric charge of memory cell, i.e. refresh operation.As Fig. 7 (a), because what the present invention proposed is double channel, the dual-port embedded DRAM, can carry out read operation and refresh operation independently by two ports, be that the operation of transistor seconds reading cells data and the first transistor carry out refresh operation and do not disturb mutually, this makes refresh operation and read operation to carry out independently of one another, can be simultaneously or timesharing carry out, particularly, apply the 7th voltage by transistor seconds bit line BL2 to the drain region 709 of transistor seconds, such as 0.6V, apply the 8th voltage by second word line WL2 to the grid 715 of transistor seconds, carry out read operation such as 0.6V, simultaneously when the data that need refresh are 1, can apply the 1st voltage to the drain region 707 of the first transistor by the first transistor bit line BL1, such as 1.2V, apply the 2nd voltage by the first transistor word line WL1 to the grid 714 of the first transistor, such as 0.6V, also can apply tertiary voltage to the drain region 707 of the first transistor by the first transistor bit line BL1, such as 1.2V, apply the 4th voltage by article one word line WL1 to the grid 714 of the first transistor, such as-0.6V, when the data that refresh when needs are 0, apply the 5th voltage by the first transistor bit line BL1 to the drain region 707 of the first transistor, such as-1.2V, apply the 6th voltage by article one word line WL1 to the grid 714 of the first transistor, such as 0.6V, source region 706 ground connection that the first transistor and transistor seconds are shared, realized that like this refresh operation and read operation independently carry out separately, read operation needn't wait for after refresh operation is finished and just can carry out that the present invention has improved the reading rate of embedded DRAM.

The embedded DRAM refresh operation of present embodiment and read operation can be carried out simultaneously, also can timesharing carry out, promptly according to different mode of operations, change and adjust refreshing frequency, to satisfy different power consumption demand, corresponding fast mode (High speed Active mode), adopt at a high speed and refresh, refresh once power consumed maximum like this, corresponding equilibrium mode (High speed Stand-by mode) at full speed such as the 0.5-5 millisecond, adopt at full speed and refresh, refresh once such as 10-50ms, corresponding Half Speed equilibrium mode (half speed Stand-by mode) adopts Half Speed to refresh, refresh once such as 100-300ms, the state (Power off) of corresponding sleep of not reading does not refresh, and power consumption is reduced to minimum like this.Therefore the embedded DRAM of the present invention's proposition can be according to different mode of operations, and under different mode of operations, the frequency difference that refreshes is to satisfy different power consumption demand.

Fig. 7 (b) is made of the embodiment of embedded DRAM several memory cell, the number of memory cell is 3 in the present embodiment, 700 are previously described memory cell among Fig. 7 (b), when needs are operated memory cell 700, need choose BL1 when refreshing (write operation or), BL2 (during read operation), WL1 when refreshing (write operation or), WL2 (during read operation), concrete voltage swing describes in detail at preamble.

The embodiment of Fig. 7 (a) is the embedded DRAM memory cell structure that the present invention proposes based single crystal silicon body, memory cell also can be based on SOI, as Fig. 7 (c), embedded DRAM memory cell structure based on SOI, comprise P-type silicon substrate 701, oxidation buried layer 722, depletion region 704, shallow trench isolation region 705, the source region 706 that heavy doping N++ type the first transistor and transistor seconds are shared and the drain region 707 of the first transistor, the source region 708 and the drain region 709 of light dope N+ type the first transistor, the drain region 710 of heavy doping N++ type transistor seconds, the source region 711 and the drain region 712 of light dope N+ type transistor seconds, p type floater area 713, the gate electrode 714 of the first transistor, the gate electrode 715 of transistor seconds, the sidewall region 716-717 of the first transistor, the sidewall region 718-719 of transistor seconds, the gate oxide 720-721 of the first transistor and transistor seconds.N-type buried region 702 is formed under the transistor as the back grid.Under suitable biasing, depletion region 704 and oxidation buried layer 722 are kept apart the floater area 713 of memory cell fully with substrate and other N type injection zones.The source region 706 general ground connection that the first transistor and transistor seconds are shared.Memory cell respectively has two word lines independent of each other and bit line, wherein article one bit line BL1 is connected to the drain region 707 of the first transistor, second bit line BL2 is connected to the drain region 709 of transistor seconds, article one, word line line WL1 is connected to the gate electrode 714 of the first transistor, and second word line line WL2 is connected to the gate electrode 715 of transistor seconds.

Method of operation based on the embedded DRAM memory cell of SOI is identical with the embedded DRAM memory cell of based single crystal silicon body, and this describes in detail at preamble.

Fig. 8 (a) is that the present invention proposes a kind of triple channel, the memory cell profile of three port embedded DRAMs, 3 n channel metal-oxide field-effect transistors are arranged in the memory cell, specifically comprise P-type silicon substrate 801, N-type buried layer 802,802 upper surfaces are positioned at following first degree of depth of semiconductor surface, the depletion region 803 that N type buried layer and P type substrate form, shallow trench isolation region 805,805 go deep into first degree of depth below, promptly go deep into buried layer 802 lower surfaces, the source region 806 of heavy doping N++ type the first transistor and the 3rd transistors share and the drain region 807 of the first transistor, the source region 808 and the drain region 809 of light dope N+ type the first transistor, the zone 810 that share in the source region of heavy doping N++ type transistor seconds and the 3rd transistorized drain region and the drain region 811 of transistor seconds, the source region 812 and the drain region 813 of light dope N+ type transistor seconds, light dope N+ type the 3rd transistorized source region 814 and drain region 815, first, second, the 3rd transistorized source region, drain region and p type substrate form depletion region 804, shallow trench isolation region 805, depletion region 804,803 surround and the p type floater area 816 that is the electricity isolation on every side, the gate electrode 817 of the first transistor, the gate electrode 818 of transistor seconds, the 3rd transistorized gate electrode 819, the sidewall region 820-821 of the first transistor, sidewall region 822-823 the 3rd transistorized sidewall region 824-825 of transistor seconds, the first transistor, transistor seconds and the 3rd transistorized gate oxide 826-828.Three transistors respectively have a pair of word line bit line right, wherein article one bit line BL1 is connected to the drain region 809 of the first transistor, drain region 811, the three bit lines BL3 that second bit line BL2 is connected to transistor seconds are connected to 810, three bit lines in the 3rd transistorized drain region and link to each other with three ports separately.Article one, word line line WL1 is connected to the gate electrode 817 of the first transistor, and 818, the three word line line WL3 of gate electrode that second word line line WL2 is connected to transistor seconds are connected to the 3rd transistorized gate electrode 819.

When needs when memory cell writes data 1, apply the 9th voltage by the 3rd transistor bit line BL3 to the 3rd transistorized drain region 810, the 9th voltage is high level, amplitude range can lie prostrate at 1.0-1.4, typically such as 1.2V, apply the 10th voltage by the 3rd transistor word line WL3 to the 3rd transistorized grid 819, the 10th voltage is moderate range, can lie prostrate at 0.4-0.8, representative value is such as 0.6V, the 3rd transistorized source region 806 ground connection, make like this and have higher electric field in the drain region 810, channel electrons obtains enough energy at the drain terminal high field region, and electronics---the hole is right by the ionization by collision generation, and move to the buoyancy aid 816 than low potential in the hole, because the source---the body surplus is in a potential barrier, the hole will be deposited in buoyancy aid 816, has raised the electromotive force of buoyancy aid 816, because the inclined to one side effect of lining, when underlayer voltage raises (for P type substrate), can make threshold voltage reduce, so just be equivalent to finish and write 1 operation.

Can also write data 1 to memory cell by the following method, by the 3rd transistor bit line BL3 with the 3rd transistorized drain region 810 ground connection, apply the 11st voltage by the 3rd transistor word line WL3 to the 3rd transistorized grid 819, the 11st voltage is negative voltage, such as-1.2V, the 3rd transistorized source region 806 ground connection, cause grid and cause potential barrier reduction (GIDL), this moment, added drain terminal voltage can produce higher electric field in the grid leak overlapping region, thereby produce a dark depleted region, and thereby this high electric field can make the electronics generation tunnelling phenomenon in the drain region 810 produce electron hole pair, the hole flows to buoyancy aid 816 under effect of electric field, raised the electromotive force of buoyancy aid 816, because the inclined to one side effect of lining, when underlayer voltage raises (for P type substrate), can make threshold voltage reduce, so just be equivalent to finish and write 1 operation.

When needs when memory cell writes data 0, apply the 12nd voltage by the 3rd transistor bit line BL3 to the 3rd transistorized drain region 810, the 12nd voltage is negative voltage, such as-1.2V, apply the 13rd voltage by the 3rd transistor word line WL3 to the 3rd transistorized grid 819, the 13rd voltage is moderate range, can lie prostrate at 0.4-0.8, representative value is such as 0.6V, the 3rd transistorized source region 806 ground connection because buoyancy aid 816 has the hole, make substrate potential for just, so just caused the positively biased of substrate-drain region PN junction, under the effect of positive bias-voltage, be stored in hole in the buoyancy aid 816 and can break away from and wherein be injected into drain region 810, make the level of underlayer voltage before recovering, from and improved threshold voltage, so just be equivalent to write 0.

During data in needing read memory cell, can apply the 14th voltage to the drain region 807 of the first transistor by the first transistor bit line BL1, the 14th voltage is moderate range, can lie prostrate at 0.4-0.8, representative value applies 15th voltage by the first transistor word line WL1 to the grid 817 of the first transistor such as 0.6V, the 15th voltage is moderate range, can lie prostrate at 0.4-0.8, representative value is such as 0.6V, source region 806 ground connection of the first transistor; Also can apply 16th voltage higher to the drain region 811 of transistor seconds by transistor seconds bit line BL2 than source region 810 voltages of transistor seconds, such as the high 0.6V of voltage than the source region 810 of transistor seconds, apply the 17th high voltage of voltage by transistor seconds word line WL2 to the grid 818 of transistor seconds than the source region 810 of transistor seconds, such as the high 0.6V of voltage than the source region 810 of transistor seconds, like this, when the data of cell stores are 1, because threshold voltage is less, source-drain area can flow through big relatively electric current, when the data of DRAM cell stores are 0, because threshold voltage is bigger, source-drain area can flow through relatively little electric current.The data that electric current by relatively flowing through source-drain area and reference current can be determined cell stores.

Identical with the embodiment of Fig. 7 (a), the embodiment of Fig. 8 (a) can realize that also refresh operation and read operation carry out simultaneously, promptly when the 3rd transistor carries out refresh operation, the first transistor and transistor seconds can carry out read operation, because read operation and refresh operation are separate, the present invention has improved the reading speed of embedded DRAM.Can pass through the data of the word line bit line reading cells of the first transistor or transistor seconds in addition among the embodiment of Fig. 8 (a) separately, also can be by choosing the word line bit line of the first transistor or transistor seconds simultaneously, export the data in the memory cell to different logical block concurrently, can improve the speed of service of embedded system.

The embedded DRAM refresh operation of present embodiment and read operation can be carried out simultaneously, also can be according to different mode of operations, make refreshing frequency can change adjustment, to satisfy different power consumption demand, corresponding fast mode (Highspeed Active mode), adopt at a high speed and refresh, refresh once such as the 0.5-5 millisecond, power consumed maximum like this, corresponding equilibrium mode (High speed Stand-by mode) at full speed adopts at full speed and refreshes, and refreshes once such as 10-50ms, corresponding Half Speed equilibrium mode (half speed Stand-by mode), the employing Half Speed refreshes, and refreshes once the state (Power off) of corresponding sleep of not reading such as 100-300ms, do not refresh, power consumption is reduced to minimum like this.Therefore the embedded DRAM that proposes of the present invention can be according to the speed operation of read operation in different mode of operations, and under different mode of operations, the frequency difference that refreshes is to satisfy different power consumption demand.

Fig. 8 (b) is made of the embodiment of embedded DRAM several memory cell, the number of memory cell is 3 in the present embodiment, 800 are previously described memory cell among Fig. 8 (b), when needs are operated memory cell 800, need choose BL1 (during read operation), BL2 (during read operation), BL3 when refreshing (write operation or), WL1 (during read operation), WL2 (during read operation), WL3 when refreshing (write operation or), concrete voltage swing describes in detail at preamble.

The memory cell that the present invention proposes comprises separate three word lines and three bit lines, three ports are arranged, one of them port is used for write operation and refresh operation, two ports are used for read operation, the work of these three ports is separate, makes the data in the memory cell to be exported to two different logical blocks.Memory cell can comprise separate n bar word line and n bit lines (1＜n＜100) during actual the use, n port arranged, one of them port is used for write operation and refresh operation, n-1 port is used for read operation, the work of this n port is separate, make and the data in the memory cell can be exported to n different logical blocks, the speed of elevator system greatly.

The embodiment of Fig. 8 (a) is based on the embedded DRAM memory cell structure of monocrystalline silicon body, and in fact memory cell also can be based on SOI, and this is not a limitation of the present invention.

Fig. 9 (a) is the another kind of double channel that proposes of the present invention, the memory cell profile of dual-port embedded DRAM, comprises a n raceway groove floating gate type transistor and a n channel metal-oxide field-effect transistor in the memory cell.The memory cell that the present invention proposes comprises P-type silicon substrate 901, N-type buried layer 902,902 upper surfaces first degree of depth below semiconductor surface, and buried layer 902 forms depletion region 903 with substrate, and shallow trench isolation region 905,905 is deep into below 902 upper surfaces.The heavy doping N++ type drain region 907 of the heavy doping N++ type source region 906 of the first transistor and floating boom transistors share and the first transistor, the light dope N+ source region 908 and the drain region 909 of type the first transistor, the transistorized heavy doping N++ of floating boom type drain region 910, the transistorized light dope N+ of floating boom type source region 911 and drain region 912, two transistorized sources, leak the depletion region 904 that forms with p type substrate, shallow trench isolation region 905, depletion region 903 and 904 surrounds and is the p type floater area 913 that electricity is isolated on every side, the gate electrode 914 of the first transistor, the transistorized gate electrode 915 of floating boom, the sidewall region 916-917 of the first transistor, the transistorized sidewall region 918-919 of floating boom, the transistorized gate oxide 920-922 of the first transistor and floating boom, the transistorized floating boom 923 of floating boom.The source region 906 general ground connection of the first transistor and floating boom transistors share.Two transistors respectively have a pair of word line bit line right, wherein article one bit line BL1 is connected to the drain region 907 of the first transistor, second bit line BL2 is connected to the transistorized drain region 909 of floating boom, each links to each other two bit lines with two ports, article one, word line line WL1 is connected to the gate electrode 914 of the first transistor, and second word line line WL2 is connected to the transistorized gate electrode 915 of floating boom.

When needs when memory cell writes data 1, apply the 18th voltage by transistor seconds bit line BL2 to the transistorized drain region 910 of floating boom, the 18th voltage is high level, amplitude range can lie prostrate at 1.0-1.4, typically such as 1.2V, apply the 19th voltage by transistor seconds word line WL2 to the transistorized grid 915 of floating boom, the 19th voltage is moderate range, can lie prostrate at 0.4-0.8, representative value is such as 0.6V, the transistorized source region of floating boom 906 ground connection make like this to have higher electric field in the drain region 910 that channel electrons obtains enough energy at the drain terminal high field region, electronics---the hole is right by the ionization by collision generation, move to the buoyancy aid 913 than low potential in the hole, because the source---the body surplus is in a potential barrier, and the hole will be deposited in buoyancy aid 913, raised the electromotive force of buoyancy aid 913, because the inclined to one side effect of lining can make threshold voltage reduce when underlayer voltage raises (for P type substrate), so just be equivalent to finish and write 1 operation.

Can also write data 1 to memory cell by the following method, apply the 20th voltage by transistor seconds bit line BL2 to the transistorized drain region 910 of floating boom, such as 1.2V, apply the 21st voltage by transistor seconds word line WL1 to the transistorized grid 915 of floating boom, the 21st voltage is negative voltage, such as-0.6V, the transistorized source region of floating boom 906 ground connection, cause grid and cause potential barrier reduction (GIDL), this moment, added drain terminal voltage can produce higher electric field in the grid leak overlapping region, thereby produce a dark depleted region, and thereby this high electric field can make the electronics generation tunnelling phenomenon in the drain region 910 produce electron hole pair, the hole flows to buoyancy aid 913 under effect of electric field, raised the electromotive force of buoyancy aid 913, because the inclined to one side effect of lining can make threshold voltage reduce when underlayer voltage raises (for P type substrate), so just be equivalent to finish and write 1 operation.

When needs when memory cell writes data 0, apply the 22nd voltage by transistor seconds bit line BL2 to the transistorized drain region 910 of floating boom, 22 voltages are negative voltage, such as-1.2V, apply the 23rd voltage by second word line WL2 to the transistorized grid 915 of floating boom, the 23rd voltage is moderate range, can lie prostrate at 0.4-0.8, representative value is such as 0.6V, the transistorized source region of floating boom 906 ground connection because buoyancy aid 913 has the hole, make substrate potential for just, so just caused the positively biased of substrate-drain region PN junction, under the effect of positive bias-voltage, be stored in hole in the buoyancy aid 913 and can break away from and wherein be injected into drain region 910, make the level of underlayer voltage before recovering, from and improved threshold voltage, so just be equivalent to write 0.

During data in needing read memory cell, apply the 24th voltage by the first transistor bit line BL1 to the drain region 907 of the first transistor, the 24th voltage is moderate range, can lie prostrate at 0.4-0.8, representative value is such as 0.6V, apply the 25th voltage by the first transistor word line WL1 to the grid 914 of the first transistor, the 25th voltage is moderate range, can lie prostrate at 0.4-0.8, representative value is such as 0.6V, source region 906 ground connection of the first transistor, like this, when the data of cell stores are 1, because threshold voltage is less, source-drain area can flow through big relatively electric current, when the data of DRAM cell stores are 0, because threshold voltage is bigger, source-drain area can flow through relatively little electric current.The data that electric current by relatively flowing through source-drain area and reference current can be determined cell stores.

Adopt the floating boom transistor to replace original common metal oxide field-effect transistor in the present embodiment, purpose is to realize non-volatile storage, be still can store data after the power down, specific operation process is as follows: when will power down, obtain its source-drain current according to previously described method by the word line bit line of choosing the first transistor, through comparing with reference current, data in the reading cells, the result who reads is connected to voltage selector 926, voltage selector 926 produces relevant voltage to the transistorized word line bit line of floating boom according to the data that read, particularly, if reading the data that obtain memory cell is 0, then voltage selector 926 produces high voltage, and to the transistorized grid 915 of floating boom, voltage selector 926 produces logic low such as 20V, be that 0V is to the transistorized drain region 910 of floating boom, depositing electric charge in floating boom transistorized floating boom 923, is 1 if read the data that obtain memory cell, and then obstructed overvoltage selector 926 produces effective voltage to transistorized grid of floating boom and drain region.Data in the memory cell are just temporary in the floating boom transistor, even power down can not disappear yet like this.After powering on, by the second word line is transistorized grid 915 ground connection of floating boom, by the second bit line is that the transistorized drain region 910 of floating boom applies logic high, such as 1.2V, judge in the transistorized floating boom 923 of floating boom according to the electric current on the bit line whether electric charge is arranged, if in the transistorized floating boom 923 of floating boom electric charge is arranged, then the transistorized threshold voltage of floating boom is higher, the electric current that flows through the transistorized drain region 910 of floating boom is less, show that its data of depositing are 0, these data are temporary in buffer 925, if do not have electric charge in the transistorized floating boom 923 of floating boom, then the transistorized threshold voltage of floating boom is lower, the electric current that flows through the transistorized drain region 910 of floating boom is bigger, show that its data of depositing are 1, these data are temporary in buffer, read the data in the floating boom transistor floating boom after, by being that the transistorized grid 915 of floating boom applies negative level by the second word line, such as-20V, the transistorized drain region of floating boom 910 ground connection are wiped the electric charge in the floating boom transistor floating boom 923.Afterwards, be that memory cell writes data according to the data in the buffer 925 by the floating boom transistor, the method that writes data for memory cell is described in detail at preamble.Data in the back memory cell that powers on like this just are restored to the state before the power down, have realized non-volatile storage.

Present embodiment can realize that also refresh operation and read operation carry out simultaneously, promptly when the floating boom transistor carries out refresh operation, the first transistor can carry out read operation, because read operation and refresh operation are separate, the present invention has improved the reading speed of embedded DRAM.

The embedded DRAM refresh operation of present embodiment and read operation can be carried out simultaneously, also can be according to different mode of operations, make refreshing frequency can change adjustment, to satisfy different power consumption demand, corresponding fast mode (Highspeed Active mode), adopt at a high speed and refresh, refresh once such as the 0.5-5 millisecond, power consumed maximum like this, corresponding equilibrium mode (High speed Stand-by mode) at full speed adopts at full speed and refreshes, and refreshes once such as 10-50ms, corresponding Half Speed equilibrium mode (half speed Stand-by mode), the employing Half Speed refreshes, and refreshes once the state (Power off) of corresponding sleep of not reading such as 100-300ms, do not refresh, power consumption is reduced to minimum like this.Therefore the embedded DRAM of the present invention's proposition can be according to different mode of operations, and under different mode of operations, the frequency difference that refreshes is to satisfy different power consumption demand.

Fig. 9 (b) is made of the embodiment of embedded DRAM several memory cell, the number of memory cell is 3 in the present embodiment, 900 are previously described memory cell among Fig. 9 (b), when needs are operated memory cell 900, need choose BL1 when refreshing (write operation or), BL2 (during read operation), WL1 when refreshing (write operation or), WL2 (during read operation), concrete voltage swing describes in detail at preamble.

The embodiment of Fig. 9 (a) is based on the embedded DRAM memory cell structure of monocrystalline silicon body, and in fact memory cell also can be based on SOI, and this is not a limitation of the present invention.

All be based on p type silicon substrate among this paper embodiment, the embedded dynamic memory of p type buoyancy aid in fact also can adopt based on N type silicon substrate, the embedded dynamic memory of N type buoyancy aid, and this is not a limitation of the present invention.

Claims

1. the embedded DRAM of a multiport, many raceway grooves comprises several memory cell;

Each memory cell has n transistor, n is a natural number, n 〉=2, each transistor comprises source region, drain region, grid and the tagma between source region and drain region, source region between adjacent transistor and drain region interconnect or share, during each transistor turns, form conducting channel between this transistorized source and leakage;

Each transistor has 1 pair of word line bit line right, i.e. 1 word line and 1 bit lines; Each transistorized bit line links to each other with an input/output end port;

Different crystal pipe in the memory cell is arranged in same buoyancy aid, buoyancy aid and electricity isolation on every side;

In described buoyancy aid, inject charge carrier or extract charge carrier by at least one port, regulate transistorized threshold voltage, reach the purpose of write signal; Read or read the electric current of source transistor between leaking simultaneously by a plurality of ports by a port, by differentiating the size of electric current, reach the purpose of read output signal, big electric current is represented first data mode 1, and little electric current is represented the 2nd data mode 0; Regularly original signal in the memory cell is write back by at least one port, reached the purpose of refresh signal;

The word line bit line of different crystal pipe is to independently of one another, simultaneously or timesharing selected, and then simultaneously or timesharing choose corresponding different crystal pipe, by corresponding ports simultaneously or the timesharing storage operation that reads and refresh.

2. memory according to claim 1 is characterized in that described float structure is the float structure that is formed in the monocrystalline substrate, or is formed at the float structure in the SOI substrate, wherein:

The float structure that is formed in the monocrystalline substrate is as follows: form the buried layer with second conduction type below the semiconductor surface with first conduction type, the buried layer upper surface is positioned at following first degree of depth of semiconductor surface, the zone that has first conduction type above buried layer forms memory cell, isolated by shallow trench isolation region between the memory cell, the degree of depth of shallow trench isolation region is deeper than following first degree of depth of semiconductor surface; Comprise n transistor in each memory cell, n is a natural number, n 〉=2, each transistor comprises source region, drain region and the tagma between source region and drain region with second conduction type, between buried layer and tagma, between source region and tagma, form depletion region between drain region and tagma, depletion region and shallow trench isolation region surround and form the float structure of isolating with electricity all around;

The float structure that is formed in the SOI substrate is as follows: be positioned on the insulating barrier, have in the monocrystalline silicon thin film of first conduction type and form memory cell, comprise n transistor in each memory cell, n is a natural number, n 〉=2, each transistor comprises the source region with second conduction type, the drain region and be positioned at the source region and the drain region between the tagma, the transistorized source region and the drain region degree of depth that are positioned at the memory cell edge connect monocrystalline silicon thin film, other is not positioned at the transistorized source region at memory cell edge and the drain region degree of depth less than the monocrystalline silicon thin film degree of depth, insulating barrier, connect the source region of monocrystalline silicon thin film, the drain region surrounds formation and electric float structure of isolating all around with the depletion region that the tagma forms respectively.

3. memory according to claim 1 is characterized in that n transistor in the described same memory cell all is MOS (metal-oxide-semiconductor) memory.

4. memory according to claim 1, it is characterized in that n transistor in the described same memory cell comprises and two kinds of transistors below are at least respectively arranged: a kind of is MOS (metal-oxide-semiconductor) memory, and a kind of is the MOS (metal-oxide-semiconductor) memory with floating boom with non-volatile memory function.

5. memory according to claim 1 is characterized in that n equals 2, and each unit comprises two MOS (metal-oxide-semiconductor) memory: the first transistor and transistor seconds; The source of the leakage of the first transistor or source and transistor seconds or leak links to each other or is shared, and links to each other with ground; The word line of the first transistor and transistor seconds connects the grid to the first transistor and transistor seconds respectively; The bit line of the first transistor and transistor seconds connects respectively to the leakage or the source of the source of the first transistor or leakage and transistor seconds, and is connected with the input/output end port of the first transistor and transistor seconds respectively.

6. the methods of storage operating of memory as claimed in claim 5 is characterized in that described transistor is two n channel metal-oxide field-effect transistors, and its methods of storage operating comprises:

Write 1: the bit line to the first transistor applies first voltage, and word line applies second voltage, and the value of first voltage is bigger than second voltage, causes hot carrier and injects, and makes the hole inject buoyancy aid, reduces transistorized threshold voltage; Perhaps for the bit line of the first transistor applies tertiary voltage, word line applies the 4th voltage, and the 4th voltage is negative voltage, causes grid and causes the potential barrier reduction, makes the hole inject buoyancy aid, reduces transistorized threshold voltage;

Write 0: for the bit line of the first transistor applies the 5th voltage, the 5th voltage is negative voltage, and word line applies the 6th voltage, causes the positively biased of buoyancy aid-drain region PN junction, extracts the hole in the buoyancy aid, improves transistorized threshold voltage;

Refresh: according to the original data of memory cell is that the word line of the first transistor and bit line apply and write 0 or write 1 required voltage, reaches the purpose of refresh of memory cells legacy data;

Read: for the bit line and the word line of transistor seconds applies the 7th voltage and the 8th voltage respectively, read the electric current of transistor seconds by the port of transistor seconds, electric current that 1 and 0 state is corresponding big respectively and little electric current, thus tell different store statuss;

The word line bit line of choosing transistor seconds carries out read operation and the word line bit line of choosing the first transistor to memory cell, and that memory cell is carried out refresh operation is separate, refreshes when reading, and perhaps refreshes when not reading.

7. memory according to claim 1 is characterized in that n equals 3, comprises 3 metal-oxide-semiconductor field effect t transistors in the described unit: the first transistor, transistor seconds and the 3rd transistor; The first transistor, transistor seconds and the 3rd transistorized grid are connected with the 3rd transistorized word line with the word line of the first transistor, the word line of transistor seconds respectively; The leakage of the first transistor or source and the 3rd transistorized source or leakage is connected or share, and be connected with ground; The source of transistor seconds or leak with the 3rd transistorized leakage or the source links to each other or shared; The leakage of the source of the first transistor or leakage, transistor seconds or source are connected with the 3rd transistorized bit line with the bit line of the first transistor, the bit line of transistor seconds respectively with the 3rd transistorized leakage or source, and are connected with the first transistor, transistor seconds, the 3rd transistorized input/output end port respectively.

8. as the methods of storage operating to the described memory of claim 7, it is characterized in that described different crystal pipe is 3 n channel metal-oxide field effect transistor transistors, its methods of storage operating comprises:

Write 1: be that the 3rd transistorized bit line applies the 9th voltage, word line applies the 10th voltage, and the value of the 9th voltage is greater than the 10th voltage, electronics---the hole is right to utilize the ionization by collision generation, cause hot carrier and inject, make the hole inject floater area, reduce transistorized threshold voltage; Perhaps be the 3rd transistorized bit line ground connection, word line applies the 11st voltage, and the 11st voltage is negative voltage, causes grid and causes potential barrier reduction GIDL, makes the hole inject floater area, reduces transistorized threshold voltage;

Write 0: be that the 3rd transistorized bit line applies the 12nd voltage, the 12nd voltage is negative sense, and word line applies forward the 13rd voltage, causes the positively biased of buoyancy aid-drain region PN junction, extracts the hole in the buoyancy aid, improves transistorized threshold voltage;

Refresh: according to the original data of memory cell, regularly be that the 3rd transistorized word line and bit line apply and write 0 or write 1 required voltage, reach the purpose of refresh of memory cells legacy data;

Read: for the bit line and the word line of the first transistor applies the 14th and the 15th voltage respectively, the port by the first transistor reads the size of current of the first transistor source between leaking, the electric current that 1 or 0 state is corresponding big and little respectively, thus tell data in the memory cell; Perhaps apply forward the 16th voltage that is higher than its source voltage terminal for the bit line of transistor seconds, for the word line of transistor seconds applies forward the 17th voltage, port by transistor seconds reads the size of current of transistor seconds source between leaking, 1 or 0 state is the big and little electric current of correspondence respectively, thereby tells the data in the memory cell; Perhaps for applying, the bit line of the first transistor and transistor seconds and word line read required voltage simultaneously, electric current between leak in the source of reading the first transistor and transistor seconds by the first transistor port and transistor seconds port simultaneously obtains the storage data from the first transistor port and transistor seconds port simultaneously;

Choosing the 3rd transistorized word line bit line that memory cell is carried out refresh operation and the word line bit line of choosing the first transistor and/or transistor seconds, that memory cell is carried out read operation is separate.

9. memory according to claim 4 is characterized in that it is MOS (metal-oxide-semiconductor) memory that n equals 2, the 1 transistors, and the 2nd transistor is the floating gate type MOS (metal-oxide-semiconductor) memory; The 1st transistor links to each other with the 2nd transistorized word line with the 1st transistor respectively with the 2nd transistorized grid; The 1st transistorized leakage or source link to each other with the 2nd transistorized source or leakage or share, and are connected with ground; The 1st transistorized source or leakage, the 2nd transistorized leakage or source are connected with the bit line of the 1st transistorized bit line, transistor seconds respectively, and are connected with the 2nd transistorized port with the 1st transistor respectively.

10. as the methods of storage operating of memory as described in the claim 9, it is characterized in that the 1st transistor and the 2nd transistor are the n channel transistor, its methods of storage operating comprises:

Write 1: be that the 2nd transistorized bit line applies the 18th voltage, word line applies the 19th voltage, and the value of the 18th voltage is greater than the 19th voltage, electronics---the hole is right to utilize the ionization by collision generation, cause hot carrier and inject, make the hole inject floater area, reduce transistorized threshold voltage; Perhaps be that the 2nd transistorized bit line applies the 20th voltage, it is negative voltage that word line applies the 21st voltage, causes grid and causes potential barrier reduction GIDL, makes the hole inject floater area, reduces transistorized threshold voltage;

Write 0: be that the 2nd transistorized bit line applies the 22nd voltage, the 22nd voltage is negative voltage, and word line applies the 23rd voltage, causes the positively biased of buoyancy aid-drain region PN junction, extracts the hole in the buoyancy aid, improves transistorized threshold voltage;

Refresh: according to the original data of memory cell is that the 2nd transistorized word line and bit line apply and write 0 or write 1 required voltage, reaches the purpose of refresh of memory cells legacy data;

Choose the 1st transistorized word line bit line to carrying out read operation and choosing the 2nd transistorized word line bit line separate to carrying out refresh operation.