CN101217626A - Broad band frequency reducer based on band-pass sigma-delta modulation - Google Patents

Abstract

The invention relates to a broadband frequency demultiplier based on modulation of bandpass Sigma-Delta, in particular to a broadband frequency demultiplier making use of modulation of bandpass Sigma-Delta to filter out-of-band-signal. The invention is characterized in that: the output end of a low noise preamplifier is connected with the input end of an anti-aliasing low-frequency filter; the output end of the anti-aliasing low-frequency filter is connected with the input end of a bandpass Sigma-Delta modulation circuit; an input signal obtained from an antenna is input to the low noise preamplifier, a signal processed by the low noise preamplifier is input to the anti-aliasing low-frequency filter, a signal processed by the anti-aliasing low-frequency filter is input to the bandpass Sigma-Delta modulation circuit to be modulated and the obtained signal output by the bandpass Sigma-Delta modulation circuit is a digital signal. The invention makes use of bandpass Sigma-Delta ADC to sample an input signal, directly introduces an analog signal into a digital domain, thereby avoiding analog mixing; meanwhile, the bandpass modulation reduces the bandwidth of the input signal, thereby reducing dynamic space of Sigma-Delta ADC.

Description

A kind of broad band frequency reducer based on the logical ∑ of band-Δ modulation

Technical field

The present invention relates to a kind of broad band frequency reducer, specifically utilize the broad band frequency reducer filtering out of band signal of the logical ∑ of band-Δ modulation based on the logical ∑ of band-Δ modulation.

Background technology

In prior art, the broad band frequency reducer that is used for Digital Television (digital TV) has aspect two in the integrated main difficulty that generally faces of chip: the frequency mixer of the high dynamic space of solution needs of pure simulation (High Dynamic Range Mixer) will solve the problem of Harmonic Interference (HarmonicInterference) simultaneously.Because common frequency mixer adopts is that square wave but not harmonic signal are inevitably introduced odd harmonic and disturbed.Simultaneously because the integrated difficulty of big parameter simulation device is higher, analog filter also be one difficult with integrated circuit composition.Comparing successful circuit in the pure simulation frequency demultiplier is the Super Heterodyne structure that Microtune company adopts, the frequency reducing again of first raising frequency rate.This scheme efficiently solves the Harmonic Interference problem, but needs the surperficial mechanical wave filter of a peripheral hardware, and integrated level is lower.

Based on the above shortcoming of modeling scheme, the frequency reducing scheme that digital-to-analogue is mixed is widely used in DVB-C, in the Digital Television frequency demultiplier schemes such as DVB-T.The scheme that digital-to-analogue is mixed generally is that the frequency mixer by a big dynamic space directly mixes down to Low Medium Frequency with required frequency band signals, then by digital-to-analogue conversion, utilizes the DSP method to remove the negative frequency interference.The advantage of this method is the integrated level height, has avoided the shortcoming of analog filtering.The shortcoming of digital-to-analogue hybrid plan is that it needs the analog-digital converter (ADC) of a very high dynamic space, and owing to the existence of a large amount of out of band signals, the interference of phase noise is highly significant also simultaneously.

Summary of the invention

The objective of the invention is to overcome above-mentioned weak point, thereby provide a kind of broad band frequency reducer based on the logical ∑ of band-Δ modulation, utilize the logical ∑ of band-Δ ADC sampled input signal, directly analog signal is introduced domain digital signal (Digital Domain), avoided analog frequency mixing, bandpass modulation has simultaneously reduced the bandwidth of input signal, has reduced the dynamic space of ∑-Δ ADC.

Main solution of the present invention is achieved in that

The present invention includes amplifier, low-frequency filter, feature is that the output of low noise preamplifier links to each other with the input of anti-aliasing low-frequency filter, and the output of anti-aliasing low-frequency filter links to each other with the input of the logical ∑-sigma-Delta modulation circuit of band; The input signal that obtains from antenna is input to the low noise preamplifier, the signal of handling through the low noise preamplifier is input to anti-aliasing low-frequency filter, the signal of handling through anti-aliasing low-frequency filter is input to the logical ∑-sigma-Delta modulation circuit of band and modulates, and what the output of the logical ∑-sigma-Delta modulation circuit of band obtained is digital signal.Logical ∑-the sigma-Delta modulation circuit of described band is ∑-Δ analog-digital converter ADC.

Described ∑-Δ analog-digital converter ADC adopts analog input V _INLink to each other with the first adder input, first adder output connecting band bandpass filter input, filter output connects the second adder input, second adder output connecting band bandpass filter input, the band pass filter output links to each other with the input of 1 bit comparator, the output of 1 bit comparator is gone into end, digital filter and sampling sample circuit input with 1 DAC respectively and is linked to each other, and the output of 1 DAC links to each other with first adder, second adder respectively and forms closed-loop structure.

Described analog input V _IN First adder 21 of output signal process with 1 figure place weighted-voltage D/A converter DAC26, the output signal of first adder 21 is input to band pass filter 22, the output signal of the output of band pass filter 22 and 1 DAC26 is handled through second adder 23 and is input to band pass filter 24, and the sample rate of comparator 25 is Kf _sIt realizes the quantification of analog input, and what obtained by 25 outputs of 1 bit comparator is the digital signal of 1 bit data stream, through the processing of digital filter and sampling sample circuit 27, obtains the digital signal of N position.

Described ∑-Δ analog-digital converter ADC is the logical ∑ of disengaging time territory band-Δ ADC.

Described ∑-Δ analog-digital converter ADC is the logical ∑ of territory band continuous time-Δ ADC.

Described ∑-Δ analog-digital converter ADC is the logical ∑ of the band of different orders or response function-Δ analog-digital converter ADC etc.

Compared with the prior art the present invention has the following advantages:

The present invention is simple, compact and reasonable for structure; Utilize the logical ∑ of band-Δ analog-digital converter ADC sampled input signal, directly analog signal is introduced domain digital signal (Digital Domain), avoided analog frequency mixing, bandpass modulation has simultaneously reduced the bandwidth of input signal, has reduced the dynamic space of ∑-Δ analog-digital converter ADC; By the adjustment to ∑-Δ analog-digital converter ADC response function, this frequency demultiplier can effectively comprise the Digital Television frequency range of whole 50-800MHz; Owing to avoided big parameter simulation device, this frequency demultiplier can be effectively and the base band demodulating circuit be integrated in the single-chip.

Description of drawings

Fig. 1 is the broad band frequency reducer system configuration schematic diagram that the present invention is based on the logical ∑ of band-Δ modulation.

Fig. 2 is the logical ∑ of second order disengaging time territory band-Δ analog-digital converter ADC structural representation.

Embodiment

Embodiment during following the present invention incites somebody to action in conjunction with the accompanying drawings is further described:

The present invention mainly is made up of low noise preamplifier 11, anti-aliasing low-frequency filter 12, the logical ∑-sigma-Delta modulation circuit 13 (∑-Δ analog-digital converter ADC) of band, first adder 21, band pass filter 22, second adder 23, band pass filter 24,1 bit comparator 25,1 DAC26, digital filter and sampling sample circuit 27 etc.

Shown in Figure 1: the input signal that obtains from antenna is input to low noise preamplifier 11, the output of low noise preamplifier 11 links to each other with the input of anti-aliasing low-frequency filter 12, the signal of handling through low noise preamplifier 11 is input to the very wide anti-aliasing low-frequency filter 12 of this bandwidth, the output of anti-aliasing low-frequency filter 12 links to each other with the input of the logical ∑-sigma-Delta modulation circuit 13 (∑-Δ analog-digital converter ADC) of band, the signal of handling through anti-aliasing low-frequency filter 12 further is input to the logical ∑-sigma-Delta modulation circuit 13 (∑-Δ analog-digital converter ADC) of band and modulates, and what the output of the logical ∑-sigma-Delta modulation circuit 13 (∑-Δ analog-digital converter ADC) of band obtained is digital signal.

According to the frequency range of echo signal, the logical frequency of the band of the logical ∑-sigma-Delta modulation circuit 13 (∑-Δ analog-digital converter ADC) of band can correspondingly be regulated.The method that realizes the logical frequency of accommodation zone has two kinds, and a kind of is to change the sampled signal frequency, and keeps the closed loop gain circuit of ∑-sigma-Delta modulation circuit 13 constant.Another kind method is to change closed loop circuit, and accommodation zone leads to frequency.These two kinds of methods respectively have pluses and minuses.Band disengaging time territory (the discrete timedomain structure) structure that logical ∑-Δ analog-digital converter ADC can adopt switching capacity to realize, or domain structure continuous time of analog filter realization.Carry out digital mixing from the digital signal of ∑-Δ modulation output then through digital filtering, a laggard word filtering of stepping line number and a compensation exported in mixing.

Shown in Figure 2: Fig. 2 is the logical ∑ of a second order disengaging time territory band-Δ ADC structure, and it realizes the logical ∑-sigma-Delta modulation circuit 13 of band.

Described ∑-Δ analog-digital converter ADC adopts analog input V _INLink to each other with first adder 21 inputs, first adder 21 output connecting band bandpass filters 22 inputs, filter 22 outputs connect second adder 23 inputs, second adder 23 output connecting band bandpass filters 24 inputs, band pass filter 24 outputs link to each other with the input of 1 bit comparator 25, the output of 1 bit comparator 25 links to each other with 1 DAC26 input, digital filter and sampling sample circuit 27 inputs respectively, and the output of 1 DAC26 links to each other with first adder 21, second adder 23 respectively and forms closed-loop structure.

Described analog input V _IN First adder 21 of output signal process with 1 DAC26, the output signal of first adder 21 is input to band pass filter 22, the output of band pass filter 22 is handled through second adder 23 with the output signal of 1 DAC26 and is input to the band pass filter 24 that links to each other with second adder 23, and the sample rate of comparator 25 is clock Kf _sIt realizes the quantification of analog input, and what obtained by 25 outputs of 1 bit comparator is the digital signal of 1 bit data stream, and the processing through digital filter and sampling sample circuit 27 obtains N position f _sDigital signal.

The open-loop response function H (z) of this circuit is a half-wave zone bandpass filter

$H\left(z\right)=\frac{z^{2n}-1}{z^2+1}(z^2+2b+1)(z^2-2b+1)$

Wherein n is an integer, $b=\sin (\frac{\mathrm{\π}}{2}-\frac{\mathrm{\π}}{n}),$ Be z ²ⁿThe real part of-1 root nearest apart from the imaginary axis.Closed loop is output as

$Y\left(z\right)=\frac{H\left(z\right)}{1-H\left(z\right)}x\left(z\right)+\frac{1}{1-H\left(z\right)}e\left(z\right)$

In the present example, H (z) is a half-wave filter of simplifying.In actual applications, the parameter of band pass filter selects to depend on that sampling clock frequency, Filter Structures depend on the requirement of sideband inhibition and the limitation of hardware cost.Suppose that sample frequency is 2GHz, realize that 350MHz should be respectively 350/ (2000*2 π), 800/ (2000*2 π) to the height of the filter of the logical frequency range of 800MHz band by frequency.

As mentioned above, though the present invention has only set forth the logical ∑ of a second order disengaging time territory band-Δ analog-digital converter ADC structure, other any type of frequency demultiplier structures based on the logical ∑ of band-Δ ADC all contain within the scope of the present invention.For example, the logical ∑ of the described disengaging time territory band that utilizes switching capacity to realize-Δ ADC.The described logical ∑ of the territory band continuous time-Δ ADC that utilizes analog filter to realize.The logical ∑ of the band of different orders or response function-Δ analog-digital converter ADC etc.

Claims (6)

1. broad band frequency reducer based on the logical ∑ of band-Δ modulation, comprise amplifier (11), low-frequency filter (12), the output that it is characterized in that low noise preamplifier (11) links to each other with the input of anti-aliasing low-frequency filter (12), and the output of anti-aliasing low-frequency filter (12) links to each other with the input of the logical ∑-sigma-Delta modulation circuit (13) of band; The input signal that obtains from antenna is input to low noise preamplifier (11), the signal of handling through low noise preamplifier (11) is input to anti-aliasing low-frequency filter (12), the signal of handling through anti-aliasing low-frequency filter (12) is input to the logical ∑-sigma-Delta modulation circuit (13) of band and modulates, and what the output of the logical ∑-sigma-Delta modulation circuit (13) of band obtained is digital signal.

2. a kind of broad band frequency reducer based on the logical ∑ of band-Δ modulation according to claim 1 is characterized in that it is ∑-Δ analog-digital converter ADC that described band leads to ∑-sigma-Delta modulation circuit (13).

3. a kind of broad band frequency reducer based on the logical ∑ of band-Δ modulation according to claim 1 is characterized in that described ∑-Δ analog-digital converter ADC adopts the defeated (V of simulation _IN) link to each other with first adder (21) input, first adder (21) output connecting band bandpass filter (22) input, filter (22) output connects second adder (23) input, second adder (23) output connecting band bandpass filter (24) input, band pass filter (24) output links to each other with the input of 1 bit comparator (25), the output of 1 bit comparator (25) respectively with 1 DAC (26) input, digital filter links to each other with sampling sample circuit (27) input, the output of 1 DAC (26) respectively with first adder (21), second adder (23) links to each other and forms closed-loop structure;

Described analog input (V _IN) pass through first adder (21) with the output signal of 1 DAC (26), the output signal of first adder (21) is input to band pass filter (22), the output signal of the output of band pass filter (22) and 1 DAC (26) is handled through second adder (23) and is input to band pass filter (24), and the sample rate of comparator (25) is (Kf _s), it realizes the quantification of analog input, what obtained by 1 bit comparator (25) output is the digital signal of 1 bit data stream, through the processing of digital filter and sampling sample circuit (27), obtains the digital signal of (N) position.

4. a kind of broad band frequency reducer based on the logical ∑ of band-Δ modulation according to claim 1 and 2 is characterized in that described ∑-Δ analog-digital converter ADC is the logical ∑ of disengaging time territory band-Δ ADC.

5. according to claim 1 or 3 described a kind of broad band frequency reducers, it is characterized in that described ∑-Δ analog-digital converter ADC is the logical ∑ of territory band continuous time-Δ ADC based on the logical ∑ of band-Δ modulation.

6. according to claim 1 or 4 described a kind of broad band frequency reducers, it is characterized in that described ∑-Δ analog-digital converter ADC is the logical ∑ of the band-Δ analog-digital converter ADC of different orders or response function based on the logical ∑ of band-Δ modulation.

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