CN101211783A - Method for forming metal pattern and method for forming gate electrode in semiconductor device using the same - Google Patents

Method for forming metal pattern and method for forming gate electrode in semiconductor device using the same Download PDF

Info

Publication number
CN101211783A
CN101211783A CNA2007101357459A CN200710135745A CN101211783A CN 101211783 A CN101211783 A CN 101211783A CN A2007101357459 A CNA2007101357459 A CN A2007101357459A CN 200710135745 A CN200710135745 A CN 200710135745A CN 101211783 A CN101211783 A CN 101211783A
Authority
CN
China
Prior art keywords
layer
etching
hard mask
described method
etching stopping
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2007101357459A
Other languages
Chinese (zh)
Other versions
CN101211783B (en
Inventor
吴相录
刘载善
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of CN101211783A publication Critical patent/CN101211783A/en
Application granted granted Critical
Publication of CN101211783B publication Critical patent/CN101211783B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location

Abstract

A method for forming a metal pattern in a semiconductor device includes forming an etch stop layer over a semi-finished substrate including a metal layer, forming a hard mask over the etch stop layer, etching the hard mask to form a hard mask pattern exposing the etch stop layer, and etching the etch stop layer and the metal layer using the hard mask pattern.

Description

Form the method for metal pattern and formation gate electrode in the semiconductor device
Related application
The present invention requires to enjoy respectively on December 27th, 2006 and the korean patent application No.10-2006-0134344 of submission on May 10th, 2007 and the priority of 10-2007-0045288, by reference its full content is incorporated into.
Technical field
The present invention relates to a kind of method of making semiconductor device, more specifically relate to a kind of method and a kind of method of in semiconductor device, using this hard mask to form gate electrode of in semiconductor device, using hard mask to form metal pattern.
Background technology
Polysilicon layer is typically as gate electrode in metal-oxide semiconductor (MOS) (MOS) transistor.This polysilicon gate electrode shows the advantage of stablizing forming process.Yet the various patterns that comprise this gate electrode are the integrated and micronization that becomes along with the height of semiconductor device.The technology of micronization (micronization) has realized 0.15 μ m or littler live width recently.The polysilicon that has been used for the doping that typical gate electrode forms is owing to its high resistivity characteristic has long time of delay.Therefore be difficult to the polysilicon of this doping need in the device of high-speed cruising to be applied to.
This difficulty is along with semiconductor device has become highly integrated and serious restriction that rise to.Therefore, carried out a large amount of research and developments to being used for by on polysilicon, forming the improvement technology that refractory metal as tungsten (W) forms gate electrode recently.
A kind of polysilicon layer and refractory metal of utilizing is briefly described as follows as gate electrode with the typical method that forms gate electrode in semiconductor device.On substrate, form polysilicon and tungsten as gate electrode material.Comprise based on nitride the layer hard mask be formed on the gate electrode.Amorphous carbon layer and silicon oxynitride (SiON) layer as antireflecting coating are formed on the hard mask.The photoresist pattern is formed on the structure that is produced.
Make with photoresist pattern implement etching process with the etching antireflecting coating, thereby form the anti-reflective coating layer pattern as etching mask.Use this anti-reflective coating layer pattern to implement another etching process with etch hard mask, thereby form hard mask pattern as etching mask.Utilize hard mask pattern as the etching mask etch tungsten, to form gate electrode.
Yet the typical method that forms gate electrode in semiconductor device shows following limitation usually.When forming hard mask pattern, a part of tungsten may be owing to comprising based on the hard mask of the layer of nitride and the low selectivity between the tungsten and etched singularly.Thereby, may produce the crack.Very little thereby almost do not have a selectivity based on the layer of nitride and the low selectivity between the tungsten because based on difference on rate of etch between the layer of nitride and the tungsten.
When Fig. 1 and 2 explanation forms the typical method of gate electrode in being applied in semiconductor device, on the tungsten surface, produce the micrograph of crack (with Reference numeral ' A ' expression).Particularly, Fig. 1 explanation produces the crack on the tungsten surface with column rod crystal structure.This crack produces on the tungsten surface with column rod crystal structure usually.
Result from the lip-deep crack of tungsten during the etching of polysilicon subsequently, cause the unusual macrolesion on polysilicon.Therefore, may in the neighboring area, cause wedge shape damage or cause pin hole.This neighboring area is meant except forming extra-regional some zone of semiconductor device memory cell.Form in the neighboring area in order to the driving element that drives memory cell.
Fig. 3 illustrates the micrograph of wedge shape polysilicon damage (with Reference numeral ' B ' expression).Fig. 4 explanation results from the micrograph of the pin hole (with Reference numeral ' C ' expression) in the neighboring area.The damage of this polysilicon and pin hole produce and can cause short circuit between contact plug and gate electrode during contact plug forming process subsequently.Therefore, yields can reduce significantly.Fig. 5 explanation produces the micrograph of the wafer surface of short circuit between contact plug and gate electrode.
Summary of the invention
A kind of method that forms metal pattern in semiconductor device that provides is provided embodiment of the present invention, and it can the lip-deep crack generation at metal level increases yields when using hard mask etching metal level by reducing.
A kind of method that forms grid in semiconductor device that provides is provided another embodiment of the present invention, and it increases yields by produce the crack in the etching process that reduces formation gate electrode in semiconductor device on the surface of gate electrode.
According to an aspect of of the present present invention, a kind of method that forms metal pattern in semiconductor device is provided, comprising: form etching stopping layer comprising on the semi-finished product substrate of metal level; On etching stopping layer, form hard mask; Etch hard mask is to form the hard mask pattern that exposes this etching stopping layer; With utilize this etching stopping layer of hard mask pattern etching and metal level.
According to another aspect of the present invention, a kind of method that forms gate electrode in semiconductor device is provided, comprising: form the structure that comprises as the metal level on upper strata; On metal level, form etching stopping layer; On etching stopping layer, form hard mask; The hard mask of etching part is to form the hard mask pattern that exposes this etching stopping layer; With utilize this etching stopping layer of hard mask pattern etching and metal level.
Description of drawings
The micrograph in the crack that Fig. 1 explanation produces on the surface of the tungsten layer with typical column rod crystal structure;
When Fig. 2 explanation forms the typical method of gate electrode in being applied in semiconductor device, the micrograph in the crack that on the surface of the tungsten layer that forms gate electrode, produces;
When Fig. 3 explanation forms the typical method of gate electrode in being applied in semiconductor device, the micrograph of the wedge shape polysilicon damage of generation;
When Fig. 4 explanation forms the typical method of gate electrode in being applied in semiconductor device, in the neighboring area, produce the micrograph of pin hole;
When Fig. 5 explanation forms the typical method of gate electrode in being applied in semiconductor device, between contact plug and gate electrode, produce the micrograph of the wafer surface of short circuit;
Fig. 6 A forms the sectional view of the method for gate electrode in semiconductor device according to embodiment of the present invention to the 6E explanation.
Embodiment
Embodiment of the present invention relate to a kind of method of metal pattern and method that forms gate electrode of forming in semiconductor device.
Fig. 6 A is to the sectional view of 6E explanation according to embodiment of the present invention method of etch metal layers in semiconductor device.For ease of explanation, explanation in this embodiment is used for forming at semiconductor device the method for the gate electrode of bulb-type recessed structure.
With reference to Fig. 6 A, implement shallow trench isolation from (STI) etching process and wet etch process, in substrate 10, to form bulb-type recessed regional (not shown).Gate insulator 11 is formed on the surface profile (profile) of the structure that is produced.By implementing wet oxidation process, dry oxidation process or free-radical oxidation process to form this gate insulator 11.
Polysilicon layer 12 is formed on the gate insulator 11 and fills sunk area.Form polysilicon layer 12, with as first conductive layer in order to the formation gate electrode.Polysilicon layer 12 comprises by implementing doping or the unadulterated polysilicon layer that low-pressure chemical vapor deposition (LPCVD) equipment forms.As a reference, except silane (SiH 4) outside the gas, also utilize hydrogen phosphide (PH 3), boron chloride (BCl 3) or diborane (B 2H 6) gas forms the polysilicon of doping as impurity gas.
First conductive layer can comprise other material except that polysilicon.First conductive layer can comprise metal level or alloy-layer, and they are the electric conducting materials except that polysilicon.First conductive layer can comprise the stacked structure that is configured to metal level and alloy-layer.
Metal level 13 is formed on the polysilicon layer 12.In this embodiment, metal level 13 comprises as exemplary tungsten.Therefore, after this metal level 13 can be described as tungsten layer 13.Form tungsten layer 13 as second conductive layer that is used to form grid.Except tungsten layer 13, second conductive layer can comprise the stacked structure that is configured to tungsten nitride (WN) layer, tungsten silicide layer and tungsten layer.Second conductive layer can comprise other material except that tungsten.Second conductive layer can comprise transition metal or rare earth metal.Second conducting shell can comprise the alloy-layer of transition metal and rare earth metal, based on layer, silicide layer or its combination of nitride.
For example, transition metal can comprise iron (Fe), cobalt (Co), tungsten (W), nickel (Ni), palladium (Pd), platinum (Pt), molybdenum (Mo) or titanium (Ti).Rare earth metal can comprise erbium (Er), ytterbium (Yb), samarium (Sm), yttrium (Y), lanthanum (La), cerium (Ce), terbium (Tb), dysprosium (Dy), holmium (Ho), thulium (Tm) or gold-plating (Lu).
Etching stopping layer 14 is formed on the tungsten layer 13.Etching stopping layer 14 can comprise the material that follow-up hard mask 15 is had high selectivity.For example, when hard mask 15 comprised material based on nitride, etching stopping layer 14 comprised having greatly optionally polysilicon layer.Yet the material of etching stopping layer 14 is not limited to polysilicon layer.The material of etching stopping layer 14 can change according to the material of hard mask 15.Therefore, etching stopping layer 14 can comprise that the material to hard mask 15 has the material of high selectivity.Have high selectivity and be meant between different materials, to have sizable etch-rate difference.Therefore, under essentially identical situation, hard mask 15 is optionally etched and etching stopping layer 14 is not etched.
When formation had the etching stopping layer 14 of polysilicon layer, polysilicon layer can comprise that doped polycrystalline silicon layer is to change etching characteristic.Therefore, when comparing, can change etching characteristic, thereby more easily control selectivity according to the material of hard mask 15 according to doping content with unadulterated polysilicon layer.
Etching stopping layer 14 forms approximately
Figure A20071013574500091
Or it is thicker.That is, etching stopping layer 14 forms approximately Approximately
Figure A20071013574500093
Thickness.Though not have etching fully be desirable to etching stopping layer 14 when etch hard mask 15, but because partially-etched stop layer 14 can be etched and and the selectivity between etching stopping layer 14 and the hard mask 15 or optionally restriction (limit) have nothing to do, so etching stopping layer 14 forms this thickness.That is, consider that etching stopping layer 14 is etched when etch hard mask 15, the thickness of etching stopping layer 14 forms approximately
Figure A20071013574500094
Or it is thicker.
Hard mask 15 is formed on the etching stopping layer 14.Hard mask 15 can comprise the material that etching stopping layer 14 is had high selectivity.For example, when etching stopping layer comprised polysilicon layer, hard mask 15 can comprise the layer based on nitride.Know clearly it, hard mask 15 can comprise silicon nitride (Si xN y) layer, wherein to represent the x of silicon (Si) atom ratio and represent the y of nitrogen (N) atom ratio to be natural number except that 0, it can comprise in-situ treatment in the chamber of etching stopping layer 14 of polysilicon layer in processing.For example, hard mask 15 comprises silicon nitride (Si 3N 4).
Antireflecting coating 16 is formed on the hard mask 15.Antireflecting coating 16 can comprise inorganic based antireflecting coating or organic group antireflecting coating.For example, the inorganic based antireflecting coating can comprise amorphous carbon layer or silicon oxynitride (SiON) layer.This antireflecting coating 16 can comprise the stacked structure that is configured to amorphous carbon layer and silicon oxynitride layer.The organic group antireflecting coating is used for the ArF interference of light sources of little pattern in order to control.The organic substrate material package draw together make anti-reflecting layer have the curing agent of bridge construction, in order to light absorbing light absorber in the wave-length coverage of exposure light source and as the organic solvent and the hot acid propellant (thermal acid generator) that activate the bridge catalyst for reaction.
Photoresist layer is formed on the antireflecting coating 16.Use photomask to implement exposure and developing process, to form photoresist pattern 17.Photoresist pattern 17 limits the gate electrode zone of the subsequent gate electrode that wherein will form bulb-type recessed grid structure.Photoresist pattern 17 forms in the mode that exposes the zone except that sunk area to the open air.
With reference to Fig. 6 B, utilize photoresist pattern 17 to come etching antireflecting coating 16 as etching mask.Therefore, form anti-reflective coating layer pattern 16A.Utilize anti-reflective coating layer pattern 16A to implement etching process 18 with etch hard mask 15 (Fig. 6 A) as etching mask.Therefore, hard mask pattern 15A is formed on the etching stopping layer 14.
For example, when hard mask 15 comprised that silicon nitride layer and etching stopping layer 14 comprise polysilicon layer, etching process 18 uses can increase between silicon nitride layer and the polysilicon layer optionally fluorocarbon.For example, use C xF yOn behalf of the y of x and the atom ratio of represent fluorine (F) of the atom ratio of carbon (C), gas wherein be natural number except that 0, and use C xH yF zGas, wherein represent the atom ratio of C x, represent hydrogen (H) atom ratio y and represent the z of the atom ratio of F to be natural number except that 0.Carbon tetrafluoride (CF 4), hexafluoroization two carbon (C 2F 6) or octafluoroization three carbon (C 3F 8) can be used as C xF yGas.Fluoroform (CHF 3) can be used as C xH yF zGas.And, also can further add hydrogen (H 2) to increase the selectivity between silicon nitride layer and the polysilicon layer.Hydrogen can increase the selectivity to polysilicon.Therefore, etching process 18 stops on the upper surface of etching stopping layer 14.Therefore, tungsten layer 13 can damaged when at formation hard mask pattern 15A.
As shown in the figure, during etching process 18, photoresist pattern 17 is removed when etching has the hard mask 15 of big thickness.Therefore, the specific part that is formed at the antireflecting coating 16 of photoresist pattern 17 belows also can be removed.
With reference to Fig. 6 C, implement to remove process to remove anti-reflective coating layer pattern 16A (Fig. 6 B).If residual fraction photoresist pattern 17, then residual fraction can remove with anti-reflective coating layer pattern 16A.
Utilize hard mask pattern 15A to come etching etching stopping layer 14, tungsten layer 13 and polysilicon layer 12 as etching mask.Implement etching process in the following manner: residual fraction polysilicon layer 12, rather than remove polysilicon layer 12 fully.Therefore, the residual polysilicon layer 12A with specific thicknesses remains on the substrate 10 that comprises the zone except that the gate electrode zone.Reference numeral 13A and 14A refer to residual tungsten layer 13A and residual etching stopping layer 14A respectively.
For example, by transformer (transformer) coupled plasma (TCP) method, inductively coupled plasma (ICP) method or magnetic intensified response ion(ic) etching (MERIE) method, utilize plasma source to come etching etching stopping layer 14.And, can apply the source power of about 300W～about 500W and about 40W～about 150W substrate bias power.
With reference to Fig. 6 D, form residual cover layer 19.Particularly, cover layer is formed on the surface profile of resulting structures, to be reduced in the follow-up oxidation that reoxidizes two sidewalls of residual tungsten layer 13A during the process.Cover layer can comprise the material that residual polysilicon layer 12A is had high selectivity.For example, cover layer comprises the layer based on nitride.As a reference, the described process that reoxidizes refers to the general oxidizing process of implementing with the etching loss of compensation gate electrode, that is, and and the sidewall loss of the gate electrode that during the etching process that forms gate electrode, produces.
Implement mask process and dry etch process with the etching cover layer.Therefore, form the residual cover layer 19 that surrounds hard mask pattern 15A and contact with two sidewalls of residual etching stopping layer 14A, residual tungsten layer 13A and residual polysilicon layer 12A.
With reference to Fig. 6 E, utilize residual cover layer 19 to implement the expose portion of etching process, thereby expose the part of gate insulator 11 with etch residue polysilicon layer 12A as etch stop layer.Reference numeral 12B is meant the polysilicon layer 12B of patterning.Therefore, form bulb-type recessed gate electrode 20.
According to embodiment of the present invention, implement etching process, the etching stopping layer that will have high selectivity simultaneously during etching comprises the process of structure of metal level inserts metal level with firmly between the mask.Therefore, etching stopping layer is as protective layer protection metal level, the loss of metal level when avoiding etch hard mask.
According to embodiment of the present invention, in the etching process of gate electrode, can reduce tungsten loss by the application of aforementioned method with the stacked structure that is configured to polysilicon layer and tungsten layer.Therefore, on the surface of tungsten layer, the crack be can not produce, and the loss of the polysilicon layer below the tungsten layer and the generation of pin hole therefore can be reduced.In addition, can reduce short circuit between gate electrode and the follow-up contact plug that is formed between the gate electrode.Therefore, can increase the yields of semiconductor device.
According to embodiment of the present invention, the surface of metal level also can be passed through subsequent process (for example, by form the tectal process that reoxidizes above the etched surfaces of metal level) and come oxidation.
Though the present invention has been described about specific embodiments, to those skilled in the art, it is evident that, can make variations and modifications and do not depart from the spirit and scope of the present invention as defined by the appended claims.

Claims (35)

1. method that forms metal pattern in semiconductor device comprises:
Form etching stopping layer comprising on the semi-finished product substrate of metal level;
On described etching stopping layer, form hard mask;
The described hard mask of etching is to form the hard mask pattern that exposes described etching stopping layer; And
Use described etching stopping layer of described hard mask pattern etching and described metal level.
2. the described method of claim 1, wherein said metal level comprise the alloy-layer that is selected from transition metal, rare earth metal, contains transition metal and rare earth metal, a kind of based in layer, silicide layer and the combination thereof of nitride.
3. the described method of claim 1, wherein said etching stopping layer comprise described hard mask are had the high material of selecting, so that at the described hard mask of etching described etching stopping layer of not etching when forming hard mask pattern.
4. the described method of claim 1, wherein said hard mask comprise the layer based on nitride.
5. the described method of claim 1, wherein said hard mask comprises silicon nitride layer.
6. the described method of claim 5, wherein said etching stopping layer comprises polysilicon layer.
7. the described method of claim 6, wherein the described hard mask of etching comprises and uses the etching gas that contains fluorocarbon gas to form described hard mask pattern.
8. the described method of claim 7, wherein said fluorocarbon gas comprises C xF yOn behalf of the y of x and the atom ratio of represent fluorine (F) of the atom ratio of carbon (C), gas wherein be natural number except that 0, or is comprised C xH yF zGas, wherein represent the atom ratio of C x, represent hydrogen (H) atom ratio y and represent the z of the atom ratio of F to be natural number except that 0.
9. the described method of claim 7, wherein the described hard mask of etching comprises using and contains hydrogen (H to form described hard mask pattern 2) additional gas of gas.
10. the described method of claim 1, wherein said etching stopping layer comprises doped polycrystalline silicon layer.
11. the described method of claim 1, wherein said etching stopping layer forms about 50
Figure A2007101357450002C1
～about 1000
Figure A2007101357450002C2
Thickness.
12. the described method of claim 1 wherein forms described hard mask and is included in the basic chamber original position identical with being used for described etching stopping layer and forms hard mask.
13. a method that forms gate electrode in semiconductor device comprises:
Formation comprises the structure of metal level as the upper strata;
On described metal level, form etching stopping layer;
On described etching stopping layer, form hard mask;
The described hard mask of etching part is to form the hard mask pattern that exposes described etching stopping layer; With
Utilize described etching stopping layer of described hard mask pattern etching and described metal level.
14. the described method of claim 13, wherein said metal level comprise the alloy-layer that is selected from transition metal, rare earth metal, contains transition metal and rare earth metal, a kind of based in layer, silicide layer and the combination thereof of nitride.
15. the described method of claim 13 also is included in the described hard mask of formation and forms antireflecting coating afterwards on described hard mask.
16. the described method of claim 15, wherein said antireflecting coating comprise a kind of in inorganic based antireflecting coating and the organic group antireflecting coating.
17. the described method of claim 15, wherein said antireflecting coating comprise amorphous carbon layer and comprise a kind of in the stacked structure of amorphous carbon layer and silicon oxynitride layer.
18. the described method of claim 13, wherein said etching stopping layer comprise the material that described hard mask is had high selectivity, make at the described hard mask of etching when forming hard mask pattern the described etching stopping layer of not etching.
19. the described method of claim 18, wherein said hard mask comprise the layer based on nitride.
20. the described method of claim 18, wherein said hard mask comprises silicon nitride layer.
21. the described method of claim 18, wherein said etching stopping layer comprises polysilicon layer.
22. the described method of claim 21, wherein the described hard mask of etching comprises that to form described hard mask pattern use contains the etching gas of fluorocarbon gas.
23. the described method of claim 22, wherein said fluorocarbon gas comprises C xF yOn behalf of the y of x and the atom ratio of represent fluorine (F) of the atom ratio of carbon (C), gas wherein be natural number except that 0, or is comprised C xH yF zGas, wherein represent the atom ratio of C x, represent hydrogen (H) atom ratio y and represent the z of the atom ratio of F to be natural number except that 0.
24. the described method of claim 22, wherein the described hard mask of etching comprises that to form hard mask pattern use comprises hydrogen (H 2) additional gas of gas.
25. the described method of claim 20, wherein said etching stopping layer comprises doped polycrystalline silicon layer.
26. the described method of claim 13, wherein said etching stopping layer forms about 50
Figure A2007101357450004C1
～about 1000 Thickness.
27. the described method of claim 13 wherein forms described hard mask and is included in the basic chamber original position identical with being used for described etching stopping layer and forms described hard mask.
28. the described method of claim 13, wherein said structure comprises the conductive layer that is formed under the described metal level.
29. the described method of claim 28, wherein the described metal level of etching comprises that the described conductive layer of etching is to certain thickness.
30. the described method of claim 28, wherein said conductive layer forms the ball-type structure, and the part of described conductive layer is filled the sunk area in the substrate.
31. the described method of claim 28 also is included in after the described metal level of etching:
Forming cover layer on the described metal level and on the sidewall of the etching of described conductive layer and exposed portions; With
Utilize described cover layer to come the remainder of the unlapped described conductive layer of the described cover layer of etching.
32. the described method of claim 31, wherein said conductive layer comprise a kind of in doped polycrystalline silicon layer and the unadulterated polysilicon layer.
33. the described method of claim 31, wherein said cover layer comprise the layer based on nitride.
34. the described method of claim 13, wherein the described etching stopping layer of etching comprises use transformer coupled plasma (TCP) method, inductively coupled plasma (ICP) method, or magnetic intensified response ion(ic) etching (MERIE) method.
35. the described method of claim 34, wherein the described etching stopping layer of etching comprises the use plasma source, wherein applies source power and the about 40W～about 150W substrate bias power of about 300W～about 500W.
CN2007101357459A 2006-12-27 2007-08-10 Method for forming metal pattern in semiconductor device Expired - Fee Related CN101211783B (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
KR20060134344 2006-12-27
KR1020060134344 2006-12-27
KR10-2006-0134344 2006-12-27
KR10-2007-0045288 2007-05-10
KR1020070045288 2007-05-10
KR1020070045288A KR100842764B1 (en) 2006-12-27 2007-05-10 Method for forming a pattern of metal film and method for forming a gate electrode in semiconductor device

Publications (2)

Publication Number Publication Date
CN101211783A true CN101211783A (en) 2008-07-02
CN101211783B CN101211783B (en) 2010-06-16

Family

ID=39611694

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2007101357459A Expired - Fee Related CN101211783B (en) 2006-12-27 2007-08-10 Method for forming metal pattern in semiconductor device

Country Status (3)

Country Link
KR (1) KR100842764B1 (en)
CN (1) CN101211783B (en)
TW (1) TWI358773B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103794507A (en) * 2012-11-05 2014-05-14 中国科学院微电子研究所 Device isolation method in gate-last process
CN109103076A (en) * 2017-06-20 2018-12-28 英特尔公司 The method and apparatus of improved etching stopping layer or hard mask layer for memory devices

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101972159B1 (en) * 2012-08-24 2019-08-16 에스케이하이닉스 주식회사 Semiconductor device with silicon-containing hard mask and method of fabricating the same
JP5887366B2 (en) 2013-03-26 2016-03-16 東京エレクトロン株式会社 Method for etching a film containing a transition metal

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100687853B1 (en) * 2000-07-29 2007-02-27 주식회사 하이닉스반도체 Method for forming W-bit line
KR100672762B1 (en) * 2003-10-29 2007-01-22 주식회사 하이닉스반도체 Method for manufacturing semiconductor device using reverse gate process
KR100562657B1 (en) * 2004-12-29 2006-03-20 주식회사 하이닉스반도체 Recess gate and method for manufacturing semiconductor device with the same
KR20060133166A (en) * 2005-06-20 2006-12-26 삼성전자주식회사 Method of forming gate in non-volatile memory device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103794507A (en) * 2012-11-05 2014-05-14 中国科学院微电子研究所 Device isolation method in gate-last process
CN109103076A (en) * 2017-06-20 2018-12-28 英特尔公司 The method and apparatus of improved etching stopping layer or hard mask layer for memory devices

Also Published As

Publication number Publication date
TW200828447A (en) 2008-07-01
CN101211783B (en) 2010-06-16
KR100842764B1 (en) 2008-07-01
TWI358773B (en) 2012-02-21

Similar Documents

Publication Publication Date Title
JP4398467B2 (en) Manufacturing method of semiconductor device
EP1330838B1 (en) Control trimming of hard mask for transistor gate
JP5221928B2 (en) Dry etching method of polysilicon gate doped with YB
CN101335181B (en) Method for manufacturing a semiconductor device using a spacer as an etch mask
US20060017093A1 (en) Semiconductor devices with overlapping gate electrodes and methods of fabricating the same
US7572704B2 (en) Method for forming metal pattern and method for forming gate electrode in semiconductor device using the same
CN101290879B (en) Manufacturing method of gate
TWI234881B (en) Phosphoric acid free process for polysilicon gate definition
CN101211783B (en) Method for forming metal pattern in semiconductor device
US7811888B2 (en) Method for fabricating semiconductor memory device
CN102194698B (en) Method for forming semiconductor devices
US20080160698A1 (en) Method for fabricating a semiconductor device
CN100550320C (en) Make the method for semiconductor device
TW200820349A (en) Method of fabricating semiconductor device with recess gate
KR20040022996A (en) Forming method for floating gate patterns by etching with mixture of HBr and He gas and manufacturing method for FLASH memory device using the same
KR100965047B1 (en) Method for forming gate of flash memory device
CN104517887B (en) A method of making semiconductor devices
AU2001252939A1 (en) Hydrogen catalysis
WO2001070627A2 (en) Hydrogen catalysis
KR20090066405A (en) Flash device fabrication method
US20230395387A1 (en) Method for manufacturing semiconductor device
US20230395388A1 (en) Method for manufacturing semiconductor device
KR101009068B1 (en) Method of manufacturing a semiconductor device
KR100866119B1 (en) Method for forming dual gate electrode
KR100609035B1 (en) Method for fabricating gate of mos transistor in semiconductor device

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20100616

Termination date: 20130810