TWI358773B - Method for forming metal pattern and method for fo - Google Patents
Method for forming metal pattern and method for fo Download PDFInfo
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- TWI358773B TWI358773B TW096124574A TW96124574A TWI358773B TW I358773 B TWI358773 B TW I358773B TW 096124574 A TW096124574 A TW 096124574A TW 96124574 A TW96124574 A TW 96124574A TW I358773 B TWI358773 B TW I358773B
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- Prior art keywords
- layer
- hard mask
- etch stop
- forming
- metal
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- 238000000034 method Methods 0.000 title claims description 65
- 229910052751 metal Inorganic materials 0.000 title claims description 24
- 239000002184 metal Substances 0.000 title claims description 24
- 239000010410 layer Substances 0.000 claims description 142
- 238000005530 etching Methods 0.000 claims description 22
- 239000006117 anti-reflective coating Substances 0.000 claims description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 18
- 229920005591 polysilicon Polymers 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 claims description 17
- 150000004767 nitrides Chemical class 0.000 claims description 8
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 5
- 229910052799 carbon Inorganic materials 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 229910052770 Uranium Inorganic materials 0.000 claims description 4
- 238000009616 inductively coupled plasma Methods 0.000 claims description 4
- 239000004576 sand Substances 0.000 claims description 4
- JFALSRSLKYAFGM-UHFFFAOYSA-N uranium(0) Chemical compound [U] JFALSRSLKYAFGM-UHFFFAOYSA-N 0.000 claims description 4
- 238000011065 in-situ storage Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 229910052735 hafnium Inorganic materials 0.000 claims description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 2
- 238000001020 plasma etching Methods 0.000 claims description 2
- 239000007789 gas Substances 0.000 claims 6
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims 2
- 150000002431 hydrogen Chemical class 0.000 claims 2
- 229910052739 hydrogen Inorganic materials 0.000 claims 2
- 239000001257 hydrogen Substances 0.000 claims 2
- 229910052761 rare earth metal Inorganic materials 0.000 claims 2
- 150000002910 rare earth metals Chemical class 0.000 claims 2
- 229910052723 transition metal Inorganic materials 0.000 claims 2
- 150000003624 transition metals Chemical class 0.000 claims 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims 1
- 229910045601 alloy Inorganic materials 0.000 claims 1
- 239000000956 alloy Substances 0.000 claims 1
- 229910052731 fluorine Inorganic materials 0.000 claims 1
- 239000011737 fluorine Substances 0.000 claims 1
- 239000003350 kerosene Substances 0.000 claims 1
- 238000005121 nitriding Methods 0.000 claims 1
- 229910052707 ruthenium Inorganic materials 0.000 claims 1
- 229910052727 yttrium Inorganic materials 0.000 claims 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 claims 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 20
- 229910052721 tungsten Inorganic materials 0.000 description 20
- 239000010937 tungsten Substances 0.000 description 20
- 238000005336 cracking Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 238000001000 micrograph Methods 0.000 description 3
- 238000010405 reoxidation reaction Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 101100269850 Caenorhabditis elegans mask-1 gene Proteins 0.000 description 1
- 229910052684 Cerium Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000006096 absorbing agent Substances 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- GWXLDORMOJMVQZ-UHFFFAOYSA-N cerium Chemical compound [Ce] GWXLDORMOJMVQZ-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Ceramic Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
1358773 阻圖案係形成於該結果結構上方。 使用該光阻圖案作爲蝕刻遮罩而執行蝕刻製程以蝕刻 抗反射塗覆層，以形成抗反射塗覆圖案。使用此抗反射塗 覆圖案作爲蝕刻遮罩而執行另一蝕刻製程以蝕刻硬遮罩， 以形成硬遮罩圖案。該鎢係使用此硬遮罩圖案作爲飩刻遮 罩而蝕刻，以形成閘極。 然而，典型於半導體元件中形成閘極的方法一般呈現 下列限制。當形成硬遮罩圖案時，一部分鎢可能會由於含 有氮化物系層與鎢之硬遮罩之間的低選擇性而不規則地蝕 刻。因而，可能產生破裂情況。該氮化物系層與鎢之間的 低選擇性由於氮化物系層與鎢之間在蝕刻率上存有非常小 的差異故幾乎沒有選擇性。 第1與2圖說明當在半導體元件中應用典型形成閘極 之方法時，於鎢表面上產生破裂（以元件符號’A’表示）之顯 微照相圖。特別地，第1圖說明於具有圓柱桿結晶結構之 鎢表面上產生破裂。此破裂通常於具有圓柱桿結晶結構之 鎢表面上產生。 產生於鎢表面上的破裂於隨後多晶矽之蝕刻期間，導 致於多晶矽上的不規則大損害》因此，可能在周圍區域中 導致楔形損害或引起針孔。該周圍區域除了半導體元件之 記憶格的區域外，將參照特定區域形成。用以驅動記憶格 之驅動元件係於此周圍區域中形成。 第3圖說明楔形多晶矽損害之顯微照相圖（以元件符 號’B’表示）。第4圖說明產生於周圍區域中之針孔之顯微 1358773 照相圖（以元件符號’c’表示）。此多晶矽損害與針孔產生會 在隨後接觸栓形成製程期間，於接觸栓與閘極之間引起短 路。因此，產量會接著降低。第5圖說明晶圓表面上於接 觸栓與閘極之間產生短路之顯微照相圖。 【發明內容】 本發明之實施例係指出提供一種於半導體元件中形成 金屬圖案之方法，當使用硬遮罩蝕刻此金屬層時，其可藉 由降低金屬層之表面上之破裂產生而增加產量。 • · . · 本發明之其他實施例係指出提供一種於半導體元件中 形成閘極之方法，其在半導體元件中形成閘極之蝕刻製程 期間，藉由降低閘極之表面上破裂產生而增加產量。 依據本發明之一觀點，提供一種於半導體元件中形成 金屬圖案之方法，包含：於含有金屬層之半完成基板上方 形成蝕刻停止層；於蝕刻停止層上方形成硬遮罩；蝕刻硬 遮罩以形成曝露該鈾刻停止層之硬遮罩圖案；及使用硬遮 罩圖案蝕刻該蝕刻停止層與金屬層。 依據本發明之另一觀點，提供一種於半導體元件中形 成閘極之方法，包含：形成含有金屬層之結構作爲上層； 於該金屬層上方形成蝕刻停止層；於該餽刻停止層上方形 成硬遮罩；蝕刻部分硬遮罩以形成曝露此蝕刻停止層之硬 遮罩圖案及使用硬遮罩圖案蝕刻該蝕刻停止層與金屬層》 【實施方式】 本發明之實施例係關於一種於半導體元件中形成金屬 圖案之方法與形成閘極之方法。 1358773 是理想的，但因爲部分飩刻停止層14可被蝕刻而無關於該 選擇性或蝕刻停止層14與硬遮罩15之間的選擇性的限 制，故此蝕刻停止層14形成此厚度。亦即，當蝕刻硬遮罩 15考量飩刻該蝕刻停止層14時，蝕刻停止層14之厚度係 形成大約5 0A或較大的厚度。 該硬遮罩15係形成於蝕刻停止層14上方。此硬遮罩 15可包含對該蝕刻停止層14具有高選擇性之材料。例如， 當蝕刻停止層14包含一多晶矽層時，此硬遮罩15可包含 氮化物系層。詳而言之，此硬遮罩15可包含氮化矽（Si xNy) 層，其中代表矽（Si)原子比率的x以及代表氮（N)原子比率 的y係爲大於〇的自然數，其可在處理含有多晶矽層之蝕 刻停止層1 4之腔室原位中處理。例如，此硬遮罩1 5包含 氮化矽（Si3N4)。 一抗反射塗覆層16係形成於硬遮罩15上方。此抗反 射塗覆層16可包含一無機系之抗反射塗覆層或有機系之 抗反射塗覆層。例如，該無機系之抗反射塗覆層可包含一 非.結晶碳層或氮氧化矽（SiON)層。該有機系之抗反射塗覆 層16可包含由非結晶碳層與氮氧化矽層架構之堆疊結 構。此有機系之抗反射塗覆層係用以控制用在微圖案之 ArF光源的干擾。有機系材料包含可讓抗反射層具有橋結 構之變硬劑、用以於曝光光源之波長範圍中吸收光之光吸 收劑，以及熱酸產生器與作爲催化劑之有機溶劑，以活化 一橋反應。 —光阻層係形成於抗反射塗覆層16上方。使用光罩執 -10- 135^773 < 光阻圖案17下方之特定部分之抗反射塗覆層16也可被移 除。 ' 參照第6C圖，執行移除製程以移除抗反射塗覆圖案 ' 16A(第6B圖）。若剩下部分光阻圖案17，則此剩下部分可 與抗反射塗覆圖案16A —起移除。 該蝕刻停止層1 4、鎢層1 3以及多晶矽層1 2係使用硬 遮罩圖案1 5 A作爲蝕刻遮罩被蝕刻。以下列方式執行蝕刻 製程：剩餘部分多晶矽層1 2代替完全.移除多晶矽層1 2。 ® 因此，具有特定厚度之剩餘多晶矽層12A剩餘在含有除了 閘極區域以外的區域之基板10上方。元件符號13 A與14A 分別參照剩餘鎢層1 3 A以及剩餘蝕刻停止層1 4 A。 例如，該蝕刻停止層14係使用變壓耦合電漿（TCP)方 法，感應耦合電漿（ICP)方法，或磁場強化反應性離子蝕刻 (MERIE)方法，利用一電漿來源蝕刻。同樣地，可供應電源 電力範圍從約300W到約5 00W，並且偏壓電力範圍從約 4 0 W 到約 1 5 0 W。 參照第6D圖，形成剩餘覆蓋層19。詳而言之，形成 覆蓋層於結果結構之表面外形上方，以降低之後再氧化製 程期間剩餘鎢層1 3 A之二側壁之氧化。此覆蓋層可包含對 該剩餘多晶矽層1 2 A具有高選擇性之材料。例如，此覆蓋 層包含氮化系層。作爲參考，該再氧化製程參照一般執行 以補償閘極之蝕刻損失的氧化製程，亦即，於形成閘極之 蝕刻製程期間產生的閘極之側壁損失。 執行一遮罩製程與一乾蝕刻製程以蝕刻該覆蓋層。因 -12-1358773 A resist pattern is formed over the resulting structure. An etching process is performed using the photoresist pattern as an etch mask to etch the anti-reflective coating layer to form an anti-reflective coating pattern. Another etching process is performed using the anti-reflective coating pattern as an etch mask to etch the hard mask to form a hard mask pattern. The tungsten is etched using the hard mask pattern as an engraved mask to form a gate. However, the method of forming a gate typically in a semiconductor element generally exhibits the following limitations. When a hard mask pattern is formed, a portion of the tungsten may be irregularly etched due to the low selectivity between the nitride-containing layer and the hard mask of tungsten. Thus, a rupture may occur. The low selectivity between the nitride-based layer and tungsten is almost non-selective due to the very small difference in etching rate between the nitride-based layer and tungsten. Figs. 1 and 2 illustrate a micrograph showing cracking (indicated by the symbol 'A') on the surface of tungsten when a method of typically forming a gate is applied to a semiconductor element. In particular, Figure 1 illustrates the occurrence of cracks on the surface of tungsten having a cylindrical rod crystal structure. This cracking is usually produced on the surface of the tungsten having a cylindrical rod crystal structure. Irregular large damage on the polycrystalline crucible due to cracking on the surface of the tungsten during etching of the subsequent polysilicon, therefore, may cause wedge damage or pinholes in the surrounding region. The surrounding area is formed with reference to a specific area in addition to the area of the memory cell of the semiconductor element. A driving element for driving the memory cell is formed in the surrounding area. Figure 3 illustrates a photomicrograph of the damage of the wedge-shaped polysilicon (indicated by the component symbol 'B'). Figure 4 illustrates a micrograph of a pinhole produced in the surrounding area. 1358773 Photograph (indicated by the symbol 'c'). This polysilicon damage and pinhole generation can cause a short circuit between the contact plug and the gate during the subsequent contact plug formation process. Therefore, the output will then decrease. Figure 5 illustrates a photomicrograph of a short circuit on the wafer surface between the contact plug and the gate. SUMMARY OF THE INVENTION Embodiments of the present invention are directed to provide a method of forming a metal pattern in a semiconductor device, which can increase yield by reducing cracking on the surface of the metal layer when the metal layer is etched using a hard mask. . Other embodiments of the present invention are directed to providing a method of forming a gate in a semiconductor device that increases yield by reducing cracking on the surface of the gate during an etching process in which a gate is formed in the semiconductor device . According to one aspect of the present invention, a method of forming a metal pattern in a semiconductor device includes: forming an etch stop layer over a semi-finished substrate containing a metal layer; forming a hard mask over the etch stop layer; etching the hard mask to Forming a hard mask pattern exposing the uranium engraving stop layer; and etching the etch stop layer and the metal layer using a hard mask pattern. According to another aspect of the present invention, a method for forming a gate electrode in a semiconductor device includes: forming a structure including a metal layer as an upper layer; forming an etch stop layer over the metal layer; forming a hard layer above the feed stop layer a mask; etching a portion of the hard mask to form a hard mask pattern exposing the etch stop layer and etching the etch stop layer and the metal layer using a hard mask pattern. [Embodiment] Embodiments of the present invention relate to a semiconductor device A method of forming a metal pattern and a method of forming a gate. 1358773 is desirable, but because the partial etch stop layer 14 can be etched without regard to the selectivity of the selectivity or etch stop layer 14 and the hard mask 15, the etch stop layer 14 forms this thickness. That is, when etching the hard mask 15 to etch the etch stop layer 14, the thickness of the etch stop layer 14 is formed to a thickness of about 50 A or a large thickness. The hard mask 15 is formed over the etch stop layer 14. This hard mask 15 may comprise a material having high selectivity to the etch stop layer 14. For example, when the etch stop layer 14 comprises a polysilicon layer, the hard mask 15 may comprise a nitride layer. In detail, the hard mask 15 may include a tantalum nitride (Si x Ny) layer, wherein x representing a ratio of atomic ratio of germanium (Si) and a y system representing a ratio of atomic ratio of nitrogen (N) are natural numbers greater than 〇, It can be processed in situ in the chamber where the etch stop layer 14 containing the polysilicon layer is treated. For example, the hard mask 15 contains tantalum nitride (Si3N4). An anti-reflective coating layer 16 is formed over the hard mask 15. The anti-reflective coating layer 16 may comprise an inorganic anti-reflective coating or an organic anti-reflective coating. For example, the inorganic anti-reflective coating layer may comprise a non-crystalline carbon layer or a cerium oxynitride (SiON) layer. The organic anti-reflective coating layer 16 may comprise a stacked structure of a non-crystalline carbon layer and a hafnium oxynitride layer structure. The organic anti-reflective coating is used to control the interference of the ArF source used in the micropattern. The organic material comprises a hardening agent for allowing the antireflection layer to have a bridge structure, a light absorber for absorbing light in a wavelength range of the exposure light source, and a thermal acid generator and an organic solvent as a catalyst to activate a bridge reaction. A photoresist layer is formed over the anti-reflective coating layer 16. The anti-reflective coating layer 16 of a specific portion under the photoresist pattern 17 can also be removed by using a photomask -10- 135^773 < Referring to Fig. 6C, the removal process is performed to remove the anti-reflection coating pattern '16A (Fig. 6B). If a portion of the photoresist pattern 17 remains, the remaining portion can be removed together with the anti-reflection coating pattern 16A. The etch stop layer 14 , the tungsten layer 13 and the polysilicon layer 12 are etched using the hard mask pattern 15 A as an etch mask. The etching process is performed in the following manner: the remaining portion of the polysilicon layer 12 is replaced by the complete. The polysilicon layer 12 is removed. ® Therefore, the remaining polysilicon layer 12A having a specific thickness remains over the substrate 10 containing a region other than the gate region. The component symbols 13 A and 14A refer to the remaining tungsten layer 13 A and the remaining etch stop layer 1 4 A, respectively. For example, the etch stop layer 14 is etched using a plasma source using a pressure swing coupled plasma (TCP) method, an inductively coupled plasma (ICP) method, or a magnetic field enhanced reactive ion etching (MERIE) method. Similarly, the power supply can be supplied from about 300 W to about 500 W, and the bias power ranges from about 40 W to about 150 W. Referring to Figure 6D, the remaining cover layer 19 is formed. In detail, a cap layer is formed over the surface topography of the resulting structure to reduce oxidation of the sidewalls of the remaining tungsten layer 13 A during the subsequent reoxidation process. This cover layer may comprise a material having a high selectivity to the remaining polycrystalline germanium layer 1 2 A. For example, the overlay layer comprises a nitride layer. For reference, the reoxidation process refers to an oxidation process that is typically performed to compensate for the etch loss of the gate, i.e., sidewall loss of the gate generated during the etch process that forms the gate. A mask process and a dry etch process are performed to etch the cap layer. Because -12-
1358773 此’圍住該硬遮罩圖案15A並與剩餘蝕刻停止層 餘鎢層1 3 A以及剩餘多晶矽層1 2 A之二側壁接領 覆蓋層19可被形成。 參照第6E圖，使用剩餘覆蓋層19作爲蝕亥 行蝕刻製程以蝕刻剩餘多晶矽層1 2 A之曝露部女 露閘絕緣層11之部分。元件符號12B係關於一 E 之多晶矽層12B。因此，形成燈型凹槽閘極20。 依據本發明之實施例，在蝕刻含有金屬層泛 程期間，執行蝕刻製程，同時於金屬層與硬遮聋 具有高選擇性之蝕刻停止層。因此，該蝕刻停il 護層之功能，以保護該金屬層，以避免蝕刻該瑪 屬層的損失。 依據本發明之實施例，由多晶矽層與鎢層構 堆疊結構之閘極的蝕刻製程中，鎢損失可藉由應 法降低。此外，於該鎢層之表面上不會產生破裂 可降低該鎢層下方之多晶矽層的損失與針孔之 外’可減少閘極與之後發生於閘極間形成的接觸 短路。因此，可增加半導體元件之產量。 依據本發明之實施例，該金屬層之表面也巧 隨後發生的製程（例如，藉由於金屬層之已蝕刻庄 形成覆蓋層之再氧化製程）來氧化。 雖然已對特定實施例說明本發明時，其可赁 領域中具有通常知識者顯而易見的是，本發明互 變與修正而仍不脫離本發明於下述申請專利範圍 :1 4 A、剩 之該剩餘 丨障壁層執 •，致使曝 ，製成圖案 .結構的製 :之間插入 .層作爲保 丨遮罩時金 丨成之具有 :用前述方 ，並因此， 產生。此 ΐ栓之間的 「不用藉由 J表面上方 〖所屬技術 「做各種改 1中所界定 -13- 135^773 之精神與範圍。 【圖式簡單說明】 ' 第1圖說明於具有典型圓柱桿結晶結構之鎢層之表面 • 上產生破裂之顯微照相圖； 第2圖說明當於半導體元件中應用典型形成閘極的方 法時，於形成閫極之鎢層之表面上產生破裂之顯微照相圖； 第3圖說明當於半導體元件中應用典型形成閘極之方 法時產生楔形多晶矽損害之顯微照相圖； • 第4圖說明當於半導體元件中應用典型形成閘極之方 法時，於周圍區域中產生針孔之顯微照相圖； 第5圖說明當於半導體元件中應用典型形成閘極之方 法時，於接觸栓與閘極之間在晶圓表面上產生短路之顯微 照相圖； 第6A到6E圖說明依據本發之實施例於半導體元件中 形成閘極之方法之斷面示意圖。 【主要元件符號說明】 10 基板 11 閘絕緣層 12 多晶砂層 1 2A 剩餘多晶砂層 1 2B 多晶砂層 13 金屬層（鎢層） 1 3 A 剩餘鶴層 14 蝕刻停止層 -14- 1358773 1 4 A 剩 餘 蝕 刻 停 止 層 15 硬 遮 罩 1 5 A 硬 遮 罩 圖 案 16 抗 反 射 塗 覆 層 1 6A 抗 反 射 塗 覆 圖 案 17 光 阻 圖 案 18 蝕 刻 製 程 19 剩 餘 覆 蓋 層 20 燈 型 凹 槽 閘 極 A 破 裂 B 楔 形 多 晶 矽 損 害 C 針 孔1358773 This can be formed by enclosing the hard mask pattern 15A and with the remaining etch stop layer residual tungsten layer 13 A and the remaining sidewalls of the remaining polysilicon layer 1 2 A. Referring to Fig. 6E, the remaining overcoat layer 19 is used as an etching process to etch a portion of the exposed portion of the exposed polysilicon layer 1 2 A. The component symbol 12B is a polysilicon layer 12B relating to an E. Therefore, the lamp type groove gate 20 is formed. In accordance with an embodiment of the present invention, an etch stop process is performed while etching the metal containing layer process while having a high selectivity etch stop layer for the metal layer and the hard concealer. Therefore, the etch stops the function of the Shield to protect the metal layer from etching the MAS layer. According to an embodiment of the present invention, in the etching process of the gate of the polycrystalline germanium layer and the tungsten layer stacked structure, the tungsten loss can be reduced by the method. In addition, no cracking occurs on the surface of the tungsten layer to reduce the loss of the polysilicon layer under the tungsten layer and the outside of the pinhole, which can reduce the contact short circuit formed between the gate and the gate electrode. Therefore, the yield of the semiconductor element can be increased. In accordance with an embodiment of the present invention, the surface of the metal layer is also oxidized by a subsequent process (e.g., by a reoxidation process in which the metal layer has been etched to form a cap layer). While the invention has been described with respect to the specific embodiments thereof, it will be apparent to those skilled in the art of the invention that the invention may be modified and modified without departing from the scope of the invention. The remaining 丨 丨 层 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Between the ΐ ΐ 「 「 「 「 「 「 「 「 不用 不用 不用 不用 不用 不用 不用 不用 不用 不用 不用 不用 不用 不用 不用 不用 不用 -13 -13 -13 -13 -13 -13 -13 -13 -13 -13 -13 -13 -13 -13 -13 -13 -13 -13 -13 -13 The surface of the tungsten layer of the rod crystal structure • a photomicrograph showing the occurrence of cracks; Fig. 2 illustrates the occurrence of cracks on the surface of the tungsten layer forming the drain when a typical method of forming the gate is applied to the semiconductor element. Micrograph; Figure 3 illustrates a photomicrograph of wedge-shaped polysilicon damage when a typical gate formation method is applied to a semiconductor device; • Figure 4 illustrates the application of a typical gate formation method in a semiconductor device. A photomicrograph showing the occurrence of pinholes in the surrounding area; Figure 5 illustrates a photomicrograph of a short circuit on the surface of the wafer between the contact plug and the gate when a typical method of forming a gate is applied to a semiconductor device. Figure 6A to 6E are schematic cross-sectional views showing a method of forming a gate in a semiconductor device in accordance with an embodiment of the present invention. [Description of Main Components] 10 Substrate 11 Gate Insulation Layer 12 Sand layer 1 2A Residual polycrystalline sand layer 1 2B Polycrystalline sand layer 13 Metal layer (Tungsten layer) 1 3 A Remaining crane layer 14 Etching stop layer-14- 1358773 1 4 A Remaining etch stop layer 15 Hard mask 1 5 A Hard mask Pattern 16 Anti-reflective coating layer 1 6A Anti-reflection coating pattern 17 Photoresist pattern 18 Etching process 19 Remaining cover layer 20 Lamp-type groove gate A Crack B Wedge-shaped polysilicon damage C pinhole
Claims (1)
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| Application Number | Priority Date | Filing Date | Title |
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| KR20060134344 | 2006-12-27 | ||
| KR1020070045288A KR100842764B1 (en) | 2006-12-27 | 2007-05-10 | Method for forming a pattern of metal film and method for forming a gate electrode in semiconductor device |
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| TW200828447A TW200828447A (en) | 2008-07-01 |
| TWI358773B true TWI358773B (en) | 2012-02-21 |
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| KR (1) | KR100842764B1 (en) |
| CN (1) | CN101211783B (en) |
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| KR101972159B1 (en) * | 2012-08-24 | 2019-08-16 | 에스케이하이닉스 주식회사 | Semiconductor device with silicon-containing hard mask and method of fabricating the same |
| CN103794507A (en) * | 2012-11-05 | 2014-05-14 | 中国科学院微电子研究所 | Device isolation method in gate-last process |
| JP5887366B2 (en) * | 2013-03-26 | 2016-03-16 | 東京エレクトロン株式会社 | Method for etching a film containing a transition metal |
| US10304749B2 (en) * | 2017-06-20 | 2019-05-28 | Intel Corporation | Method and apparatus for improved etch stop layer or hard mask layer of a memory device |
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| KR100687853B1 (en) * | 2000-07-29 | 2007-02-27 | 주식회사 하이닉스반도체 | Method for forming W-bit line |
| KR100672762B1 (en) * | 2003-10-29 | 2007-01-22 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device using reverse gate process |
| KR100562657B1 (en) * | 2004-12-29 | 2006-03-20 | 주식회사 하이닉스반도체 | Recess gate and method for manufacturing semiconductor device with the same |
| KR20060133166A (en) * | 2005-06-20 | 2006-12-26 | 삼성전자주식회사 | Method of forming gate in non-volatile memory device |
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| CN101211783B (en) | 2010-06-16 |
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| CN101211783A (en) | 2008-07-02 |
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