CN101207098B - Soldering pad structure in semiconductor apparatus and related method - Google Patents
Soldering pad structure in semiconductor apparatus and related method Download PDFInfo
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- CN101207098B CN101207098B CN2006101712297A CN200610171229A CN101207098B CN 101207098 B CN101207098 B CN 101207098B CN 2006101712297 A CN2006101712297 A CN 2006101712297A CN 200610171229 A CN200610171229 A CN 200610171229A CN 101207098 B CN101207098 B CN 101207098B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title claims abstract description 10
- 238000005476 soldering Methods 0.000 title 1
- 238000003466 welding Methods 0.000 claims abstract description 44
- 230000006698 induction Effects 0.000 claims description 43
- 239000002184 metal Substances 0.000 claims description 43
- 239000000758 substrate Substances 0.000 claims description 42
- 238000010276 construction Methods 0.000 claims description 12
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000036039 immunity Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000000295 complement effect Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000009434 installation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H01L2924/01006—Carbon [C]
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- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/01082—Lead [Pb]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Abstract
The invention discloses a welding pad structure which is arranged in a semiconductor device, and a method which is used for forming the welding pad structure. The semiconductor device comprises a base, and the welding pad structure comprises a connecting structure and an inductance structure. The connecting structure allows a lead wire to be connected on. The inductance structure is coupled with the connecting structure, and is used for reducing the equivalent capacitance value between the lead wire and the base.
Description
Technical field
The present invention relates to the weld pad in the semiconductor device, refer to a kind of welding pad structure that reduces the equivalent capacitance value between lead-in wire and substrate especially.
Background technology
Wafer is one of element extremely common in the various now electronic installations.Generally speaking, must be provided with firm weld pad (Bonding pad) on the wafer, allow outside lead-in wire (Bonding wire) can be electrically connected to the core circuit of wafer by weld pad.Via weld pad, the core circuit in the wafer can be sent to external circuit with output signal, or receives the input signal that external circuit sends.And in the middle of known semiconductor technology,, and guarantee the reliability (Reliability) of weld pad for fear of the generation of peeling off effect (Peel-off effect), generally use a plurality of layers of metal level to be used as the primary structure of weld pad.
Yet, for known welding pad structure, all can there be parasitic capacitance (Parasitic capacitance) in per two adjacent metal interlayers, also can there be parasitic capacitance between the substrate (Substrate) of the metal level of below and wafer, on the whole, those parasitic capacitances are equivalent to lead-in wire is connected to the equivalent capacity of substrate.Owing to have equivalent capacity between lead-in wire and substrate, externally circuit transmits signals in the process of core circuit by lead-in wire and weld pad, or transmit signals to by weld pad and lead-in wire in the process of external circuit at core circuit, signal all can because of the equivalent capacity dissipation (Loss) of weld pad to substrate.In addition, the equivalent capacity of weld pad also can reduce the noise immunity (Noise immunity) of weld pad for substrate, and causes the increase of noise figure (Noise figure).These negative effects all can reduce the overall efficiency of wafer, and particularly for the wafer of high-speed applications circuit, the situation that wafer usefulness reduces can be more obvious.
Summary of the invention
Therefore, one of purpose of the present invention is to provide a kind of welding pad structure that reduces the equivalent capacitance value between lead-in wire and substrate, to solve the problem that known technology was faced.
Embodiments of the invention disclose a kind of welding pad structure that is arranged in the semiconductor device.This semiconductor device includes substrate, and this welding pad structure includes syndeton and induction structure.This syndeton allows that lead-in wire connects thereon.This induction structure be coupled in this syndeton and be arranged at this substrate and this syndeton between, in order to reduce the equivalent capacitance value between this lead-in wire and this substrate.
Description of drawings
Fig. 1,3 and 4 is the embodiment schematic diagram of welding pad structure of the present invention.
Fig. 2 is the equivalent circuit diagram of the welding pad structure of Fig. 1.
Description of reference numerals
100,300,400 semiconductor devices
110,310,410 substrates
120,320,420 welding pad structures
140,340,341,440,441,442,443 syndetons
160,360,460 induction structures
C
Pad, C
ParaEquivalent capacity
The L equivalent inductance
M3, M4, M5, M6, M7, M8 metal level
Embodiment
Fig. 1 is the schematic diagram of the welding pad structure of the embodiment of the invention.The welding pad structure 120 of present embodiment is arranged in the semiconductor device 100, is used for lead-in wire 50 core circuits (not illustrating) that are electrically connected in the semiconductor device 100.Wherein, semiconductor device 100 includes substrate 110, and 120 of welding pad structures include syndeton 140 and induction structure 160.
Syndeton 140 is used for connecting lead-in wire 50 and this core circuit, is transmitted between lead-in wire 50 and this core circuit via syndeton 140 to allow the signal of telecommunication.In the present embodiment, syndeton 140 includes three-layer metal layer M6～M8 altogether, wherein, metal level M6 and M7 by one or more guide holes (Via) interconnect, metal level M7 and M8 by one or more guide holes interconnect, metal level M8 then tolerable lead-in wire 50 be connected in its upper surface.
In addition, the space of each metal interlevel in the welding pad structure 120, and the space in each layer line coil structures in the induction structure 160 then can be filled up by dielectric material (Dielectric material).
Fig. 2 is the equivalent circuit diagram of welding pad structure 120, wherein, and C
PadFor go between 50 and metal level M5 between equivalent capacity, L is the equivalent inductance of 110 of metal level M5 and substrates, C
ParaThen be the parasitic capacitance of 110 of metal level M5 and substrates, substrate 110 in Fig. 2 with the ground connection symbolic representation.On the whole, the equivalent capacitance value C between lead-in wire 50 and the substrate 110
EffShown in following equation:
Can learn by above formula, in specific frequency range, C
EffWill be less than C
Pad, particularly exist
Situation under, C
EffWill equal zero.In other words, by between syndeton 140 and substrate 110, setting up induction structure 160, in specific frequency range, can reduce the equivalent capacitance value C between lead-in wire 50 and the substrate 110 really effectively
EffTherefore, when signal was transmitted between lead-in wire 50 and this core circuit by welding pad structure 120, the ratio that signal dissipates to substrate 110 can become lower.In addition, because in the present embodiment, has lower equivalent capacitance value C between lead-in wire 50 and the substrate 110
EffSo lead-in wire 50 noise immunities for substrate 110 (Noise immunity) can become better, therefore, the noise figure of welding pad structure 120 (Noise figure) also can be fallen lowlyer.The above welding pad structure 120 that is all present embodiment is better than known welding pad structure part.
Because in the embodiment shown in fig. 1, induction structure 160 be arranged at syndeton 140 under (that is induction structure 160 is between syndeton 140 and substrate 110, and induction structure 160 has the area that equates in fact with syndeton 140), can't cause welding pad structure 120 in semiconductor device 100, to occupy more area so set up induction structure 160.In addition, the welding pad structure 120 of present embodiment is compatible to general complementary metal oxide semiconductor (Complementary Metal OxideSemiconductor fully, CMOS) technology, the welding pad structure 120 of present embodiment can't use extra mask and technology because of the pass of setting up induction structure 160, so can't cause the increase of semiconductor device 100 on manufacturing cost.
Please note, though in the embodiment shown in fig. 1, syndeton 140 all includes the three-layer metal layer with induction structure 160, each metal level all forms square loop construction in the induction structure 160, yet, the present invention is not as limit, in other words, in the welding pad structure of other embodiment, syndeton can include one or more layers metal level, induction structure can include one or more layers metal level, then can form square or the loop construction of other shapes (for example circular, octangle ...) as for each metal level in the induction structure.In addition, in the welding pad structure of other embodiment, induction structure might not be connected to substrate by guide hole, if do not interconnect by guide hole between induction structure and substrate, still can have lower equivalent capacitance value between lead-in wire and substrate.
In addition, though form single welding pad structure 120 by the single induction structure 160 of single syndeton 140 collocation in the embodiment shown in fig. 1, yet, in other embodiments, can also be by the common single induction structure of arranging in pairs or groups of a plurality of syndetons to form single welding pad structure (this welding pad structure can connect thereon for a plurality of lead-in wires), or by the single syndeton of the common collocation of the induction structure of a plurality of mutual vicinities to form single welding pad structure, these all are the feasible practices, and the welding pad structure that forms all can allow and has lower equivalent capacitance value between lead-in wire and substrate.
For instance, in the embodiment shown in fig. 3, arrange in pairs or groups single induction structure 360 to form single welding pad structure 320 by two connecting structures 340 and 341, wherein, connecting structure 340 and 341 is used for respectively lead-in wire 51 and 52 core circuits (not illustrating) that are electrically connected in the semiconductor device 300, and different metal interlevels can not interconnect by one or more guide holes (illustrating) in connecting structure 340 and 341.Owing to include induction structure 360, lead-in wire 51 and 310 of substrates will have lower equivalent capacitance value C
Eff1, and go between 52 and 310 of substrates also can have lower equivalent capacitance value C
Eff2As in the embodiment shown in fig. 4, then by four connecting structures 440,441,442, with 443 the collocation single induction structure 460 to form single welding pad structure 420, wherein, connecting structure 440,441,442, with 443 be used for respectively lead-in wire 53,54,55, with 56 core circuits (not illustrating) that are electrically connected in the semiconductor device 400, and at connecting structure 440,441,442, in 443, different metal interlevels can not interconnect by one or more guide holes (illustrating), in addition, each metal level all forms octagonal loop construction in the induction structure 460.Owing to include induction structure 460, lead-in wire 53,54,55, and 56 and 310 of substrates can have lower equivalent capacitance value C respectively
Eff3, C
Eff4, C
Eff5, and C
Eff6
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (10)
1. welding pad structure that is arranged in the semiconductor device, this semiconductor device includes substrate, and this welding pad structure includes:
Syndeton connects thereon in order to allow lead-in wire; And
Induction structure, be coupled in this syndeton and be arranged at this substrate and this syndeton between, in order to reducing the equivalent capacitance value between this lead-in wire and this substrate, and this induction structure is directly connected in the substrate.
2. welding pad structure as claimed in claim 1, wherein the area of this induction structure equals the area of this syndeton.
3. welding pad structure as claimed in claim 1, wherein this induction structure includes a plurality of layers of metal level, and each metal level in these a plurality of layers of metal levels all forms loop construction.
4. welding pad structure as claimed in claim 3, wherein per two adjacent metal layers interconnect by guide hole in these a plurality of layers of metal levels.
5. method that on semiconductor device, forms welding pad structure, it includes:
Substrate top in this semiconductor device forms induction structure; And
Form syndeton in this induction structure top;
Wherein this induction structure and this syndeton constitute this welding pad structure, and this syndeton allows that lead-in wire connects thereon, and this induction structure is directly connected in the substrate.
6. method as claimed in claim 5, wherein the area of this induction structure equals the area of this syndeton.
7. method as claimed in claim 5, wherein this induction structure includes a plurality of layers of metal level, and each metal level in these a plurality of layers of metal levels all forms loop construction.
8. method as claimed in claim 7, wherein per two adjacent metal layers interconnect by guide hole in these a plurality of layers of metal levels.
9. welding pad structure that is arranged in the semiconductor device, this semiconductor device includes substrate, and this welding pad structure includes:
Syndeton connects thereon in order to allow lead-in wire; And
Induction structure, be coupled in this syndeton and be arranged at this substrate and this syndeton between, in order to reducing the equivalent capacitance value between this lead-in wire and this substrate,
Wherein this induction structure includes a plurality of layers of metal level, and each metal level in these a plurality of layers of metal levels all forms loop construction.
10. method that on semiconductor device, forms welding pad structure, it includes:
Substrate top in this semiconductor device forms induction structure; And
Form syndeton in this induction structure top;
Wherein this induction structure and this syndeton constitute this welding pad structure, and this syndeton allows that lead-in wire connects thereon, and this induction structure includes a plurality of layers of metal level, and each metal level in these a plurality of layers of metal levels all forms loop construction.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2006101712297A CN101207098B (en) | 2006-12-21 | 2006-12-21 | Soldering pad structure in semiconductor apparatus and related method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2006101712297A CN101207098B (en) | 2006-12-21 | 2006-12-21 | Soldering pad structure in semiconductor apparatus and related method |
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| CN101207098A CN101207098A (en) | 2008-06-25 |
| CN101207098B true CN101207098B (en) | 2010-04-14 |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5742091A (en) * | 1995-07-12 | 1998-04-21 | National Semiconductor Corporation | Semiconductor device having a passive device formed over one or more deep trenches |
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- 2006-12-21 CN CN2006101712297A patent/CN101207098B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5742091A (en) * | 1995-07-12 | 1998-04-21 | National Semiconductor Corporation | Semiconductor device having a passive device formed over one or more deep trenches |
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