CN111668193A - Integrated circuit chip with inductance coil - Google Patents
Integrated circuit chip with inductance coil Download PDFInfo
- Publication number
- CN111668193A CN111668193A CN202010398794.7A CN202010398794A CN111668193A CN 111668193 A CN111668193 A CN 111668193A CN 202010398794 A CN202010398794 A CN 202010398794A CN 111668193 A CN111668193 A CN 111668193A
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- Prior art keywords
- chip
- inductance coil
- inductor
- integrated circuit
- pad
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- 238000004804 winding Methods 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims description 27
- 229910052751 metal Inorganic materials 0.000 claims description 27
- 238000005516 engineering process Methods 0.000 abstract description 2
- 230000010354 integration Effects 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000001939 inductive effect Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/10—Inductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Coils Or Transformers For Communication (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
An integrated circuit chip with an inductance coil relates to the integrated circuit technology. The invention arranges an inductance coil and a chip bonding pad on the same basic structure body, wherein the inductance coil winding surrounds the chip bonding pad, and the chip bonding pad is positioned in the central area of the inductance coil winding. The invention has the advantages that the central area of the inductance winding is fully utilized, and the high integration and the miniaturization of the chip are facilitated.
Description
Technical Field
The present invention relates to integrated circuit technology.
Background
On-chip integrated inductors are often used in Phase Locked Loop (PLL) circuits using inductor-capacitor voltage controlled oscillators (LC VCOs), T-coil inductors in high speed signal circuits to counteract chip PAD (PAD) parasitic capacitance effects, inductors for inductive peaking techniques to increase circuit bandwidth, inductors used in radio frequency circuits, and the like.
However, the on-chip integrated inductor occupies a large chip area, so that the chip cost is increased.
In the prior art, the method is closer to the method that:
patent 1, patent application number of the people's republic of china: 201110445564.2, application publication number: CN103187926A, LC-VCO chip and its layout method, the main inventive point is to combine the filter capacitance of the inductance coil and RC filter to carry out layout, refer to FIG. 1.
Patent 2, patent application number of the people's republic of china: 200510111036.8, publication No.: CN1979852A, a layout structure for improving quality factors of inductors, the main invention is to add a substrate shielding layer between a substrate and a metal layer of an inductor layout. The invention is greatly different from the invention and is not detailed.
Other traditional chip integrated inductors and chip bonding pads are two separate layouts, and the total layout area is the sum of the two layouts.
Disclosure of Invention
The invention aims to solve the technical problem of providing an integrated circuit chip with an inductance coil, which has extremely high layout area utilization rate.
The integrated circuit chip with the inductance coil is characterized in that the inductance coil and a chip bonding pad are arranged on the same basic structure body, the inductance coil winding surrounds the chip bonding pad, and the chip bonding pad is located in the central area of the inductance coil winding.
Furthermore, the inductance coils are distributed on at least two metal layers of the basic structure body, and layer changing connection among different metal layers is achieved through conducting wires.
Furthermore, in the basic structure, at least one multiplexing metal layer is provided, the inductance coil is provided with at least two turns of coils on the same multiplexing metal layer, and adjacent turns are connected through a lead.
The invention has the advantages that the central area of the inductance winding is fully utilized, and the high integration and the miniaturization of the chip are facilitated.
Drawings
Fig. 1 is a schematic structural diagram of a first prior art.
Fig. 2 is a layout diagram of the present invention.
FIG. 3 is a layout diagram of an embodiment.
Fig. 4 is a schematic sectional view taken along line a-a of fig. 3.
Detailed Description
The present invention refers to a structure in which metal layers and insulating layers are alternately stacked as a base structure, and a pad is provided on the base structure, which is a conventional technique.
Referring to fig. 2, the inductor coil of the inductor integrated in the chip is laid around a PAD (PAD) of the chip, so as to save the chip area.
The complete rectangle in the figure is the chip pad used for the interconnection of power, ground and signal input and output between the chip (die) and the package pins. Between the chip pad and the package pin, gold wire bonding (bonding) is generally used.
The chip pad is affected by the bonding process and the like, and generally occupies a large chip area.
The inductor of the present invention is laid out around the chip pad, such as the inductor portion of fig. 2. The two ends of the inductance coil are respectively a signal P and a signal N.
The signal P and the signal N are used as two ends of the inductor and are connected to other circuit modules. I.e. the part of the inductor coil between signal P and signal N is equivalent to an inductive device.
The inductor carries out layout around the chip bonding pad, and the total layout area is slightly larger than the area of the chip bonding pad and is far smaller than the area of the discrete inductor coil and the discrete chip bonding pad.
There are a variety of shapes for the chip pad, most commonly a rectangle, as shown in FIG. 2; or 8-sided as shown in fig. 3. In addition, the shape of the film may be circular. The invention is not limited to the shape of the die pad.
The shape of the inductor coil may have various shapes, such as a rectangle as shown in fig. 2 and an 8-sided polygon as shown in fig. 3. The shape of the inductor is not limited in the invention.
The number of turns (number of turns) of the inductance coil is not limited. The inductor shown in fig. 2 has 1 turn, the inductor shown in fig. 3 has 2 turns, and the two turns of inductors can be interconnected through different metal layer-changing connecting wires.
The invention does not limit the polysilicon layer (Poly layer) or the metal layer used by the chip PAD and the inductance coil. I.e., the chip PAD and the inductor coil are constructed using any hierarchy, and shall fall within the scope of the present invention.
As an embodiment of the layout of the inductor around the chip pad, as shown in fig. 3 and 4. The chip bonding pad occupies the topmost metal to facilitate gold wire bonding. In fig. 4, the top metal layer is labeled as metal layer 4.
The inductance coil occupies the metal layer 3, and the metal layer 4 or the metal layer 2 can be used when the metal layer is replaced.
The chip bonding pad is connected to other metal layers through the through hole and then connected to the inside of the chip through the routing. In fig. 4, the traces use metal layer 1.
Two or more turns of the inductor may be provided on the same metal layer, such as metal layer 3 of fig. 4, which is referred to as a multiplexed metal layer. The same inductor may be distributed over multiple multiplexed metal layers.
In another mode, only one turn of coil is arranged on the same metal layer, and multiple metal layers realize multiple turns of coils to form an inductor.
The invention is not limited to the type of signal that the inductor surrounds the die pad. In view of the fact that mutual interference between the chip pad and the inductance signal should be minimized, the chip pad signal type surrounded by the inductance coil should be the most preferable type of the chip pad signal type, which should be the power supply pad, the ground pad, and the direct current signal pad. But does not exclude the possibility of the inductor winding surrounding other types of signal pads.
The number of the inductor coils surrounding the chip bonding pad is not limited in the invention. Fig. 2 and 3 are both the case where the inductor coil surrounds 1 chip pad. However, the situation that the layout of the larger inductance coil is performed around 2 or more than 2 chip bonding pads is not excluded.
Claims (3)
1. The integrated circuit chip with the inductance coil is characterized in that the inductance coil and a chip bonding pad are arranged on the same basic structure body, the inductance coil winding surrounds the chip bonding pad, and the chip bonding pad is located in the central area of the inductance coil winding.
2. The integrated circuit chip with inductor according to claim 1, wherein the inductor is distributed in at least two metal layers of the base structure, and the layer-change connection between different metal layers is realized by a conducting wire.
3. The integrated circuit chip with inductor according to claim 1, wherein in the base structure, there is at least one multiplexed metal layer, and the inductor has at least two turns of the same multiplexed metal layer, and adjacent turns are connected by a wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010398794.7A CN111668193A (en) | 2020-05-12 | 2020-05-12 | Integrated circuit chip with inductance coil |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010398794.7A CN111668193A (en) | 2020-05-12 | 2020-05-12 | Integrated circuit chip with inductance coil |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111668193A true CN111668193A (en) | 2020-09-15 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010398794.7A Pending CN111668193A (en) | 2020-05-12 | 2020-05-12 | Integrated circuit chip with inductance coil |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111668193A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114496979A (en) * | 2021-09-06 | 2022-05-13 | 上海芯圣电子股份有限公司 | Promote chip territory structure of LDO interference killing feature |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10154795A (en) * | 1996-11-19 | 1998-06-09 | Advanced Materials Eng Res Inc | Inductor on semiconductor chip and its manufacturing method |
| US20040155675A1 (en) * | 2003-02-07 | 2004-08-12 | Zerbe Jared L. | Input/output circuit with on-chip inductor to reduce parasitic capacitance |
| US20060151851A1 (en) * | 2005-01-13 | 2006-07-13 | International Business Machines Corporation | On-pad broadband matching network |
| JP2006245545A (en) * | 2005-02-03 | 2006-09-14 | Nec Electronics Corp | Circuit substrate and semiconductor device |
| CN1979852A (en) * | 2005-12-01 | 2007-06-13 | 上海华虹Nec电子有限公司 | Domain structure of increwing induction quality factor |
| US20080284032A1 (en) * | 2005-03-29 | 2008-11-20 | Megica Corporation | High performance system-on-chip using post passivation process |
| CN102299134A (en) * | 2011-07-22 | 2011-12-28 | 华东师范大学 | On-chip integrated inductor internally inserted with dummy metal arrays |
| US20120268229A1 (en) * | 2011-04-21 | 2012-10-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Compact Vertical Inductors Extending in Vertical Planes |
| CN103487743A (en) * | 2007-12-04 | 2014-01-01 | 瑞萨电子株式会社 | Semiconductor device |
| US20140346634A1 (en) * | 2013-05-23 | 2014-11-27 | Synopsys, Inc. | On-chip inductors with reduced area and resistance |
-
2020
- 2020-05-12 CN CN202010398794.7A patent/CN111668193A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10154795A (en) * | 1996-11-19 | 1998-06-09 | Advanced Materials Eng Res Inc | Inductor on semiconductor chip and its manufacturing method |
| US20040155675A1 (en) * | 2003-02-07 | 2004-08-12 | Zerbe Jared L. | Input/output circuit with on-chip inductor to reduce parasitic capacitance |
| US20060151851A1 (en) * | 2005-01-13 | 2006-07-13 | International Business Machines Corporation | On-pad broadband matching network |
| JP2006245545A (en) * | 2005-02-03 | 2006-09-14 | Nec Electronics Corp | Circuit substrate and semiconductor device |
| US20080284032A1 (en) * | 2005-03-29 | 2008-11-20 | Megica Corporation | High performance system-on-chip using post passivation process |
| CN1979852A (en) * | 2005-12-01 | 2007-06-13 | 上海华虹Nec电子有限公司 | Domain structure of increwing induction quality factor |
| CN103487743A (en) * | 2007-12-04 | 2014-01-01 | 瑞萨电子株式会社 | Semiconductor device |
| US20120268229A1 (en) * | 2011-04-21 | 2012-10-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Compact Vertical Inductors Extending in Vertical Planes |
| CN102299134A (en) * | 2011-07-22 | 2011-12-28 | 华东师范大学 | On-chip integrated inductor internally inserted with dummy metal arrays |
| US20140346634A1 (en) * | 2013-05-23 | 2014-11-27 | Synopsys, Inc. | On-chip inductors with reduced area and resistance |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114496979A (en) * | 2021-09-06 | 2022-05-13 | 上海芯圣电子股份有限公司 | Promote chip territory structure of LDO interference killing feature |
| CN114496979B (en) * | 2021-09-06 | 2023-05-23 | 上海芯圣电子股份有限公司 | Chip layout structure for improving LDO anti-jamming capability |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200915 |
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| RJ01 | Rejection of invention patent application after publication |