CN101202149A - On-chip laminating inductance implemented using throughhole ring and implementing method thereof - Google Patents
On-chip laminating inductance implemented using throughhole ring and implementing method thereof Download PDFInfo
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- CN101202149A CN101202149A CNA2006101195553A CN200610119555A CN101202149A CN 101202149 A CN101202149 A CN 101202149A CN A2006101195553 A CNA2006101195553 A CN A2006101195553A CN 200610119555 A CN200610119555 A CN 200610119555A CN 101202149 A CN101202149 A CN 101202149A
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- inductance coil
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- hole ring
- laminated inductor
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Abstract
The invention discloses an upper chip piled inductance realized by a through-hole ring and the realizing method thereof. The invention can reduce electric field leakage and the impact of a through-hole resistance so as to enhance the quality factor of the chip inductance. The upper chip piled inductance comprises a plurality of layers of inductance coils winded by metal strips; a plurality of strips which appear as gaps and are arranged in parallel along the metal strips, i.e. through-hole rings, are formed on each layer of the metal inductance coils, and the shape of the through-hole ring of each layer of metal inductance coils is same.
Description
Technical field
The present invention relates to a kind of and go up laminated inductor, relate in particular to a kind of laminated inductor on the sheet that the through hole ring realizes that uses.The invention still further relates to a kind of described method that goes up laminated inductor that realize.
Background technology
In order to improve the quality factor of on-chip inductor in the radio-frequency (RF) CMOS technology, laminated inductor is realized on the general employing sheet, going up laminated inductor for used in the prior art generally is to use via-hole array to realize connection between the multiple layer metal, its concrete structure is as follows: comprise that multilayer forms inductance coil by the bonding jumper coiling, all be formed with a plurality of via-hole array on every layer of metal inductance coil, its vertical view and partial enlarged drawing can be referring to Fig. 1 a and Fig. 1 b.Though this laminated inductor of the prior art can reduce the resistance of inductance, equivalence increases the thickness of metal, thereby can improve the quality factor of on-chip inductor to a certain extent, but this connected mode can cause certain electric field to leak, and has therefore influenced the quality factor of inductance.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of laminated inductor on the sheet that the through hole ring realizes that uses, and can reduce electric field and leak, and reduces the influence of the resistance of through hole, thereby improves the quality factor of on-chip inductor.The present invention also provides a kind of described method that goes up laminated inductor that realize for this reason.
For solving the problems of the technologies described above, the invention provides a kind of laminated inductor on the sheet that the through hole ring realizes that uses, comprise that multilayer forms inductance coil by the bonding jumper coiling, it is characterized in that, all be formed with the slot-shaped bar shaped of being of many parallel placements on every layer of metal inductance coil along described bonding jumper, be the through hole ring, wherein the annular of the through hole on every layer of metal inductance coil shape is identical.
The present invention also provides a kind of method that realizes described laminated inductor, may further comprise the steps: at first, use bonding jumper to form the inductance coil of top layer; Then, on this top layer inductance coil, form the first through hole ring; Then, re-use bonding jumper and form time top layer inductance coil; Subsequently, on this time top layer inductance coil, form and the second identical shaped through hole ring of the first through hole ring; Then, the rest may be inferred, up to reaching on the sheet till the needed number of metal that reaches of laminated inductor.
The present invention is owing to adopted technique scheme, has such beneficial effect, promptly by adopting the through hole ring to connect multiple layer metal, effectively overcome the big shortcoming of through hole resistance, reduce the negative mutual inductance value of electric field leakage and each metal interlevel simultaneously, thereby effectively improved the quality factor of on-chip inductor.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 a is an of the prior art schematic top plan view that goes up an embodiment of laminated inductor;
Fig. 1 b is the partial enlarged drawing of laminated inductor on the sheet shown in Fig. 1 a;
Fig. 2 is an of the present invention tangent plane schematic diagram of going up an embodiment of laminated inductor;
Fig. 3 a is an of the present invention schematic top plan view that goes up an embodiment of laminated inductor;
Fig. 3 b is described partial enlarged drawing of going up laminated inductor of Fig. 3 a.
Embodiment
Be illustrated in figure 2 as the of the present invention tangent plane schematic diagram of going up an embodiment of laminated inductor, go up laminated inductor for described and comprise that multilayer forms inductance coil by the bonding jumper coiling, all be formed with the slot-shaped bar shaped of being of many parallel placements on every layer of metal inductance coil along described bonding jumper, it is the through hole ring, wherein the annular of the through hole on every layer of metal inductance coil shape is identical, and its vertical view and partial enlarged drawing can be referring to Fig. 3 a and Fig. 3 b.So just realized the mode of the multiple layer metal in the laminated inductor on the sheet by the through hole ring is connected together, thereby effectively overcome the big shortcoming of through hole resistance, reduce the negative mutual inductance value of electric field leakage and each metal interlevel simultaneously, thereby effectively improved the quality factor of on-chip inductor.
Accordingly, realize that of the present invention method that goes up laminated inductor is as follows: at first, use bonding jumper to form the inductance coil of top layer; Then, on this top layer inductance coil, form the first through hole ring; Then, re-use bonding jumper and form time top layer inductance coil; Subsequently, on this time top layer inductance coil, form and the second identical shaped through hole ring of the first through hole ring; Then, the rest may be inferred, up to reaching on the sheet till the needed number of metal that reaches of laminated inductor.The laminated inductor of realizing by said method can be used in the technologies such as RF COMS and Bi-CMOS.
Claims (2)
1. one kind is used laminated inductor on the sheet that the through hole ring realizes, comprise that multilayer forms inductance coil by the bonding jumper coiling, it is characterized in that, all be formed with the slot-shaped bar shaped of being of many parallel placements on every layer of metal inductance coil along described bonding jumper, be the through hole ring, wherein the annular of the through hole on every layer of metal inductance coil shape is identical.
2. described implementation method that goes up laminated inductor of a claim 1 is characterized in that, may further comprise the steps: at first, use bonding jumper to form the inductance coil of top layer; Then, on this top layer inductance coil, form the first through hole ring; Then, re-use bonding jumper and form time top layer inductance coil; Subsequently, on this time top layer inductance coil, form and the second identical shaped through hole ring of the first through hole ring; Then, the rest may be inferred, up to reaching on the sheet till the needed number of metal that reaches of laminated inductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2006101195553A CN101202149B (en) | 2006-12-13 | 2006-12-13 | On-chip laminating inductance implemented using throughhole ring and implementing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2006101195553A CN101202149B (en) | 2006-12-13 | 2006-12-13 | On-chip laminating inductance implemented using throughhole ring and implementing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101202149A true CN101202149A (en) | 2008-06-18 |
| CN101202149B CN101202149B (en) | 2011-06-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2006101195553A Active CN101202149B (en) | 2006-12-13 | 2006-12-13 | On-chip laminating inductance implemented using throughhole ring and implementing method thereof |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102087910A (en) * | 2009-12-08 | 2011-06-08 | 上海华虹Nec电子有限公司 | Double-layer inductor connected in parallel by using multiple layers of metal |
| CN104246925A (en) * | 2012-02-20 | 2014-12-24 | 华为技术有限公司 | High current, low equivalent series resistance printed circuit board coil for power transfer application |
| CN104347255A (en) * | 2013-07-29 | 2015-02-11 | 三星电机株式会社 | Thin film type inductor and method of manufacturing the same |
| WO2020148630A1 (en) * | 2019-01-16 | 2020-07-23 | International Business Machines Corporation | Assembling of chips by stacking with rotation |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3800540B2 (en) * | 2003-01-31 | 2006-07-26 | Ｔｄｋ株式会社 | Inductance element manufacturing method, multilayer electronic component, multilayer electronic component module, and manufacturing method thereof |
-
2006
- 2006-12-13 CN CN2006101195553A patent/CN101202149B/en active Active
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102087910A (en) * | 2009-12-08 | 2011-06-08 | 上海华虹Nec电子有限公司 | Double-layer inductor connected in parallel by using multiple layers of metal |
| CN104246925A (en) * | 2012-02-20 | 2014-12-24 | 华为技术有限公司 | High current, low equivalent series resistance printed circuit board coil for power transfer application |
| US9818527B2 (en) | 2012-02-20 | 2017-11-14 | Futurewei Technologies, Inc. | High current, low equivalent series resistance printed circuit board coil for power transfer application |
| US9837201B2 (en) | 2012-02-20 | 2017-12-05 | Futurewei Technologies, Inc. | High current, low equivalent series resistance printed circuit board coil for power transfer application |
| US10431372B2 (en) | 2012-02-20 | 2019-10-01 | Futurewei Technologies, Inc. | High current, low equivalent series resistance printed circuit board coil for power transfer application |
| US11120937B2 (en) | 2012-02-20 | 2021-09-14 | Futurewei Technologies, Inc. | High current, low equivalent series resistance printed circuit board coil for power transfer application |
| US11538622B2 (en) | 2012-02-20 | 2022-12-27 | Futurewei Technologies, Inc. | High current, low equivalent series resistance printed circuit board coil for power transfer application |
| CN104347255A (en) * | 2013-07-29 | 2015-02-11 | 三星电机株式会社 | Thin film type inductor and method of manufacturing the same |
| WO2020148630A1 (en) * | 2019-01-16 | 2020-07-23 | International Business Machines Corporation | Assembling of chips by stacking with rotation |
| US10991685B2 (en) | 2019-01-16 | 2021-04-27 | International Business Machines Corporation | Assembling of chips by stacking with rotation |
| GB2595097A (en) * | 2019-01-16 | 2021-11-17 | Ibm | Assembling of chips by stacking with rotation |
| GB2595097B (en) * | 2019-01-16 | 2022-11-02 | Ibm | Assembling of chips by stacking with rotation |
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| Publication number | Publication date |
|---|---|
| CN101202149B (en) | 2011-06-01 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20131216 |
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Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
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Effective date of registration: 20131216 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |