CN101197280A - Forming method of metal silicide - Google Patents
Forming method of metal silicide Download PDFInfo
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- CN101197280A CN101197280A CNA2006101190507A CN200610119050A CN101197280A CN 101197280 A CN101197280 A CN 101197280A CN A2006101190507 A CNA2006101190507 A CN A2006101190507A CN 200610119050 A CN200610119050 A CN 200610119050A CN 101197280 A CN101197280 A CN 101197280A
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Abstract
The invention discloses a forming method for metal silicide, which comprises the following steps of: providing a substrate with the surface having silicon material; forming a metal layer on the substrate; performing the first heat annealing treatment for the substrate; removing the unreacted metal layer on the substrate; forming a stress layer on the substrate; performing the second heat annealing treatment for the substrate. The forming method for metal silicide in the invention forms a low-resistance metal silicide with smooth surface and regular shape by adding the stress layer, thus improving the performance of the device and enhancing the final product rate of products.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of formation method of metal silicide.
Background technology
In the semiconductor fabrication process, often utilize the metal silicide technology to form the internal electrical tie point of low-resistance on the silicon materials surface.So-called metal silicide technology, be a kind of can closing of deposition with silication, but the metal that can not react with other materials, as cobalt (Co), nickel (Ni) or titanium (Ti) etc., utilize thermal anneal process that this metal level and silicon are fully reacted again, generate the CoSi of low-resistivity
2, NiSi or TiSi
2Deng silicide, to improve the technology of device electrical performance.
With the MOS element manufacturing is example, and the formation method of existing metal silicide is described.Figure 1A to 1E is the formation method schematic diagram of existing metal silicide, and Fig. 2 is the flow chart of existing metal silicide formation method, simply introduces the formation method of existing metal silicide and the problem of existence thereof below in conjunction with Figure 1A to 1E and Fig. 2.
At first, provide a substrate (S201), formed grid and source/drain region usually on it.Figure 1A shown in Figure 1A, has deposited pad silicon oxide layer 103 (Pad Oxide) for the device profile schematic diagram behind formation source/drain region on silicon substrate 101, and substrate is carried out etching fill, and forms isolated groove 102 between each device; Deposit spathic silicon then, etching forms grid 104; Then on each gate lateral wall, formed gate lateral wall layer 105, realized good protection polysilicon gate.Next, be mask with grid and side wall layer, in mode formation source/ drain doping region 107 and 108 between grid of injecting with ion on the substrate.
Then, deposition forms metal level (S202) on this substrate, and Figure 1B is the device profile schematic diagram behind the depositing metal layers, shown in Figure 1B, form metal silicide, needs earlier refractory metal 110 to be deposited on the silicon chip, as cobalt (Co), nickel (Ni) etc.
Then, carry out the thermal anneal process first time (S203), in order to form metal silicide, need carry out The high temperature anneal, but along with development of integrated circuits, the reducing of device size requires the thickness of the metal silicide that forms can not be too thick.For this reason, adopt twice annealed method to form metal silicide now usually.Fig. 1 C is the device profile schematic diagram after the thermal anneal process first time, shown in Fig. 1 C, is not silicon materials on the surface, is the gate lateral wall layer of silica as the surface, and metal 110 can not react, and can not form metal silicide.On the surface is the zone of silicon materials, and the temperature of thermal annealing is selected lowlyer because of the first time, and the time is also shorter, has only part to form metal silicide 120 with the silicon adjacent metal after the feasible annealing, fails to react with silicon and still have part metals 110 topmost.In addition, because the temperature of selecting for use is lower, the metal silicide that produces in the thermal annealing also is a kind of excessive attitude product of high resistant usually for the first time, as CoSi, Ni
2Si etc.
For the first time behind the thermal annealing, wet etching is removed the metal (S204) that does not react, Fig. 1 D is the device profile schematic diagram after corroding, shown in Fig. 1 D, method by selective wet etching is removed the metal level 110 that does not react, only stay metal silicide 120, form self aligned metal suicide structure at substrate surface.
Then, carry out the thermal anneal process second time (S205),, need carry out thermal anneal process to substrate once more for the metal silicide of the high resistant that form behind the thermal annealing for the first time is converted into the metal silicide of low-resistance.Fig. 1 E is the device profile schematic diagram after the thermal anneal process second time, and shown in Fig. 1 E, the temperature of annealing can be higher than primary annealing temperature usually for the second time, after the annealing, can form the metal silicide 130 of low-resistance, as CoSi
2, NiSi etc., formation to electrically contact quality better.But, find in the actual production, in second time during annealing in process, the silicide meeting regrowth (re-grow) of the high resistant of one side annealing back formation for the first time forms bigger crystal grain, and phenomenon (agglomeration) occurs condensing, on the other hand, because of the wafer behind the growing metal shows as tensile stress, can promote metal further to spread in the thermal annealing in the second time, the consequence that the problem of above-mentioned two aspects is brought has:
1, the phenomenon of condensing causes very coarse, the out-of-flatness in metal silicide surface that forms, has reduced the quality that electrically contacts of metal silicide;
2, the out-of-flatness meeting on metal silicide surface has influence on normally carrying out of subsequent technique;
3, the device inside metal silicide condenses and spreads, can make the edge of silicide that irregular extension takes place, influence the performance of device, can cause that as the length of device grids so the variation that takes place the device performance parameter takes place by corresponding the variation, can cause the increase of device creepage in the time of seriously;
4, the further diffusion of metal silicide has reduced the dynamic area that device can be used, and this is particularly unfavorable to shallow-junction devices.
Along with developing rapidly of very lagre scale integrated circuit (VLSIC), the integrated level of chip is more and more higher, and the size of components and parts is more and more littler, and the above-mentioned problem that occurs after the secondary thermal anneal process that metal silicide is carried out is also more and more obvious to the influence of device.At present, how to avoid the problem that occurs behind the above-mentioned secondary thermal annealing, become one of the emphasis problem that to pay close attention in the metal silicide production technology.
Application number is the manufacture method that 02118617.0 Chinese patent discloses a kind of metal silicide, this method has added a step ion implantation technology between the annealing in process in the first time annealing in process and the second time, with reduce the second time during thermal anneal process because the problem that the device dynamic district that the downward diffusion of metal causes reduces, but this method can not solve the other problems that produces after the above-mentioned secondary thermal anneal process, as coarse, the out-of-flatness of suicide surfaces and the problems such as irregular extension at edge.
Summary of the invention
The invention provides a kind of formation method of metal silicide, to improve problems such as the existing metal silicide rough surface that behind the secondary thermal annealing, occurs, the irregular extension of out-of-flatness and edge.
The formation method of a kind of metal silicide provided by the invention comprises step:
The substrate of one surperficial material is provided;
On described substrate, form a metal level;
Described substrate is carried out the thermal anneal process first time;
Remove unreacted metal layer on the described substrate;
On described substrate, form a stressor layers;
Described substrate is carried out the thermal anneal process second time.
Wherein, described metal level is nickel or cobalt layer, and described stressor layers is the TiN layer, and described TiN layer thickness is 100 to 400
Between.
Wherein, described stressor layers is formed by the method for chemical vapour deposition (CVD) or physical vapour deposition (PVD).
Wherein, after described substrate is carried out the thermal anneal process second time, remove the described stressor layers on the described substrate.
Wherein, described first time thermal annealing treatment temperature between 250 ℃ to 300 ℃, the processing time is between 10 to 30 seconds.
Wherein, described second time thermal annealing treatment temperature between 350 ℃ to 450 ℃, the processing time is between 10 to 30 seconds.
Compared with prior art, the present invention has the following advantages:
Metal silicide formation method of the present invention, after wet etching is removed unreacted metal, for the second time before the thermal anneal process, one deck stressor layers of having grown, the existence of this stressor layers can prevent the metal silicide phenomenon of condensing in the thermal anneal process in the second time on the one hand, improve its thermal stability, on the other hand, wafer state can also be adjusted into compression by tensile stress, suppress the further diffusion of metal, not only can improve the surface roughness of metal silicide, evenness and regular edges can also prevent the minimizing in the device dynamic district that the further extension because of metal silicide causes and the change of device performance.Metal silicide formation method of the present invention can be improved the formation quality of metal silicide, improves the performance of device and the rate of finished products of product.
Description of drawings
Figure 1A to 1E is the formation method schematic diagram of existing metal silicide;
Fig. 2 is the flow chart of existing metal silicide formation method;
Fig. 3 A to 3G is the formation method schematic diagram of metal silicide of the present invention;
Fig. 4 is the flow chart of metal silicide formation method of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Processing method of the present invention can be widely applied in many application; and can utilize many suitable material; be to be illustrated below by preferred embodiment; certainly the present invention is not limited to this specific embodiment, and the known general replacement of one of ordinary skilled in the art is encompassed in protection scope of the present invention far and away.
Secondly, the present invention utilizes schematic diagram to describe in detail, when the embodiment of the invention is described in detail in detail, for convenience of explanation, the profile of expression device architecture can be disobeyed general ratio and be done local the amplification, should be with this as limitation of the invention, in addition, in the making of reality, should comprise the three dimensions size of length, width and the degree of depth.
Metal silicide formation method of the present invention, at first utilize the method for physical vapour deposition (PVD) or chemical vapour deposition (CVD) to have deposition layer of metal layer on the substrate of silicon materials on the surface, (, generally adopt the cobalt metal for 0.18 micron following technology, for the following technology of 65nm, generally adopt the nickel metal); Then, it is carried out the thermal anneal process first time, the treatment temperature of this time thermal annealing is lower, and the processing time is also shorter, only can form limited metal silicide layer, can prevent to generate blocked up silicide layer.In addition, after this step annealing was handled, a kind of often excessive attitude of the silicide of formation showed as the characteristic of high resistant.Then, the corrosion of metals that substrate surface is not reacted is removed, and comprises the metal that is grown on the zone that substrate surface is not silicon materials, though and be grown on the zone that substrate surface is silicon materials, fail the upper strata metal that reacts with silicon.Follow again, the formation method of metal silicide of the present invention, increased the step of one step growth stressor layers, this stressor layers can prevent that not only metal silicide from condensing in the thermal anneal process in the second time of back, improve the thermal stability of silicide, wafer state can also be adjusted into compression by tensile stress, play the further effect of diffusion of metal that suppresses.Then, the substrate that the surface is covered with stressor layers carries out the thermal anneal process second time, because the existence of this stressor layers, for the second time in the thermal anneal process process, when the excessive attitude metal silicide with high resistant is converted into the stable silicide of low-resistance, the phenomenon that the silicide regions that also can not occur causing because of metal diffusing enlarges the rough surface that causes because of condensing, irregular phenomenon can not appear,, improved the performance of device, can be significantly improved as the leakage current of device.
Fig. 3 A to 3G is the formation method schematic diagram of metal silicide of the present invention, and Fig. 4 is the flow chart of metal silicide formation method of the present invention, below in conjunction with Fig. 3 A to 3G and Fig. 4 a specific embodiment of the present invention is described in detail.
At first, provide the substrate (S401) of a surperficial material, metal silicide is the formation that reacts of metal and silicon materials, and therefore, silicon materials need be contained in some zone of the substrate surface that is provided, just may form metal silicide.The most typical application of metal silicide is in the MOS element manufacturing, forms metal silicide at top portions of gates, source/leakage doped region with self-aligned manner.Present embodiment just with the example that forms of self-aligned metal silicate commonly used in the MOS device fabrication processes, is introduced metal silicide formation method of the present invention.Fig. 3 A is the device profile schematic diagram after formation source/drain doping region, as shown in Figure 3A, have a plurality of MOS device architectures on the silicon substrate 101, utilize isolated groove 102 to isolate between each device, each device has a polysilicon gate 104, this grid below is pad silicon oxide layer 103 (Pad Oxide), and has formed gate lateral wall layer 105 on each gate lateral wall, and it can form the good protection to polysilicon gate; In addition, in the grid both sides of each device, be mask with grid structure and side wall layer, between grid, formed source/ drain doping region 107 and 108 in the mode of injecting with ion on the substrate.
Then, deposition layer of metal layer (S402) on substrate, Fig. 3 B is the device profile schematic diagram behind the depositing metal layers, shown in Fig. 3 B, form silicide, usually need earlier refractory metal 110 to be deposited on the silicon chip, the manufacture craft in the present embodiment is below the 65nm, so the metal level that adopts is nickel (Ni) layer.This Ni layer 110 can utilize the method for physical vapour deposition (PVD) to form, and thickness can be 50 to 200
Between, as be 100
, the temperature of its growth usually can be at room temperature.
Then, carry out the thermal anneal process first time (S403), to form the less metal silicide of thickness.For the 65nm device, require the thickness of the metal silicide of formation to be less than 200 at least
, blocked up for the silicide layer that prevents to form, adopted the method for substrate being carried out twice thermal anneal process.Fig. 3 C is the device profile schematic diagram after the thermal anneal process first time, shown in Fig. 3 C, after this one-step rapid thermal anneal is handled, formed metal silicide 120 at silicon materials and Ni metal level 110 contacted zones, and other zones on substrate, as the surface is on the side wall layer of silica, and metal can not react, and can not form the Ni silicide.Wherein, the temperature of thermal anneal process is selected lowlyer because of the first time, usually between 200 ℃ to 300 ℃, as is 250 ℃; Time is also shorter, only there are 10 to 30 seconds, as it is time of 20 seconds, have only part and contacted Ni metal of silicon materials and silicon to react after this annealing and form Ni silicide 120, and the top of metal level 110 still can not react with silicon by reserve part Ni metal 110, guaranteed that the metal silicide layer that forms is thinner.In addition, note that because the temperature of selecting for use is lower, the metal silicide that produces in the thermal annealing is generally a kind of excessive attitude product of high resistant for the first time, as Ni
2Si.
For the first time after the thermal anneal process, wet etching is removed the metal (S404) that does not react, Fig. 3 D is the device profile schematic diagram behind the wet etching, shown in Fig. 3 D, method by selective wet etching is removed the Ni metal level 110 that does not react, only stay the surface and reacted the high resistant Ni silicide 120 of formation, so just the top portions of gates on substrate and source/drain region have formed the self aligned metal suicide structure of thinner thickness.
Metal silicide production method before this step is identical with existing silicide manufacture method, in order to solve problems such as metal silicide rough surface that existing method forms, the irregular extension of out-of-flatness and edge, manufacture method of the present invention has increased the step of one step growth stressor layers behind this step wet corrosion technique.
Behind the wet etching, in substrate surface deposition one deck stressor layers (S405), Fig. 3 E is the device profile schematic diagram after the formation stressor layers, shown in Fig. 3 E, method with chemical vapour deposition (CVD) or physical vapour deposition (PVD) has formed one deck stressor layers 301 at substrate surface, this layer can be adjusted into compressive stress state by the tensile stress state with wafer, thereby can suppress the diffusion of Ni metal.In the present embodiment, this stressor layers is to utilize the TiN layer of the method formation of chemical vapour deposition (CVD), and its thickness can be arranged on 100 to 400
Between, as be 200
Process conditions when the adjustment of this stressor layers stress intensity can deposit by change realize that this method of adjustment is that those of ordinary skill in the art is known, does not repeat them here.
In the present embodiment, be the method deposition stressor layers of utilizing chemical vapour deposition (CVD), in other embodiments of the invention, can also utilize additive method formation stressor layers such as physical vapour deposition (PVD).
Behind the deposition stressor layers TiN, carry out thermal anneal process second time (S406), this thermal anneal process is carried out for the stable metal silicide that the metal silicide of the excessive attitude of the high resistant that will form behind the thermal annealing first time is converted into low-resistance.Fig. 3 F is the device profile schematic diagram behind the thermal annealing second time, and shown in Fig. 3 F, after the annealing in process, originally the excessive attitude silicide 120 of high resistant has been transformed into the NiSi silicide 310 of low-resistance, has improved the electrical property of device for the second time.The treatment temperature that this thermal anneal process adopts compares the higher of the annealing process first time; but consider if treatment temperature is too high or the processing time is oversize; heat budget to device is unfavorable; usually the treatment temperature of this step process can be arranged between 350 ℃ to 450 ℃; as it is 400 ℃; the time of handling is between 10 to 30 seconds; as it is 20 seconds; notice; because the existence of stressor layers 301, behind this step annealing, condense phenomenon and diffusion phenomena do not appear in the low resistance silicide 310 of formation; keep the even curface after the thermal anneal process for the first time and the edge of rule, also just avoided a series of problems that cause with diffusion phenomena because of condensing.
For the second time after the annealing, utilize the method for selective wet etching that stressor layers is removed (S407) again, Fig. 3 G is for removing the device profile schematic diagram after the stressor layers, shown in Fig. 3 G, is the carrying out of the subsequent technique that do not influence device, after double annealing is finished, this stressor layers can be removed, final only in the formation surfacing of the corresponding position of device, smooth, the low-resistance Ni silicide 310 of regular shape, and do not influence other structures of device.
The formation method of metal silicide of the present invention has improved the thermal stability of metal silicide, has formed in apparent good order and condition, regular shape, electric contact area that size is suitable, has improved the performance of device, has improved the rate of finished products of product.
In the present embodiment, what form is the Ni silicide that is formed by the Ni metal level that is generally used for the following technology of 65nm, in other embodiments of the invention, formation method of the present invention can also be applied to make utilizes Ti, Ti silicide and Co silicide that metals such as Co form, its concrete processing step and implementation method are similar to above-mentioned formation Ni silicide, just the temperature of twice thermal annealing will slightly adjust according to the difference of the metal level that adopts, as when adopting metal Co, used annealing temperature can be omited height, these adjustment are conspicuous for the ordinary skill in the art, do not repeat them here.
In the present embodiment, the stressor layers of employing is the TiN layer, and in other embodiments of the invention, this stressor layers can also adopt other dielectric layers that can cause compression, as the SiN layer, and SiON layer or SiO
2Layer etc.
What describe in the present embodiment is that contact electrode on the silicon chip with MOS structure is sentenced the method that self-aligned manner forms metal silicide, in other embodiments of the invention, can also utilize method of the present invention to have and form high-quality metal silicide on the substrate slice of silicon materials on any surface.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (10)
1. the formation method of a metal silicide comprises step:
The substrate of one surperficial material is provided;
On described substrate, form a metal level;
Described substrate is carried out the thermal anneal process first time;
Remove unreacted metal layer on the described substrate;
On described substrate, form a stressor layers;
Described substrate is carried out the thermal anneal process second time.
2. formation method as claimed in claim 1 is characterized in that: described metal level is nickel or cobalt layer.
3. formation method as claimed in claim 1 is characterized in that: described stressor layers is the TiN layer.
4. formation method as claimed in claim 3 is characterized in that: described TiN layer thickness 100 to
Between.
5. formation method as claimed in claim 1 is characterized in that: described stressor layers is formed by the method for chemical vapour deposition (CVD) or physical vapour deposition (PVD).
6. formation method as claimed in claim 1 is characterized in that: after described substrate is carried out the thermal anneal process second time, remove the described stressor layers on the described substrate.
7. formation method as claimed in claim 1 is characterized in that: described first time thermal annealing treatment temperature between 250 ℃ to 300 ℃.
8. formation method as claimed in claim 1 is characterized in that: described first time thermal annealing processing time between 10 to 30 seconds.
9. formation method as claimed in claim 1 is characterized in that: described second time thermal annealing treatment temperature between 350 ℃ to 450 ℃.
10. formation method as claimed in claim 1 is characterized in that: described second time thermal annealing processing time between 10 to 30 seconds.
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| CN2006101190507A CN101197280B (en) | 2006-12-04 | 2006-12-04 | Forming method of metal silicide |
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|---|---|---|---|
| CN2006101190507A CN101197280B (en) | 2006-12-04 | 2006-12-04 | Forming method of metal silicide |
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| CN101197280B CN101197280B (en) | 2010-06-16 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102634753A (en) * | 2011-02-12 | 2012-08-15 | 深圳职业技术学院 | Hard coating and preparation method thereof |
| CN103035497A (en) * | 2011-09-29 | 2013-04-10 | 中芯国际集成电路制造(上海)有限公司 | Nickel silicide forming method and transistor forming method |
| CN104900516A (en) * | 2015-06-29 | 2015-09-09 | 上海华力微电子有限公司 | Method for forming nickel silicide |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100577020B1 (en) * | 2004-04-09 | 2006-05-10 | 매그나칩 반도체 유한회사 | Forming method of semiconductor device for improvement of removing residu and thermal stability |
| CN1700478A (en) * | 2004-05-17 | 2005-11-23 | 富士通株式会社 | Semiconductor device and method for manufacturing same |
-
2006
- 2006-12-04 CN CN2006101190507A patent/CN101197280B/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102634753A (en) * | 2011-02-12 | 2012-08-15 | 深圳职业技术学院 | Hard coating and preparation method thereof |
| CN103035497A (en) * | 2011-09-29 | 2013-04-10 | 中芯国际集成电路制造(上海)有限公司 | Nickel silicide forming method and transistor forming method |
| CN103035497B (en) * | 2011-09-29 | 2016-01-06 | 中芯国际集成电路制造(上海)有限公司 | Nickel silicide formation method and Transistor forming method |
| CN104900516A (en) * | 2015-06-29 | 2015-09-09 | 上海华力微电子有限公司 | Method for forming nickel silicide |
| CN104900516B (en) * | 2015-06-29 | 2018-01-26 | 上海华力微电子有限公司 | A kind of forming method of nickel silicide |
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