CN101196951A - Circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method - Google Patents
Circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method Download PDFInfo
- Publication number
- CN101196951A CN101196951A CNA2007101668439A CN200710166843A CN101196951A CN 101196951 A CN101196951 A CN 101196951A CN A2007101668439 A CNA2007101668439 A CN A2007101668439A CN 200710166843 A CN200710166843 A CN 200710166843A CN 101196951 A CN101196951 A CN 101196951A
- Authority
- CN
- China
- Prior art keywords
- pin
- fpga
- information
- pld
- design
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention provides a circuit-design supporting device and a method, as well as a computer product and a method for producing a printed circuit board. The method comprises the step of searching the FPGA-information such as pin-assignment information and attribute information that is created by an FPGA-designing CAD apparatus from a FPGA-information managing unit included in a circuit-designing CAD apparatus. When performing a DRC, as for in an FPGA, a DRC unit checks the attribute of a pin and the like by referring to the FPGA information that is retrieved from the FPGA-designing CAD apparatus and stored in a FPGA-information storing unit by the FPGA-information managing unit.
Description
Technical field
The present invention relates to a kind of technology of design being supported programmable logic device (PLD) (PLD) as the circuit of parts (support).
Background technology
Traditional circuit Design CAD device carries out DRC by the reference cell storehouse to the circuit diagram by the circuit designers design.In this case, as DRC, for example described following inspection: the I/O attribute checks that it checks with respect to the I/O attribute of each gauze (net) whether the quantity of output pin is 1 by using each pin; Differential wave checks it is used for checking whether all pins that are included in a gauze have identical differential attribute; And the supply voltage inspection, it is used to check whether the magnitude of voltage of power pin is identical with the supply voltage of gauze.
In addition, the flat 4-246778 of Japanese Patent Application Laid-Open discloses a kind of like this technology, in the time will arranging the I/O pin of SIC (semiconductor integrated circuit), after use logical connection information, packaging information and library information have carried out physical examination and electric checking, arrange these I/O pins.
Yet, when the circuit design supportive device to will carry out DRC as the circuit diagram of parts the time such as the PLD of FPGA (field programmable gate array), be not registered in the part library of power supply road design support apparatus reference about the accurate information of PLD.Therefore, can't carry out DRC exactly.
That is, in part library, the pin attribute of PLD (I/O attribute, differential attribute, supply voltage etc.) is not the attribute that obtains after write-in program.Therefore, can't carry out the inspection of I/O attribute, differential wave inspection and supply voltage inspection.
Summary of the invention
The objective of the invention is to solve at least in part the problem in the conventional art.
According to an aspect of the present invention, a kind of circuit design supportive device is provided, this circuit design supportive device support design is with the circuit of PLD as parts, this circuit design supportive device comprises: the PLD information receiving unit, it receives PLD information, and this PLD information is the design information of using the PLD Design CAD to create by at PLD; With the DRC unit, it is by using described PLD information and executing DRC.
According to a further aspect in the invention, provide a kind of method as the circuit of parts with PLD of supporting to design, this method may further comprise the steps: receive PLD information, this PLD information is the design information of using the PLD Design CAD to create by at PLD; And by using described PLD information and executing DRC.
According to another aspect of the invention, a kind of manufacture method of printed circuit board (PCB) is provided, this method is supported to design PLD is adopted as the circuit design supportive device of the circuit of parts, said method comprising the steps of: receive PLD information, this PLD information is the design information of using the PLD Design CAD to create by at PLD; And by using described PLD information and executing DRC.
In accordance with a further aspect of the present invention, provide a kind of computer readable recording medium storing program for performing, this computer readable recording medium storing program for performing stores therein and makes computing machine carry out the computer program of above method.
Read following detailed description in conjunction with the drawings, will be better understood above and other purpose of the present invention, feature, advantage and technology and industrial significance presently preferred embodiments of the invention.
Description of drawings
Fig. 1 is the key diagram that is used to explain according to the notion of the FPGA coordinate design of first embodiment of the invention;
Fig. 2 is the functional block diagram according to the FPGA coordinate design system of first embodiment;
Fig. 3 is the key diagram that is used for the rendering circuit design;
Fig. 4 A and Fig. 4 B are the key diagrams that is used to explain the symbolic library of FPGA;
Fig. 5 is the figure that is stored in the example of the FPGA information in the FPGA information memory cell;
Fig. 6 is the figure that is stored in the example of the symbolic library in the symbolic library storage unit;
Fig. 7 is the figure of the example of pin exchange;
How Fig. 8 exchanges the figure that is reflected in the example in the circuit diagram with pin;
Fig. 9 is the figure that is stored in the example of the constraint condition in the constraint condition storage unit;
Figure 10 is the figure that is stored in the example that changes the change history in the history storage unit;
Figure 11 is the figure of example that is outputed to the announcement information of FPGA Design CAD device by historical output unit;
Figure 12 is the figure of the output format of announcement information;
Figure 13 is processing of being carried out by circuit design CAD device that is used for the Create Symbol storehouse and the process flow diagram that is used for the processing of cloth set symbol;
Figure 14 is a process flow diagram of being checked the processing of I/O attribute by DRC unit being used to of carrying out;
Figure 15 is a process flow diagram of being checked the processing of differential wave by DRC unit being used to of carrying out;
Figure 16 is a process flow diagram of being checked the processing of supply voltage by DRC unit being used to of carrying out;
Figure 17 is the process flow diagram of being handled by the pin exchange that the pin switch processing unit is carried out;
Figure 18 is the process flow diagram of being carried out by historical output unit that is used to export the processing that changes history;
Figure 19 is the key diagram that is used to explain according to the notion of the FPGA coordinate design of second embodiment of the invention;
Figure 20 is the functional block diagram according to the FPGA coordinate design system of second embodiment;
Figure 21 is the figure of the example of the gauze tabulation of being obtained by gauze tabulation acquiring unit;
Figure 22 is the figure by the example of the gauze tabulation of gauze tabulation converting unit output;
Figure 23 is the figure by the example of the temporary library of temporary library creating unit establishment;
Figure 24 is the process flow diagram that is used for the information processing of package design CAD by the output that the temporary library creation apparatus is carried out;
Figure 25 is the process flow diagram of processing that is reflected the consideration result of encapsulation by temporary library creation apparatus being used to of carrying out; And
Figure 26 is the functional block diagram of execution according to the computing machine of the circuit design CAD program of first embodiment.
Embodiment
Explain according to an illustrative embodiment of the invention in detail with reference to the accompanying drawings.In addition, the main situation that applies the present invention to FPGA of explaining in these embodiments.
At first, the notion to the FPGA coordinate design of first embodiment of the invention makes an explanation.Fig. 1 is the key diagram that is used to explain according to the notion of the FPGA coordinate design of first embodiment.As shown in the drawing, in FPGA coordinate design according to first embodiment, be used to support the FPGA design FPGA Design CAD device 10, be used for printed circuit holding package design package design CAD device 20 and cooperate each other to support the deviser as the circuit design CAD device 100 of the circuit design supportive device of supporting circuit design.
Specifically, circuit design CAD device 100 receives the FPGA information of being created by FPGA Design CAD device 10 such as the pin layout, and the Create Symbol storehouse.When creating the symbolic library of FPGA, if the FPGA in Create Symbol storehouse is disposed in the circuit diagram, promptly, if because the change of FPGA and newly created symbolic library, then circuit design CAD device 100 utilizes as much as possible such as part and distributes and the information about having symbol now of the layout of symbol pin is come the Create Symbol storehouse.
As mentioned above, circuit design CAD device 100 is by the symbolic library of use FPGA information creating FPGA, thereby circuit designers does not need to create the symbolic library of FPGA.Therefore, can reduce the workload of circuit designers.In addition, when because when the change of FPGA and new Create Symbol storehouse, circuit design CAD device 100 utilizes as much as possible about the information of existing symbol and comes the Create Symbol storehouse.Therefore, change can be reduced, and the efficient of circuit design can be improved thus circuit diagram.
In addition, when carrying out DRC (DRC), circuit design CAD device 100 is by carrying out DRC with reference to the FPGA information of being created by FPGA Design CAD device 10 such as pin I/O attribute.For example, circuit design CAD device 100 is checked the quantity of output pin at the pin I/O attribute of each gauze by reference FPGA.Like this, circuit design CAD device 100 is carried out DRC by reference such as the FPGA information of pin I/O attribute, and can carry out DRC more accurately thus.
In addition, when the pin exchange took place in package design, circuit design CAD device 100 obtained the pin exchange message from package design CAD device 20, and the pin exchange is reflected in symbolic library, the circuit diagram etc.In addition, circuit design CAD device 100 exchanges the pin in the package design in the constraint condition that is reflected in such as the line length between the pin.Like this, circuit design CAD device 100 also is reflected in the exchange of the pin in the package design in the constraint condition, and thus, can eliminate the inconsistent of circuit-design information and package design information.
In addition, the history of the pin exchange in the circuit design CAD device 100 record package design, and the historical information that pin is exchanged is provided to FPGA Design CAD device 10.Like this, the history of the pin exchange in the circuit design CAD device 100 record package design, and the historical information of pin exchange is provided to FPGA Design CAD device 10, and can guarantees the consistance between FPGA design, circuit design and the package design thus.
Next, the structure according to the FPGA coordinate design system of first embodiment is made an explanation.Fig. 2 is the functional block diagram according to the FPGA coordinate design system of first embodiment.As shown in the drawing, this FPGA coordinate design system comprises FPGA Design CAD device 10, package design CAD device 20 and circuit design CAD device 100.
Circuit design CAD device 100 is supported the circuit design as parts with FPGA collaboratively with FPGA Design CAD device 10 and package design CAD device 20.Fig. 3 is the key diagram that is used for the rendering circuit design.As shown in the drawing, the symbol that circuit designers will be registered as the symbolic library that is associated with parts is arranged in the circuit diagram, and the symbol pin is connected to each other, thus design circuit.
Yet, under the situation of FPGA, if symbol is registered as symbolic library before writing program on the FPGA, because pin can be used for input or output, so pin is defined as the I/O pin.Therefore, when using the symbolic library of registration, the pin that is used to import is positioned at the right side, and on the contrary, the pin that is used to export is positioned at the left side, perhaps sequentially do not arrange bus shown in Fig. 4 A, and circuit diagram complicates thus.
Therefore, when write-in program, need the Create Symbol storehouse.As a result, in this case, when write-in program, circuit design CAD device 100 is created the symbolic library of FPGA.Shown in Fig. 4 B, by creating the symbolic library of FPGA when the write-in program, can be with the pin arrangement that is used to import in the left side, and can sequentially arrange bus.
Return the explanation to Fig. 2, circuit design CAD device 100 comprises: FPGA information management unit 110, FPGA information memory cell 115, storehouse creating unit 120, symbolic library storage unit 125, circuit diagram reflection unit 130, circuit diagram storage unit 135, DRC unit 140, pin switch processing unit 150, constraint condition storage unit 155, historical output unit 160 and change history storage unit 165.
FPGA information management unit 110 is to be used to manage FPGA information processing unit.FPGA information management unit 110 obtains FPGA information (such as the corresponding relation between physical pins and the logic pin, pin I/O attribute, magnitude of voltage and frame (bank) numbering) from the file by FPGA Design CAD device 10 output, and with the FPGA information stores obtained in FPGA information memory cell 115.
In this case, at FPGA information management unit 110 at first with after the FPGA information stores is in FPGA information memory cell 115, when FPGA information management unit 110 obtains FPGA information and is stored in the FPGA information of obtaining in the FPGA information memory cell 115 again, FPGA information management unit 110 also will indicate the change historical storage of change of FPGA information in changing history storage unit 165.
FPGA information memory cell 115 is with FPGA information stores storage unit therein under the control of FPGA information management unit 110.Fig. 5 is the figure that is stored in the example of the FPGA information in the FPGA information memory cell 115.As shown in the drawing, FPGA information memory cell 115 is stored physical pins title, logic pin title, I/O attribute, frame numbering, exchange group #, differential attribute and the supply voltage about each pin therein.
Storehouse creating unit 120 is to utilize the FPGA information that is stored in the FPGA information memory cell 115 to create the processing unit of the symbolic library of FPGA, and the symbolic library of being created is stored in the symbolic library storage unit 125.Storehouse creating unit 120 comprises part division unit 121 and symbol creating unit 122.Part division unit 121 is divided into a plurality of parts with circuit diagram.Symbol creating unit 122 is created the symbol of the various piece that is marked off by part division unit 121.
Part division unit 121 is divided into a plurality of parts based on the part division rule of user by the GUI appointment with circuit diagram.Divide as this part,, circuit diagram is divided into a plurality of parts according to each frame numbering, each frame group, each logic pin title etc.In addition, part division unit 121 is determined the rightmost side pin on the symbol and the position of leftmost side pin based on the I/O attribute, and by sort to determine the order of pin by the pin attribute.In addition, part division unit 121 receives the regulation that is used for displacement pin between a plurality of parts via GUI from the user, and the displacement pin.
In addition, when the Create Symbol storehouse, storehouse creating unit 120 checks whether the symbol of the FPGA that wants Create Symbol is arranged in the circuit diagram.If this symbol is arranged in the circuit diagram, then storehouse creating unit 120 is come the Create Symbol storehouse by reference about the information of the symbol of layout.
Specifically, storehouse creating unit 120 comes operating part to distribute by the logic pin name being referred to as key with reference to existing symbolic library.In addition, storehouse creating unit 120 is created such symbolic library, is having the symbol pin arrangement now in the symbolic library identical position, residing position with previous pin in this symbolic library.Promptly, storehouse creating unit 120 will have be included in the logic pin title in the existing symbol pin assignments on the same position of the part identical with previous pin residing position in existing part, and will have the pin assignments that is not included in the logic pin title in the existing symbol to the identical part of the residing part of previous pin with same physical pin title.In addition, storehouse creating unit 120 will have the vacant position of pin arrangement on symbolic library of the logic pin title different with the logic pin title of using in existing symbol.If on symbolic library, there is not vacant position, storehouse creating unit 120 size in escape character storehouse in a downward direction then, and at the location arrangements pin of expansion.
When the symbol of the FPGA that wants Create Symbol was arranged in the circuit diagram, storehouse creating unit 120 was come the Create Symbol storehouse by reference about the information of the symbol of layout, and can make thus because the circuit diagram that change the caused change of FPGA design minimizes.
Symbolic library storage unit 125 is the storage unit of storing the symbolic library of FPGA therein.Fig. 6 is the figure that is stored in the example of the symbolic library in the symbolic library storage unit 125.As shown in the drawing, symbolic library storage unit 125 stores therein: about the information of library name, date created/time, version, occupied area, figure table quantity and symbol number of pin, about the information of each figure of forming symbol and about the information of each pin.
Circuit diagram reflection unit 130 is processing units, if wherein be disposed in the circuit diagram by the symbol of the FPGA in storehouse creating unit 120 Create Symbol storehouses, then this processing unit is replaced the symbol of layout with the new symbol of creating.If a line is connected to the pin with logic pin title different with the previous logic pin title of using before replacing it, then circuit diagram reflection unit 130 cuts off this line.
If a line is connected to the pin with logic pin title different with replacing it the preceding previous logic pin title of using, then circuit diagram reflection unit 130 cuts off this line, and can reduce thus to omit because the circuit diagram that change caused of FPGA design is changed.
Circuit diagram storage unit 135 is storage unit, is used to store about the information of the circuit diagram of arrangement component therein.If wherein the symbol by the FPGA in storehouse creating unit 120 Create Symbol storehouses is disposed in the circuit diagram, then circuit diagram storage unit 135 is upgraded by circuit diagram reflection unit 130.
DRC unit 140 is the processing units that are used to carry out DRC.The information in being stored in part library 30, DRC unit 140 is also by carrying out DRC with reference to the FPGA information of being managed by FPGA information management unit 110.Specifically, I/O attribute, differential wave, supply voltage etc. are checked in DRC unit 140.DRC is carried out by reference FPGA information in DRC unit 140, and can carry out the DRC that is associated with FPGA exactly thus.
Pin switch processing unit 150 is processing units, and this processing unit receives the pin exchange message by 20 outputs of package design CAD device, and the exchange of the pin that will carry out in package design is reflected in FPGA information, symbolic library and the circuit diagram.In FPGA, can change the operation of components interior by write-in program, thereby carry out the pin replacement (pin exchange) of FPGA parts so that pin assignments is easy in the package design stage.Therefore, pin switch processing unit 150 is carried out the pin in the package design is exchanged the processing that is reflected in the circuit design.
Fig. 7 is the figure of the example of pin exchange.As shown in the drawing, when the line that connects intersects, can exchange the intersection of eliminating these lines by the pin of FPGA between FPGA and miscellaneous part.How Fig. 8 exchanges the figure that is reflected in the example in the circuit diagram with pin.As shown in the drawing, in this circuit diagram, in the symbol that has physical pins title " D1 ", " E1 ", " F1 " and " G1 " respectively, changed the pin layout.
The also pin exchange in the reflection package design in such as the constraint condition of the linear distance length between the pin of pin switch processing unit 150.During pin switch processing unit 150 also is reflected in the exchange of the pin in the package design under the constraint condition, and can guarantee the consistance of design information between circuit design and package design thus.
In addition, 110 storages of pin switch processing unit 150 indication FPGA information management units exchange the change history of the FPGA information that causes owing to pin.Then, FPGA information management unit 110 should change historical storage in changing history storage unit 165.
Constraint condition storage unit 155 is the storage unit about the constraint condition of circuit design of storing therein such as the length of the line between the pin.Fig. 9 is the figure that is stored in the example of the constraint condition in the constraint condition storage unit 155.As shown in the drawing, constraint condition storage unit 155 is stored the constraint condition about the linear distance length between the pin therein.For example, be stored as constraint condition be: the length that the physical pins name that the physical pins name of parts " IC1 " is called the pin of " G1 " and parts " I12 " is called the line between the pin of " 2 " is 50mm or following.
Historical output unit 160 is processing units, and the change history of the FPGA information that this processing unit will change in the processing of the pin exchange that reflection is carried out by pin switch processing unit 150 outputs to the file of the form that can be input to FPGA Design CAD device 10 as announcement information.
Changing history storage unit 165 is the storage unit of storing the change history of the FPGA information of being managed by FPGA information management unit 110 therein.Figure 10 is the figure that is stored in the example that changes the change history in the history storage unit 165.As shown in the drawing, when carrying out pin exchange processing, change history storage unit 165 is stored the information about the pin of handling date and exchange therein.In addition, whenever 160 outputs of historical output unit change historical and whenever FPGA information management unit 110 when FPGA Design CAD device 10 obtains FPGA information, change history storage unit 165 date of stores processor therein.
Figure 11 is the figure of example that is outputed to the announcement information of FPGA Design CAD device 10 by historical output unit 160.As shown in the drawing, at the pin of each exchange, historical output unit 160 output physics pin name claim to be referred to as announcement information with the logic pin name of pin exchange change afterwards.Figure 12 is the figure of the output format of this announcement information.
Like this, change the change history that history storage unit 165 is stored FPGA information therein, and historical output unit 160 will change the historical file that outputs to the form that can be input to FPGA Design CAD device 10 as announcement information.Therefore, can guarantee the consistance of design information between package design, circuit design and FPGA design.
Then, the processing procedure in the Create Symbol storehouse of being carried out by circuit design CAD device 100 and the processing of cloth set symbol are made an explanation.Figure 13 is the process flow diagram by the processing of the processing procedure in the Create Symbol storehouse of circuit design CAD device 100 execution and cloth set symbol.
As shown in the drawing, in circuit design CAD device 100, FPGA information management unit 110 obtains the FPGA information such as pin assignments information and attribute information from the file by 10 outputs of FPGA Design CAD device, and with the FPGA information stores of obtaining (step S101) in FPGA information memory cell 115.
Then, storehouse creating unit 120 determines whether be disposed in (step S102) in the circuit diagram with the corresponding symbol of FPGA information that is obtained by FPGA information management unit 110.If this symbol is not arranged in the circuit diagram, then storehouse creating unit 120 is divided into a plurality of parts (step S103) by using the part division rule by user's appointment with circuit diagram, and according to for example by based on the I/O attribute with pin assignments to the right side or the left side come the pre-defined rule of Create Symbol, determine the position (step S104) of symbol pin.
If this symbol is disposed in the circuit diagram, then storehouse creating unit 120 will have the pin assignments of identical logic pin title to the part (step S105) identical with the residing part of this previous pin with previous pin by distributing with reference to the previous part of carrying out.If pin has not the logic pin title of being used by previous pin, then storehouse creating unit 120 with this pin assignments to the part (step S106) identical with the residing part of previous pin with same physical pin title.Then, the pin arrangement that will have identical logic pin title with previous pin is in the position (step S107) identical with this residing position of previous pin, and will have not the vacant position (step S108) of pin arrangement on symbol of the logic pin title of being used by previous pin.
Storehouse creating unit 120 receives the regulation that is used to change part distribution or pin positions via GUI from the user.If specified these changes, then storehouse creating unit 120 is come Create Symbol storehouse (step S109) by changing part distribution or pin positions, and the symbolic library of creating is stored in (step S110) in the symbolic library storage unit 125.
Then, circuit diagram reflection unit 130 determines wherein whether the previous symbol of having been created the FPGA of symbolic library by storehouse creating unit 120 is disposed in (step S111) in the circuit diagram.If this previous symbol is disposed in the circuit diagram, then circuit diagram reflects the symbol (step S112) that the 130 usefulness new symbolic substitution of creating in unit is arranged.If a line is connected to the pin that will arrange with logic pin title different with the previous logic pin title of using before, then circuit diagram reflection unit 130 cuts off this line (step S113).
Then, by parts input function the symbol of creating is arranged in (step S114) in the circuit diagram by user's appointment.
Like this, if be disposed in the circuit diagram with the corresponding symbol of FPGA information that obtains by FPGA information management unit 110, then storehouse creating unit 120 is by coming the Create Symbol storehouse with reference to the previous symbolic library of creating, and the symbol that circuit diagram reflection unit 130 usefulness have wherein newly been created symbolic library is replaced the symbol of layout.Therefore, the circuit diagram that the change owing to FPGA design is caused is changed and is minimized.
In addition, in this case, if the FPGA in Create Symbol storehouse is disposed in the circuit diagram, then storehouse creating unit 120 is with reference to the previous symbolic library of creating.Alternatively, if the symbolic library of the FPGA in Create Symbol storehouse is stored in the symbolic library storage unit 125, then storehouse creating unit 120 can be with reference to the symbolic library of previous establishment.
Then, being used to of being carried out by DRC unit 140 checked that the processing of I/O attribute makes an explanation.Figure 14 is the process flow diagram of processing procedure of being checked the processing of I/O attribute by DRC unit 140 being used to of carrying out.
As shown in the drawing, the arbitrary gauze in the connection group is paid close attention in DRC unit 140, and obtains and be included in the relevant information (S201) of all pins in the gauze paid close attention to.Then, the arbitrary pin (step S202) that has obtained its information is paid close attention in DRC unit 140, and determines whether the pin of paying close attention to is used for FPGA parts (step S203).
As a result, if the pin of paying close attention to is used for the FPGA parts, then by check the I/O attribute (step S204) of this pin with reference to the FPGA information in the FPGA information memory cell 115 of being stored in.If the pin of paying close attention to is not to be used for the FPGA parts, then check the I/O attribute (step S205) of this pin by reference cell storehouse 30.Then, determined whether to check the I/O attribute (step S206) of all pins.If there is unchecked any pin, then system's control turns back to step S202, and pays close attention to unchecked pin to check its I/O attribute.
If checked the I/O attribute of all pins, determine then whether the gauze of paying close attention to comprises two or more output pins (step S207).If comprise two or more output pins, then indicate this gauze to be connected mistake (step S208) between the output pin to user notification.In addition, determine whether the gauze of paying close attention to comprises any output pin (step S209).If do not comprise any output pin, then in the concern gauze, there is not the mistake (step S210) of output pin to the user notification indication.If it is output pin that a pin is only arranged, then be in (step S211) under the normal condition to gauze that user notification is paid close attention to.
Then, determined whether to check the quantity (step S212) of output pin at institute's wired network.If there is any gauze of not checking output pin quantity, then system's control turns back to step S201, and concern does not check that the gauze of output pin quantity is to check the quantity of output pin.If all determine to have checked the quantity of output pin, check that then the processing of I/O attribute stops at institute's wired network.
Like this, about the FPGA parts, the I/O attribute of pin is checked by reference FPGA information in DRC unit 140, and can check the I/O attribute of the circuit that comprises FPGA thus exactly.
Then, being used to of being carried out by DRC unit 140 checked that the processing of differential wave makes an explanation.Figure 15 is the process flow diagram by the processing procedure of the processing of the inspection differential wave of DRC unit 140 execution.
As shown in the drawing, arbitrary gauze is paid close attention in DRC unit 140, and obtains and be included in the relevant information (step S301) of all pins in the gauze paid close attention to.With the differential attribute of expression be positive pin quantity positive number of pin and represent of the negative number of pin zero clearing (step S302) of differential attribute for the quantity of negative pin.Then, pay close attention to the arbitrary pin (step S303) that has obtained its information, and determine whether the pin of paying close attention to is used for FPGA parts (step S304).
As a result, if the pin of paying close attention to is used for the FPGA parts, then by check the differential attribute (step S305) of this pin with reference to the FPGA information in the FPGA information memory cell 115 of being stored in.If the pin of paying close attention to is not to be used for the FPGA parts, then check the differential attribute (step S306) of this pin by reference cell storehouse 30.Then, if differential attribute then increases " 1 " with positive number of pin for just, if perhaps differential attribute, then will be born number of pin increase " 1 " (step S307) for negative.
Determined whether to check the differential attribute (step S308) of all pins.If there is any pin of not checking differential attribute, then system's control turns back to step S303, and pays close attention to and do not check that the pin of differential attribute is to check its differential attribute.
If checked the differential attribute of all pins, determine then whether positive number of pin is whether positive quantity and negative number of pin also are positive quantitys, that is, and the pin that has the pin of positive attribute and have a negative attribute whether all be present in pay close attention to (step S309) in the gauze.If positive number of pin is that positive quantity and negative number of pin also are positive quantitys, then indicate pin to be connected to the mistake (step S310) of pin with negative attribute with positive attribute to user notification.If any in positive number of pin or the negative number of pin is positive quantity, then be in normal condition (step S311) to gauze that user notification is paid close attention to.
Then, determine whether to have checked differential wave (step S312) at institute's wired network.If there is any gauze of not checking differential wave, then system's control turns back to step S301, and pays close attention to and do not check that the gauze of differential wave is to check its differential wave.If all determine to have checked differential wave, check that then the processing of differential wave stops at institute's wired network.
Like this, about the FPGA parts, the differential attribute of pin is checked by reference FPGA information in DRC unit 140, and can check the differential wave in the circuit that comprises FPGA thus exactly.
Then, being used to of being carried out by DRC unit 140 checked that the processing of supply voltage makes an explanation.Figure 16 is the process flow diagram by the processing procedure of the processing of the inspection supply voltage of DRC unit 140 execution.
As shown in the drawing, arbitrary parts (step S401) are paid close attention in DRC unit 140, and pay close attention to and be included in the arbitrary pin (step S402) in the parts paid close attention to.Then, determine the pin of paying close attention to whether be power pin (step S403).If the pin of paying close attention to is not a power pin, then system's control proceeds to step S410.
If the pin of paying close attention to is a power pin, determine then whether the pin of paying close attention to is used for FPGA parts (step S404).If the pin of paying close attention to is used for the FPGA parts, then by check the supply voltage (step S405) of this pin with reference to the FPGA information in the FPGA information memory cell 115 of being stored in.If the pin of paying close attention to is not to be used for the FPGA parts, then check the supply voltage (step S406) of this pin by reference cell storehouse 30.Then, the magnitude of voltage that the concern pin is connected to its gauze is checked (step S407), and determine this magnitude of voltage whether with the supply voltage identical (step S408) of this pin.If the supply voltage of this magnitude of voltage and this pin is inequality, then to the described supply voltage of user notification different with this magnitude of voltage (step S409).
Then, determine whether to have checked all pins (step S410).If there is unchecked any pin, then system's control turns back to step S402, and pays close attention to unchecked pin to check the magnitude of voltage of power pin.
If checked all pins, then determine whether to have checked supply voltage (step S411) at all parts.If there are any parts of not checking supply voltage, then system's control turns back to step S401, and concern does not check that the parts of supply voltage are to check supply voltage.If all determine to have checked supply voltage, check that then the processing of supply voltage stops at all parts.
Like this, about the FPGA parts, the magnitude of voltage of power pin is checked by reference FPGA information in DRC unit 140, and can check the supply voltage in the circuit that comprises FPGA thus exactly.
Then, the pin exchange processing of being carried out by pin switch processing unit 150 is made an explanation.Figure 17 is the process flow diagram that is exchanged the processing procedure of handling by the pin that pin switch processing unit 150 is carried out.
As shown in the drawing, pin switch processing unit 150 obtains the pin exchange message of being created by package design CAD device 20 (step S501), and replaces the physical pins title (step S502) of the symbolic library of the FPGA that carries out the pin exchange therein.
Then, replace (step S503) with having carried out the logic pin title and the logic association attributes that comprise in the FPGA information of FPGA of pin exchange therein, and the symbol in the circuit diagram is updated to the symbol (step S504) of wherein having replaced logic pin title and logic association attributes.About having the pin of constraint condition, when carrying out the pin exchange, replace constraint condition (step S505).
Like this, about having the pin of constraint condition, when carrying out the pin exchange, pin switch processing unit 150 is replaced constraint condition, and the pin among the package design CAD can be exchanged in the information that be reflected in exactly about circuit design thus.
Then, be used to export and change historical processing and make an explanation what carry out by historical output unit 160.Figure 18 is the process flow diagram that is changed the processing procedure of historical processing by the output that historical output unit 160 is carried out.As shown in the drawing, obtain up-to-date FPGA information from be stored in the change history that changes the history storage unit 165 after, 160 pairs of outputs of historical output unit will notify the last processing of the announcement information of FPGA Design CAD device 10 to search for (step S601).
Then, the pin of carrying out the pin exchange in be during till the last processing up to now of output notice information is carried out mark (step S602).Output is labeled the up-to-date attribute of pin as the announcement information (step S603) that will be notified to FPGA Design CAD device 10.
Promptly, after FPGA information management unit 110 obtains FPGA information and has upgraded the FPGA information that is stored in the FPGA information memory cell 115 from FPGA Design CAD device 10, historical output unit 160 outputs will be carried out the up-to-date attribute of still failing to give notice of the pin of pin exchange, as announcement information.
Like this, historical output unit 160 is stored in the change history that changes in the history storage unit 165 by use, the up-to-date attribute that will carry out the pin of pin exchange outputs to FPGA Design CAD device 10 as announcement information, and the exchange of the pin in the package design can be reflected in the FPGA design information thus.
In addition, after FPGA information management unit 110 obtains FPGA information and upgraded the FPGA information that is stored in the FPGA information memory cell 115 from FPGA Design CAD device 10, only will carry out the up-to-date attribute of still failing to give notice of the pin of pin exchange and export as announcement information.As a result, can avoid exporting the announcement information of waste or make announcement information overlapping, and the exchange of the pin in the package design can be reflected in the FPGA design information effectively thus.
As mentioned above, in the first embodiment, the FPGA information management unit 110 that is included in the circuit design CAD device 100 obtains the FPGA information of being created by FPGA Design CAD device 10 such as pin assignments information and attribute information, and storehouse creating unit 120 is come the Create Symbol storehouse by using this FPGA information.Therefore, circuit designers does not need to create the symbolic library of FPGA, thereby can reduce the workload of circuit designers.
In addition, when the Create Symbol storehouse, if the FPGA in Create Symbol storehouse is disposed in the circuit diagram, then storehouse creating unit 120 manages not change as far as possible part distribution and the pin layout that is arranged in the existing symbolic library in the circuit diagram.In addition, when the symbol that will newly create the FPGA of symbolic library when circuit diagram reflection unit 130 is arranged in the circuit diagram, do not change existing this symbol of the local layout of cloth.Therefore, the change of the circuit diagram that the change owing to FPGA design causes is minimized.
In addition, in the first embodiment, when DRC is carried out in the DRC unit 140 in being included in circuit design CAD device 100, about FPGA, by with reference to obtaining and be stored in the attribute etc. that FPGA information the FPGA information memory cell 115 is checked pin from FPGA Design CAD device 10 by FPGA information management unit 110.Therefore, can carry out DRC exactly.
In addition, in the first embodiment, the pin switch processing unit 150 that is included in the circuit design CAD device 100 obtains the pin exchange message from package design CAD device 20, and except symbolic library, FPGA information and circuit diagram, also this pin exchange is reflected in the constraint condition.Therefore, can eliminate the inconsistency of design information between circuit design and package design.
In addition, in the first embodiment, be included in change history storage unit 165 in the circuit design CAD device 100 and store the change history of FPGA information therein, and historical output unit 160 will be used to notify the information of pin exchange to output to FPGA Design CAD device 10 based on being stored in the change history that changes in the history storage unit 165.Therefore, can guarantee the consistance of design information between package design, circuit design and FPGA design.
In the first embodiment, considered such situation, in this case,, carried out the package design of printed circuit board (PCB) based on result by using the FPGA parts to come design circuit.FPGA deviser and package designer consider in advance that all the pin assignments of expectation can go far towards to shorten the design cycle.Therefore, in second embodiment of the present invention, explained the FPGA coordinate design system of the coordinate design of carrying out between a kind of FPGA of being supported in deviser and the package designer.
At first, the notion according to the FPGA coordinate design of second embodiment is made an explanation.Figure 19 is the key diagram that is used to explain according to the notion of the FPGA coordinate design of second embodiment.As shown in the drawing, in FPGA coordinate design according to second embodiment, temporary library creation apparatus 200 as the coordinate design supportive device receives the FPGA pin information of being created by FPGA Design CAD device 10 such as pin assignments information, and creates the temporary library of FPGA.In this case, temporary library is represented component shape typelib required when package design CAD device 20 is carried out pin assignments, and is the interim establishment storehouse at FPGA.
Temporary library creation apparatus 200 obtains the pin exchange message from package design CAD device 20, and the pin exchange message of obtaining is reflected in by in the FPGA information of himself managing, and this pin exchange message is notified to FPGA Design CAD device 10.
Like this, in second embodiment, temporary library creation apparatus 200 receives the FPGA pin information of being created by FPGA Design CAD device 10, and creates the interim component shape typelib at FPGA.Therefore, can consider pin assignments by using package design CAD device 20.
Then, the structure according to the FPGA coordinate design system of second embodiment is made an explanation.Figure 20 is the functional block diagram according to the structure of the FPGA coordinate design system of second embodiment.As shown in the drawing, this FPGA coordinate design system comprises FPGA Design CAD device 10, package design CAD device 20 and temporary library creation apparatus 200.Temporary library creation apparatus 200 comprises gauze tabulation acquiring unit 210, gauze list management unit 220, gauze tabulation converting unit 230, FPGA Design CAD interface unit 240, FPGA pin information administrative unit 250, temporary library creating unit 260 and pin switch processing unit 270.
Gauze tabulation acquiring unit 210 is to obtain gauze tabulation of being created by the user and the processing unit that this gauze tabulation is sent to gauze list management unit 220.Figure 21 is the figure of the example of the gauze tabulation of being obtained by gauze tabulation acquiring unit 210.
As shown in the drawing, gauze tabulation comprises: the parts definition unit that parts are defined, and the gauze definition unit that gauze is defined.In the parts definition unit,, component names and part library title are described at the parts that are used to consider.Yet, about the FPGA parts, do not have part library, thereby module title (being used to distinguish the title of FPGA) be described as following at " FPGA/ " afterwards.
In the gauze definition unit,, gauze title and the component pin that is connected to this gauze are described at each gauze.In this case, with " (component names). (component pin title) " form component pin is described.In addition, about the FPGA parts, logic pin title or physical pins title are described as pin title (physical pins title " % " mark).
Gauze list management unit 220 is the administrative units of storing and managing the gauze tabulation of being obtained by gauze tabulation acquiring unit 210 therein.When receiving the user via the change of the gauze tabulation of GUI input, gauze list management unit 220 changes the gauzes tabulation.
Gauze tabulation converting unit 230 is to be used for converting the gauze tabulation by 220 management of gauze list management unit to can be input to package design CAD device 20 form.When the tabulation of conversion gauze, gauze tabulation converting unit 230 is with reference to the FPGA information by 250 management of FPGA pin information administrative unit.
Figure 22 is the figure by the example of the gauze tabulation of gauze tabulation converting unit 230 outputs.As shown in the drawing, the gauze tabulation comprises component names, library name, component terminal numbering, pin title, gauze title, exchange group # and the differential type at each pin.In this case, the component terminal numbering is a serial number of distributing to each pin.
FPGA Design CAD interface unit 240 is the interfaces at FPGA Design CAD device 10.Specifically, FPGA Design CAD interface unit 240 obtains the FPGA pin information from FPGA Design CAD device 10, and the pin exchange message is offered FPGA Design CAD device 10.
FPGA pin information administrative unit 250 is the administrative units of storing and managing the FPGA pin information that is obtained by FPGA Design CAD interface unit 240 therein.In addition, be used to change pin at interval or during the instruction of FPGA pin information, FPGA pin information administrative unit 250 changes the FPGA information when receiving from the user via GUI.
Temporary library creating unit 260 is to use the processing unit of being created temporary library (that is interim component shape typelib) by the FPGA pin information of FPGA pin information administrative unit 250 management at the FPGA parts.
Figure 23 is the figure by the example of the temporary library of temporary library creating unit 260 establishments.As shown in the drawing, in temporary library, platform (land) shape type library name, X coordinate, Y coordinate, angle and pin title about each pin have been described.In addition, about platform shape typelib title, use the information that when receiving instruction from the user, is stored in the FPGA pin information administrative unit 250.
In addition, in temporary library, the zone of expression component sizes has been described also.In design during package design, use about this regional information and come distance between the calculating unit.In addition, come the size of calculating unit at interval based on pin by temporary library creating unit 260.
Temporary library creating unit 260 is created temporary library based on the FPGA pin information, and can consider the pin assignments among the package design CAD thus.
Pin switch processing unit 270 is to be used for obtaining the pin exchange message and indicating FPGA pin information administrative unit 250 to change the processing unit of FPGA pin information from package design CAD device 20.FPGA pin information administrative unit 250 changes the FPGA pin information, and indication FPGA Design CAD interface unit 240 is notified to FPGA Design CAD device 10 with the pin exchange message.In addition, pin switch processing unit 270 changes the gauze tabulation based on pin exchange message index line train table administrative unit 220.
Then, the information processing that the output of being carried out by temporary library creation apparatus 200 is used for package design CAD makes an explanation.Figure 24 is the process flow diagram of processing procedure that is used for the information processing of package design CAD by the output that temporary library creation apparatus 200 is carried out.
As shown in the drawing, in temporary library creation apparatus 200, FPGA Design CAD interface unit 240 obtains the pin assignments information of being created by FPGA Design CAD device 10, and this pin assignments information is sent to FPGA pin information administrative unit 250, and FPGA pin information administrative unit 250 is created FPGA pin information (step S701) then.
In addition, gauze tabulation acquiring unit 210 obtains gauze tabulation (step S702), and this gauze tabulation is sent to gauze list management unit 220.When receiving the instruction that is used to change gauze tabulation etc. from the user, gauze list management unit 220 changes the gauze tabulation by himself management.When receiving at interval etc. regulation of pin from the user (step S703), FPGA pin information administrative unit 250 changes the FPGA pin information by himself management.
Then, temporary library creating unit 260 is obtained the coordinate of pin and is created interim component shape typelib (step S704) from the FPGA pin information, and (step S705) changed in 230 pairs of gauze tabulations of gauze tabulation converting unit.Then, gauze tabulation converting unit 230 will output to a file through the gauze tabulation of conversion, and temporary library creating unit 260 outputs to this document (step S706) with the temporary library of creating.
Like this, temporary library creation apparatus 200 has been created temporary library, and can consider pin assignments by using package design CAD device 20 thus.In addition, when receiving at interval etc. regulation of pin from the user, FPGA pin information administrative unit 250 changes the FPGA pin information by himself management.Therefore, the user can consider multiple pin pin assignments at interval.
Then, being used to of being carried out by temporary library creation apparatus 200 reflected that the consideration result's of encapsulation processing makes an explanation.Figure 25 is the process flow diagram by the processing procedure of the consideration result's of the reflection encapsulation of temporary library creation apparatus 200 execution processing.
As shown in the drawing, in temporary library creation apparatus 200, pin switch processing unit 270 obtains the pin exchange message (step S801) among the package design CAD, and replaces the gauze (step S802) that will carry out the pin of pin exchange comprising in the gauze tabulation.
Then, pin switch processing unit 270 is replaced logic pin title and the logical attribute (step S803) that is included in the FPGA information, and FPGA Design CAD interface unit 240 will output to a file (step S804) about the information that is replaced pin.
Like this, pin switch processing unit 270 obtains the pin exchange message among the package design CAD, and this pin exchange is reflected in gauze tabulation and the FPGA pin information.Then, FPGA Design CAD interface unit 240 will output to described file about the information of pin exchange.Therefore, the exchange of the pin in the package design can be reflected in the FPGA design information.
As mentioned above, in second embodiment, FPGA Design CAD interface unit 240 obtains the pin assignments information of being created by FPGA Design CAD device 10, and the pin assignments information that FPGA pin information administrative unit 250 management is obtained by FPGA Design CAD interface unit 240 is as the FPGA pin information, and temporary library creating unit 260 is created interim component shape typelib by using by the FPGA pin information of FPGA pin information administrative unit 250 management, and the interim component shape typelib of the form that can packed Design CAD device 20 be read outputs to described file.Therefore, can consider previous pin assignments by using package design CAD device 20, and can shorten the cycle of designing printed circuit board.
Circuit design CAD device and temporary library creation apparatus in first and second embodiments, have been explained respectively.Alternatively, can also realize the structure of circuit design CAD device and temporary library creation apparatus by adopting software, thus realization has identical functions respectively with circuit design CAD device and temporary library creation apparatus circuit design CAD program and temporary library creation procedure.Therefore, explained later is carried out the computing machine of this circuit design CAD program.In addition, also can carry out the temporary library creation procedure by similar computing machine.
Figure 26 is the functional block diagram of execution according to the computing machine 300 of the circuit design CAD program of first embodiment.As shown in the drawing, computing machine 300 comprises RAM 310, CPU 320, HDD 330, LAN interface 340, input/output interface 350 and DVD driver 360.
To be stored among the DVD by the circuit design CAD program 311 that computing machine 300 is carried out, and read from DVD, be installed in then on the computing machine 300 by DVD driver 360.Alternatively, circuit design CAD program 311 for example is stored in via LAN interface 340 and is connected in the database of other computer systems of computing machine 300, and is read from this database, is installed in then on the computing machine 300.Then, the circuit design CAD program 311 of installation is stored among the HDD 330, is read by RAM 310, is carried out by CPU 320 then.
In the present embodiment, explained the situation as parts with FPGA.Yet, the invention is not restricted to above situation.The present invention can also be applied to PLD is used as usually the situation of parts.
According to an aspect of the present invention, about situation, carry out DRC by using the pin attribute that after write-in program, obtains, and therefore can carry out DRC exactly at PLD.
According to another aspect of the present invention, about the situation of PLD, carry out the inspection of I/O attribute by using the I/O attribute that after write-in program, obtains, and can carry out the inspection of I/O attribute exactly thus.
According to a further aspect of the invention, about the situation of PLD, carry out the differential wave inspection by using the differential attribute that after write-in program, obtains, and can carry out the differential wave inspection exactly thus.
According to a further aspect of the invention, about the situation of PLD, carry out the supply voltage inspection by using the supply voltage that after write-in program, obtains, and can carry out the supply voltage inspection exactly thus.
Although described the present invention at specific implementations for the complete sum that exposes is clear, but therefore claims are not restricted, but can be interpreted as comprising all modifications and alternative arrangements in the basic instruction that clearly falls into this elaboration that it may occur to persons skilled in the art that.
Claims (13)
1. circuit design supportive device, this circuit design supportive device support design is with the circuit of PLD as parts, and this circuit design supportive device comprises:
The PLD information receiving unit, it receives PLD information, and this PLD information is the design information of using the PLD Design CAD to create by at PLD; With
The DRC unit, it is by using described PLD information and executing DRC.
2. circuit design supportive device as claimed in claim 1, wherein,
Described PLD information comprises the I/O attribute of pin, and
I/O attribute inspection as described DRC is carried out by the I/O attribute that uses described pin in described DRC unit.
3. circuit design supportive device as claimed in claim 1, wherein,
Described PLD information comprises the differential attribute of pin, and
Differential wave inspection as described DRC is carried out by the differential attribute that uses described pin in described DRC unit.
4. circuit design supportive device as claimed in claim 1, wherein,
Described PLD information comprises the supply voltage of pin, and
Supply voltage inspection as described DRC is carried out by the supply voltage that uses described pin in described DRC unit.
5. support to design the method as the circuit of parts with PLD for one kind, this method may further comprise the steps:
Receiving step receives PLD information, and this PLD information is the design information of using the PLD Design CAD to create by at PLD; And
Execution in step is by using described PLD information and executing DRC.
6. method as claimed in claim 5, wherein,
Described PLD information comprises the I/O attribute of pin, and
Described execution in step comprises by the I/O attribute that uses described pin carries out I/O attribute inspection as described DRC.
7. method as claimed in claim 5, wherein,
Described PLD information comprises the differential attribute of pin, and
Described execution in step comprises by the differential attribute that uses described pin carries out differential wave inspection as described DRC.
8. method as claimed in claim 5, wherein,
Described PLD information comprises the supply voltage of pin, and
Described execution in step comprises by the supply voltage that uses described pin carries out supply voltage inspection as described DRC.
9. computer readable recording medium storing program for performing, this computer readable recording medium storing program for performing stores computer program therein, described computer program makes computer realization support design with the method for PLD as the circuit of parts, and described computer program makes computing machine carry out following the processing:
Receive and handle, receive PLD information, this PLD information is the design information of using the PLD Design CAD to create by at PLD; And
Carry out and handle, by using described PLD information and executing DRC.
10. computer readable recording medium storing program for performing as claimed in claim 9, wherein,
Described PLD information comprises the I/O attribute of pin, and
Described execution is handled and is comprised by the I/O attribute that uses described pin and carry out I/O attribute inspection as described DRC.
11. computer readable recording medium storing program for performing as claimed in claim 9, wherein,
Described PLD information comprises the differential attribute of pin, and
Described execution is handled and is comprised by the differential attribute that uses described pin and carry out differential wave inspection as described DRC.
12. computer readable recording medium storing program for performing as claimed in claim 9, wherein,
Described PLD information comprises the supply voltage of pin, and
Described execution is handled and is comprised by the supply voltage that uses described pin and carry out supply voltage inspection as described DRC.
13. the manufacture method of a printed circuit board (PCB), this method are supported to design PLD are adopted as the circuit design supportive device of the circuit of parts, said method comprising the steps of:
Receive PLD information, this PLD information is the design information of using the PLD Design CAD to create by at PLD; And
By using described PLD information and executing DRC.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006327389 | 2006-12-04 | ||
| JP2006327389 | 2006-12-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101196951A true CN101196951A (en) | 2008-06-11 |
Family
ID=39247339
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2007101668439A Pending CN101196951A (en) | 2006-12-04 | 2007-10-22 | Circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US7831944B2 (en) |
| EP (1) | EP1930825A3 (en) |
| JP (1) | JP5040617B2 (en) |
| KR (1) | KR100941364B1 (en) |
| CN (1) | CN101196951A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106886623A (en) * | 2015-12-15 | 2017-06-23 | 台湾积体电路制造股份有限公司 | System for designing the integrated circuit with the preceding RC information of layout |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4732311B2 (en) * | 2006-11-29 | 2011-07-27 | キヤノン株式会社 | IMAGING DEVICE, ITS CONTROL METHOD, PROGRAM, AND STORAGE MEDIUM |
| EP1930823A3 (en) * | 2006-12-04 | 2011-06-08 | Fujitsu Limited | Circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method |
| US8176457B2 (en) * | 2006-12-04 | 2012-05-08 | Fujitsu Limited | Apparatus and method updating diagram of circuit based on pin swap performed in package design with respect to PLD |
| US8255844B2 (en) * | 2006-12-04 | 2012-08-28 | Fujitsu Limited | Coordinated-design supporting apparatus, coordinated-design supporting method, computer product, printed-circuit-board manufacturing method, circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method |
| EP1930830A3 (en) * | 2006-12-04 | 2011-06-29 | Fujitsu Limited | Coordinated-design supporting apparatus, coordinated-design supporting method, computer product, and printed-circuit-board manufacturing method |
| JP5589783B2 (en) * | 2010-11-09 | 2014-09-17 | 富士通株式会社 | Design program, design apparatus and design method |
| TW201301135A (en) * | 2011-06-16 | 2013-01-01 | Hon Hai Prec Ind Co Ltd | System and method for converting component data |
| MX364612B (en) | 2014-06-27 | 2019-05-02 | Anvil Int Llc | Adjustable bracket and hub for flexible hose support. |
| CN105245815A (en) * | 2015-09-23 | 2016-01-13 | 段然 | Method for realizing use of MIPI (Mobile Industry Processor Interface) lens in wearable equipment |
| US9864825B2 (en) | 2016-02-01 | 2018-01-09 | Ciena Corporation | Systems and methods for dynamic symbols for devices in electrical schematics |
| US9971864B2 (en) * | 2016-07-22 | 2018-05-15 | Hewlett Packard Enterprise Development Lp | Symmetry verifications for differential signal vias of an electronic circuit design |
| US11042683B2 (en) | 2016-07-22 | 2021-06-22 | Hewlett Packard Enterprise Development Lp | Void avoidance verifications for electronic circuit designs |
| TWI665556B (en) * | 2018-05-11 | 2019-07-11 | 緯穎科技服務股份有限公司 | Method for configuring input/output interfaces, device with configurable input/output interfaces and control system |
| US10783308B1 (en) * | 2018-12-20 | 2020-09-22 | Xilinix, Inc. | Method of assigning contact elements associated with an integrated circuit device |
Family Cites Families (33)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04246778A (en) | 1991-02-01 | 1992-09-02 | Nec Corp | Arranging system for semiconductor integrated circuit |
| US5297053A (en) | 1991-06-04 | 1994-03-22 | Computervision Corporation | Method and apparatus for deferred package assignment for components of an electronic circuit for a printed circuit board |
| JPH06163690A (en) | 1992-11-25 | 1994-06-10 | Kawasaki Steel Corp | Placement and routing apparatus for electronic device |
| US5625565A (en) | 1994-09-09 | 1997-04-29 | Cadence Design Systems, Inc. | System and method for generating a template for functional logic symbols |
| JP3712482B2 (en) * | 1996-11-25 | 2005-11-02 | 株式会社東芝 | Operation support device and operation support method |
| US6314550B1 (en) * | 1997-06-10 | 2001-11-06 | Altera Corporation | Cascaded programming with multiple-purpose pins |
| US5978862A (en) * | 1997-08-08 | 1999-11-02 | Toshiba America Information Systems, Inc. | PCMCIA card dynamically configured in first mode to program FPGA controlling application specific circuit and in second mode to operate as an I/O device |
| US6473885B1 (en) | 1998-07-17 | 2002-10-29 | Mentor Graphics Corporation | Digital circuit layout techniques using circuit decomposition and pin swapping |
| JP2000099558A (en) | 1998-09-25 | 2000-04-07 | Nec Eng Ltd | Design rule checking method/system |
| US6968514B2 (en) * | 1998-09-30 | 2005-11-22 | Cadence Design Systems, Inc. | Block based design methodology with programmable components |
| US6347387B1 (en) * | 1998-10-09 | 2002-02-12 | Agere Systems Guardian Corp. | Test circuits for testing inter-device FPGA links including a shift register configured from FPGA elements to form a shift block through said inter-device FPGA links |
| JP3529290B2 (en) * | 1998-12-11 | 2004-05-24 | 日本電気株式会社 | I / O buffer operation power supply automatic check system |
| US6239611B1 (en) * | 1999-06-10 | 2001-05-29 | Xilinx, Inc. | Circuit and method for testing whether a programmable logic device complies with a zero-hold-time requirement |
| JP2001092857A (en) | 1999-09-17 | 2001-04-06 | Nec Eng Ltd | Cad system for designing printed board |
| US6631510B1 (en) | 1999-10-29 | 2003-10-07 | Altera Toronto Co. | Automatic generation of programmable logic device architectures |
| US6725441B1 (en) | 2000-03-22 | 2004-04-20 | Xilinx, Inc. | Method and apparatus for defining and modifying connections between logic cores implemented on programmable logic devices |
| JP2002279010A (en) | 2001-03-19 | 2002-09-27 | Nec Corp | Device, method and program for generating logic circuit diagram |
| JP3772701B2 (en) | 2001-07-19 | 2006-05-10 | 日本電気株式会社 | Circuit diagram connection information output method and circuit diagram connection information output method |
| US6629307B2 (en) | 2001-07-24 | 2003-09-30 | Hewlett-Packard Development Company, Lp. | Method for ensuring correct pin assignments between system board connections using common mapping files |
| JP3615182B2 (en) | 2001-11-26 | 2005-01-26 | 株式会社東芝 | Optical proximity effect correction method and optical proximity effect correction system |
| US7024654B2 (en) | 2002-06-11 | 2006-04-04 | Anadigm, Inc. | System and method for configuring analog elements in a configurable hardware device |
| US6732349B1 (en) * | 2002-08-29 | 2004-05-04 | Xilinx, Inc. | Method and apparatus for improving PIP coverage in programmable logic devices |
| CN1521830A (en) | 2003-02-12 | 2004-08-18 | 上海芯华微电子有限公司 | Technical method for integrated circuit design, test and measurement integration |
| US7165230B2 (en) * | 2004-06-02 | 2007-01-16 | Altera Corporation | Switch methodology for mask-programmable logic devices |
| JP2006079447A (en) | 2004-09-10 | 2006-03-23 | Fujitsu Ltd | Integrated circuit design support device, integrated circuit design support method and integrated circuit design support program |
| US7299444B1 (en) | 2005-03-31 | 2007-11-20 | Altera Corporation | Interface for pin swap information |
| US7281233B1 (en) | 2005-05-27 | 2007-10-09 | Xilinx, Inc. | Method and apparatus for implementing a circuit design for integrated circuitry on a circuit board |
| US7218567B1 (en) * | 2005-09-23 | 2007-05-15 | Xilinx, Inc. | Method and apparatus for the protection of sensitive data within an integrated circuit |
| US7627838B2 (en) * | 2006-04-25 | 2009-12-01 | Cypress Semiconductor Corporation | Automated integrated circuit development |
| EP1930823A3 (en) | 2006-12-04 | 2011-06-08 | Fujitsu Limited | Circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method |
| CN101196945B (en) | 2006-12-04 | 2010-06-02 | 富士通株式会社 | Circuit-design supporting apparatus, circuit-design supporting method, and printed-circuit-board manufacturing method |
| EP1930830A3 (en) | 2006-12-04 | 2011-06-29 | Fujitsu Limited | Coordinated-design supporting apparatus, coordinated-design supporting method, computer product, and printed-circuit-board manufacturing method |
| US20080172442A1 (en) * | 2007-01-17 | 2008-07-17 | Inventec Corporation | Multi-computer system and configuration method therefor |
-
2007
- 2007-09-27 EP EP07117435A patent/EP1930825A3/en not_active Withdrawn
- 2007-09-28 US US11/905,321 patent/US7831944B2/en not_active Expired - Fee Related
- 2007-10-17 KR KR1020070104754A patent/KR100941364B1/en not_active IP Right Cessation
- 2007-10-22 CN CNA2007101668439A patent/CN101196951A/en active Pending
- 2007-11-27 JP JP2007305869A patent/JP5040617B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106886623A (en) * | 2015-12-15 | 2017-06-23 | 台湾积体电路制造股份有限公司 | System for designing the integrated circuit with the preceding RC information of layout |
| CN106886623B (en) * | 2015-12-15 | 2023-11-28 | 台湾积体电路制造股份有限公司 | System for designing integrated circuits with pre-layout RC information |
Also Published As
| Publication number | Publication date |
|---|---|
| JP5040617B2 (en) | 2012-10-03 |
| US7831944B2 (en) | 2010-11-09 |
| US20090049419A1 (en) | 2009-02-19 |
| JP2008165748A (en) | 2008-07-17 |
| KR100941364B1 (en) | 2010-02-10 |
| KR20080051037A (en) | 2008-06-10 |
| EP1930825A3 (en) | 2011-06-29 |
| EP1930825A2 (en) | 2008-06-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101196951A (en) | Circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method | |
| CN101196945B (en) | Circuit-design supporting apparatus, circuit-design supporting method, and printed-circuit-board manufacturing method | |
| CN101196946B (en) | Circuit-design supporting apparatus, circuit-design supporting method, and printed-circuit-board manufacturing method | |
| CN101196947B (en) | Circuit-design supporting apparatus, circuit-design supporting method | |
| CN101196952B (en) | Coordinated-design supporting apparatus, coordinated-design supporting method, and printed-circuit-board manufacturing method | |
| CN101493852B (en) | Analysis supporting apparatus, analysis supporting method, and analysis supporting program | |
| US8255844B2 (en) | Coordinated-design supporting apparatus, coordinated-design supporting method, computer product, printed-circuit-board manufacturing method, circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method | |
| CN101493851A (en) | Analysis supporting apparatus, analysis supporting method, and analysis supporting program | |
| CN101493850A (en) | Analysis supporting apparatus, analysis supporting method, and analysis supporting program | |
| CN101493853B (en) | Analysis supporting apparatus, analysis supporting method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20080611 |