CN101196943A - Test point error-checking method - Google Patents
Test point error-checking method Download PDFInfo
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- CN101196943A CN101196943A CNA2006101656085A CN200610165608A CN101196943A CN 101196943 A CN101196943 A CN 101196943A CN A2006101656085 A CNA2006101656085 A CN A2006101656085A CN 200610165608 A CN200610165608 A CN 200610165608A CN 101196943 A CN101196943 A CN 101196943A
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Abstract
A testpoint error-checking method is provided, which is applied to data processing devices and is loaded in a layout application program which is used to set up testpoints on the via of circuit board. The method comprises acquiring specification parameters of the via when the layout application program selects via; acquiring specification parameters of the testpoint when the layout application program selects the testpoint to be set up on the via; comparing the specification parameters of the selected via and those of the testpoint, and when the specification parameters of the via and the testpoint are not matched, the layout application program stops setting up testpoint temporarily and sends out error prompt information to ensure the accuracy of the selected testpoint, reduce error during operation, simplify the operation flow, save operation time and improve the working efficiency at the same time.
Description
Technical field
The present invention relates to a kind of test point verification technology, being particularly related to a kind of data processing equipment that is applied to also carries to laying in the application program, in order to verify the method that the selected through hole of desiring in circuit board (Via) is gone up the correctness of the test point of laying (testpoint).
Background technology
At present, in the laying process of printed circuit board (PCB), at the circuit of being laid in the design, in order accurately to test its for example duty such as clock signal and control signal, is made the correctness laid with checking institute, generally understood the test point (testpoint) that some for example is set on through hole (via) or the pin (pin) in the place of those signal flow warps of printed circuit board (PCB).
Choose the measurability that correct test point can improve whole printed circuit board (PCB), thereby improve the success ratio of product, if and because slip-stick artist's the carelessness or the defective of application program itself are easy to the overall performance that some incorrect test points is set and influences printed circuit board (PCB) then in adding the process of test point.
For instance, if to desire in a specifications parameter be that the through hole (Via) of 20_10 go up to be laid a test point, wherein, above-mentioned 20 expression weld pads are of a size of 20mil, and 10 expression through holes are of a size of 10mil.Generally, when choosing test point, the specifications parameter of selected test point should be complementary with the specifications parameter of this through hole, for example is VIA_30_20_10M1_ENTEK or VIA_30_20_10M2_ENTEK.But, choosing action because of this is by artificial execution, can produce mistake unavoidably, if mistake has been selected the test point of other specifications parameter and owing to lay slip-stick artist's error, VIA_30_16_10M2_ENTEK for example, this through hole weld pad diameter that it is used to test after test point is set will become 16mil so, 20mil than original design, size obviously reduces, and if lay with the size after this change, can influence be electrically connected performance, even cause the decline of quality of printed circuits, to be that we are desired avoid for this.In addition, existing laying application program has the temporary function of an option, choose in test point next time promptly that this laying application program can keep the setting of last time in the process, it still is example with above-mentioned, if the preceding test point of once choosing is " VIA_30_16_10M2_ENTEK ", this application program promptly keeps the result that chooses of this time, and when choosing next time, and can give tacit consent to this second time required test point of choosing still is last time " VIA_30_16_10M2_ENTEK " that is kept.This function of application program has also increased when can facilitate lays the probability that the slip-stick artist makes mistakes.Especially, switch between need test point when choosing, lay that the slip-stick artist is easy to be forgotten and make change action in option because of carelessness, cause the mistake of choosing of test point two or even more a plurality of different size parameters when running into.
These are provided with wrong test point, and general being difficult for discovered out, and application program itself does not have the spell-checking facility to these test points yet, and common way is by manual type each selected test point to be carried out debugging one by one, to verify its correctness.
But, in the aforementioned prior art, because of the debugging operation of test point is finished with manual type by laying the slip-stick artist, so its greatest drawback is less stable, unavoidably can be because of many factors, comprise that physiology, psychological factor or the external environment of laying slip-stick artist itself influence and result in mistake takes place in the operation process.In addition, the debugging operation meeting of above-mentioned test point correctness according to related test point specifications parameter or quantity what and produce different complexities, in other words, the more then debugging work is more consuming time for required material specification parameter or quantity, spent cost is also higher, seeking the production cost reduction to increase the manufacturer of product competitiveness to desiring most ardently, obviously is extremely irrational.
Therefore, how to overcome the defective of above-mentioned prior art, and then provide the function of the correctness of the selected test point of a kind of debugging automatically, with can be in the laying process of circuit pattern, avoid the mistake that causes because of manual operation in the prior art, the flow process that simplifies the operation and saving activity duration, and improve the efficient of work, real technical matters for needing to be resolved hurrily at present.
Summary of the invention
In view of the defective of above-mentioned prior art, fundamental purpose of the present invention is to provide a kind of carelessness that can avoid laying the slip-stick artist in the process that test point is laid, guarantees the test point error-checking method of the correctness of selected test point.
The test point error-checking method that another object of the present invention is to provide a kind of simplified operation flow process and save the activity duration.
A further object of the present invention is to provide a kind of test point error-checking method of increasing work efficiency.
For achieving the above object, the invention provides a kind of test point error-checking method.The method of a kind of laying test point (testpoint), it is applied in the data processing equipment, and lift-launch a to through hole (Via) that is used to circuit board is gone up in the laying application program of laying test point, this method comprises: when choosing the through hole of desire laying test point by this wiring application program, gather the specifications parameter of this through hole; When choosing the test point of desiring on this through hole, to lay, gather the specifications parameter of this test point by this wiring application program; And the specifications parameter of this selected through hole and the specifications parameter of this test point contrasted, and in both through contrast when not matching, then make this wiring application program suspend the action of laying test point, and a miscue information is sent in cooperation.
Above-mentioned this specifications parameter includes the size of weld pad (pad) and through hole.
Above-mentioned this test point error-checking method comprises that also the specifications parameter with the specifications parameter of selected through hole and test point is converted to discernible first code of this laying application program and second code respectively, is contrasted two codes for follow-up.Wherein, this contrast operation specifically refers to be contrasted by turn with this second code in order to the specifications parameter of expression test point by this first code in order to the specifications parameter of expression through hole, and when contrast does not match, promptly send a miscue information in this first code or second code arbitrary corresponding numeral in the two.In present embodiment, this first code and this second code are made up of " 0 " and the binary digit of " 1 ".
Test point error-checking method of the present invention, be in choosing by this wiring application program that the institute desire is laid the through hole of test point and during the test point desiring on this through hole, to lay, automatically the specifications parameter of this through hole of being collected and the specifications parameter of this test point are contrasted, and when contrast does not match, make this wiring application program suspend the action of laying test point, send a miscue information simultaneously, also can guarantee that selected test point is correct with real-time discovery mistake, thereby solve owing to for want of contrasting automatically in the prior art and need easily causing the defective of choosing the test point mistake by the artificial operating type that contrasts; In addition,,, thereby simplify the operation flow process and saving activity duration, increase work efficiency really by this test point error-checking method than prior art.
Description of drawings
Fig. 1 shows the schematic flow sheet of test point error-checking method of the present invention.
Description of reference numerals
S100～S108 step
Embodiment
Below by particular specific embodiment explanation embodiments of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by the disclosed content of this instructions.The present invention also can be implemented or be used by other different specific embodiment, and the every details in this instructions also can be based on different viewpoints and application, carries out various modifications and change under the spirit of the present invention not deviating from.
See also Fig. 1, it is the schematic flow sheet of test point error-checking method of the present invention.The method of this laying test point (testpoint) is for being applied in the data processing equipment, and lift-launch a to through hole (Via) that is used to circuit board is gone up in the laying application program of laying test point, in present embodiment, this circuit board is that (Printed Circuit Board PCB) illustrates for example with a printed circuit board (PCB).
As shown in the figure, test point of the present invention (testpoint) error-checking method comprises the steps: at first at step S100, when choosing the through hole of desire laying test point by this wiring application program, promptly gather the specifications parameter of this through hole, and specifications parameter that will this selected through hole is converted to the discernible first code of this laying application program.In present embodiment, this through hole can for example one have in the tabulation of a plurality of through hole alternate items and chosen by what this laid that application program provides.Above-mentioned this specifications parameter comprises the size of weld pad (pad) and through hole, and this first code is made up of " 0 " and the binary digit of " 1 ".For instance, if the specifications parameter of selected through hole is 20_10, wherein 20 expression weld pads are of a size of 20mil, and 10 expression through holes are of a size of 10mil, are expressed as (00010100_00001010) if this 20_10 is converted to binary code.Then, execution in step S102.
At step S102, when choosing the test point of desiring on this through hole, to lay by this wiring application program, gather the specifications parameter of this test point, and specifications parameter that will this selected test point is converted to the discernible second code of this laying application program, and this second code is made up of " 0 " and the binary digit of " 1 " equally.In present embodiment, this test point can for example one have to choose in the tabulation of most test point alternate items and obtain by what this laid that application program provides.For instance, if the specifications parameter of selected through hole is VIA-30-20-10M2-ENTEK, be expressed as (00010100_00001010) after then general 20_10 wherein is converted to binary code; And, be expressed as (0001000_000001010) after then general 16-10 wherein is converted to binary code if owing to the test point that specifications parameter is VIA-30-16-10M2-ENTEK is falsely dropped in the carelessness of laying the slip-stick artist.Then, execution in step S104.
At step S104, the specifications parameter of this selected through hole and the specifications parameter of this test point are contrasted, whether mate to judge the two.In present embodiment, the contrast of this through hole and this test point specifically is meant by this first code in order to the specifications parameter of expression through hole and contrasts by turn with this second code in order to the specifications parameter of expression test point, as long as the two wherein arbitrary corresponding digital of this first code and second code, when contrast does not match, can judge selected through hole and test point and not match.If the two when coupling, then execution in step S106; Otherwise, if the two is not when matching, execution in step S108 then.
At step S106, make this wiring application program on this through hole, lay this and choose correct test point.In present embodiment, through contrast can draw with specifications parameter be that the specifications parameter of the test point that is complementary of the through hole of 20_10 is VIA-30-20-10M2-ENTEK, and lay test point with this specifications parameter.
At step S108, make this wiring application program suspend the action of laying test point, and cooperate and send one and for example be the miscue information of " choose mistake, can not lay this test point ", for choosing correct test point again in follow-up.In present embodiment, when if the specifications parameter of the test point that the laying slip-stick artist is selected is VIA-30-16-10M2-ENTEK, then after contrast, send miscue information, make amendment for follow-up, and choose the correct reference point that specifications parameter is VIA-30-20-10M2-ENTEK again.
In sum, test point error-checking method of the present invention, when mainly choosing the test point that a through hole and is desired and this through hole is complementary by this wiring application program, gather the specifications parameter of this through hole and test point, and the specifications parameter of this through hole and the specifications parameter of this test point contrasted, whether thereby real-time judge goes out selected test point correct, and in both when contrast does not match, even this wiring application program is sent a miscue information, for in the follow-up test point of choosing again with this through hole coupling, guarantee the correctness of selected test point, cause test point to choose mistake so can solve in the prior art because of nothing provides mistake mechanism, and influence the defective of electrical connection properties and circuit board overall performance.In addition,, test point is carried out debugging, in prior art, use manually debugging one by one, can improve the accuracy of debugging, and simplify the operation flow process and saving activity duration, to increase work efficiency to phase shape with automated manner by test point error-checking method of the present invention.
The foregoing description only is illustrative principle of the present invention and effect thereof, but not is used to limit the present invention, that is the present invention in fact still can do other change.Therefore, any those skilled in the art all can make amendment to the foregoing description under spirit of the present invention and category.So the scope of the present invention, claims are listed as the aforementioned.
Claims (6)
1. test point error-checking method, it is applied in the data processing equipment, and carries the laying application program that is used to lay on the through hole of circuit board test point to, it is characterized in that this test point error-checking method comprises:
When choosing the through hole of desire laying test point by this wiring application program, gather the specifications parameter of this through hole;
When choosing the test point of desiring on this through hole, to lay by this wiring application program, gather the specifications parameter of this test point; And
The specifications parameter of this selected through hole and the specifications parameter of this test point are contrasted, and in both through contrast when not matching, make the action of this wiring application program time-out laying test point, the concurrent information that makes mistake.
2. test point error-checking method according to claim 1 is characterized in that, this specifications parameter system includes the size of weld pad and through hole.
3. test point error-checking method according to claim 1, it is characterized in that, also comprise the specifications parameter of selected through hole and the specifications parameter of test point, be converted to discernible first code of this laying application program and second code respectively, two codes are contrasted for follow-up.
4. test point error-checking method according to claim 3, it is characterized in that, this through hole and this test point contrast be meant, contrast by turn with this second code by this first code in order to the specifications parameter of expression test point in order to the specifications parameter of expression through hole, and when contrast does not match, send a miscue information in the two wherein arbitrary corresponding numeral of this first code and second code.
5. test point error-checking method according to claim 3 is characterized in that, this first code and this second code are made up of " 0 " and the binary digit of " 1 ".
6. test point error-checking method according to claim 1 is characterized in that, this circuit board is printed circuit board (PCB), base plate for packaging or multilayer circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006101656085A CN101196943A (en) | 2006-12-08 | 2006-12-08 | Test point error-checking method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006101656085A CN101196943A (en) | 2006-12-08 | 2006-12-08 | Test point error-checking method |
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| CN101196943A true CN101196943A (en) | 2008-06-11 |
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| CNA2006101656085A Pending CN101196943A (en) | 2006-12-08 | 2006-12-08 | Test point error-checking method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102479272A (en) * | 2010-11-24 | 2012-05-30 | 英业达股份有限公司 | Method for setting test points |
| CN109270084A (en) * | 2018-11-02 | 2019-01-25 | 郑州云海信息技术有限公司 | The method, apparatus and medium of PCB mass are determined based on detection ICT measuring point |
| CN109377405A (en) * | 2018-10-19 | 2019-02-22 | 广汽丰田汽车有限公司 | Specification method of calibration, device, readable storage medium storing program for executing and the system of tighten data |
-
2006
- 2006-12-08 CN CNA2006101656085A patent/CN101196943A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102479272A (en) * | 2010-11-24 | 2012-05-30 | 英业达股份有限公司 | Method for setting test points |
| CN109377405A (en) * | 2018-10-19 | 2019-02-22 | 广汽丰田汽车有限公司 | Specification method of calibration, device, readable storage medium storing program for executing and the system of tighten data |
| CN109270084A (en) * | 2018-11-02 | 2019-01-25 | 郑州云海信息技术有限公司 | The method, apparatus and medium of PCB mass are determined based on detection ICT measuring point |
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Open date: 20080611 |