CN101196808A - 8-digit microcontroller - Google Patents
8-digit microcontroller Download PDFInfo
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- CN101196808A CN101196808A CNA2006101193558A CN200610119355A CN101196808A CN 101196808 A CN101196808 A CN 101196808A CN A2006101193558 A CNA2006101193558 A CN A2006101193558A CN 200610119355 A CN200610119355 A CN 200610119355A CN 101196808 A CN101196808 A CN 101196808A
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Abstract
An eight bit microcontroller is provided, the structure comprises: a data memory, a programme memory, a data bus, an address bus, a command coder, a multiplexer, a register file and an arithmetic logic unit. The invention adopts a high speed four phase clock, a single cycle command only requires four clock cycles, the shortening of machine cycle greatly improves efficiency of command execution; the invention adopts a reduced instruction set structure, which not only changes the command length but also ensures the original function; the invention adopts a mode of unified addressing when addressing the data random memory inside and outside the chip, the speed when reading external data random memory is greatly improved.
Description
Technical field
The present invention relates to the microcontroller field of SIC (semiconductor integrated circuit), particularly relate to a kind of 8 8-digit microcontrollers.
Background technology
The core component of tradition 8 8-digit microcontrollers is arithmetic unit and control assembly.Described arithmetic unit is finished operations such as arithmetic, logic, position and data transmission; Described control assembly is benchmark with the dominant frequency, use CPU (central processing unit) sequential, get and refer to and instruction decode, control each hardware link co-ordination.The typical case of tradition 8 8-digit microcontrollers is represented as 8051, yet is using 8051 o'clock, often has a lot of weak points:
1.8051 the machine cycle of instruction is 12 clock period, the instruction cycle is 1 to 4 machine cycle, causes 8051 execution command efficient low excessively;
2.8051 the inside and outside data-carrier store of employing sheet separates addressing, efficient is low excessively when causing carrying out sheet data device addressing outward;
3.8051 adopt the 5V power supply, this causes 8051 system power dissipations higher.
Summary of the invention
Fundamental purpose of the present invention is to solve the deficiency of traditional 8 8-digit microcontrollers aspect clock speed, memory access speed and instruction execution speed, 8 8-digit microcontrollers that design a kind of processor speed height, have extensive adaptability, structural integrity.
Structure of the present invention comprises: data-carrier store, program storage, data bus, address bus, command decoder, MUX, register file, ALU.
The present invention adopts the mode of unified addressing when the data random access memory addresses inside and outside to sheet, speed improves a lot when reading the external data random access memory.
The present invention adopts 4 phase clocks at a high speed, and clock generator provides 4 phase clock signals, and system finishes corresponding operation in the clock of correspondence.Like this, an one-cycle instruction only needs 4 clock period both can finish, and the shortening of machine cycle has improved the efficient that instruction is carried out greatly.
The present invention adopts the reduced instruction structure set, guarantees original function again when changing instruction length.Instruction set one of the present invention has 60 instructions, every instruction length is 16, function according to instruction is divided into logical operation operational order, arithmetical operation operational order, data transfer operation instruction, other operational orders, affiliated other operational orders comprise that conditional transfer, bit manipulation, the program storage page are selected, the data-carrier store page is selected, enters sleep pattern, returned and interrupt return instruction, have formed the complete instruction set of a cover.
Described reduced instruction concentrate comprise 9 logical operation operational orders be used for will instruction operand carry out corresponding logical operation according to the result of instruction decode.
Described reduced instruction is concentrated and to be comprised 27 arithmetical operation operational orders, be used for will instruction operand carry out corresponding arithmetical operation according to the result of instruction decode.
Described reduced instruction is concentrated and is comprised 8 data transfer operation instructions, is used for source operand is reached destination register or storer according to the instruction decode result.
Comprise in other operational orders of described reduced instruction set computer that 1 enters sleep pattern instruction SLEP, is used to stop the vibration of king oscillator.
Comprise 1 house dog clear instruction WDTC in other operational orders of described reduced instruction set computer, be used for data zero clearing the house dog register.
Comprise 1 unconditional jump instruction JUMP in other operational orders of described reduced instruction set computer, be used for the numerical value of reprogramming counter, give programmable counter the assignment of counting immediately in the instruction.
Comprise 1 table-look-up instruction MOVC#a in other operational orders of described reduced instruction set computer, be used for 16 bit data of the program storage at a place, address of specified page are read, send into internal register then.
Comprise 1 table-look-up instruction MOVC R in other operational orders of described reduced instruction set computer, be used for internal processes reservoir 16 bit data are sent into internal register.
Comprise 1 transfer instruction CALL #a in other operational orders of described reduced instruction set computer, be used for giving programmable counter, carry out stacked processing after simultaneously current program counter value being added 1 a assignment
Comprise link order RET and RETI in other operational orders of described reduced instruction set computer, when described RET instruction is carried out, go out stack operation, give programmable counter with 16 bit data assignment in the storehouse, program is returned from subroutine address, and stack pointer subtracts 1 simultaneously; When described RETI instruction is carried out, go out stack operation, give programmable counter with 16 bit data assignment in the storehouse, program is returned from interrupting subroutine address, and stack pointer subtracts 1 simultaneously.
Comprise locked memory pages selection instruction PAGE and BANK in other operational orders of described reduced instruction set computer.Described PAGE instruction is used for the program storage page to be selected, and described BANK instruction is used for the data-carrier store page and selects.
The present invention adopts full Synchronization Design and complete static CMOS design, and highest frequency can reach 50MHZ.
Operating voltage of the present invention is 2.6V-5.5V.
Advantage of the present invention is: operating voltage of the present invention is 2.6V-5.5V, has reduced power consumption, and has expanded application; Adopt complete static CMOS design, can under lower frequency, move; The present invention adopts 4 phase clocks at a high speed, and per 4 clock period are a machine cycle, and instruction length is 16, and the execution of all instructions needs 1 or 2 machine cycle, and instruction execution speed is fast, and instruction is simplified, convenient programming; The present invention takes the inside and outside data-carrier store of sheet to adopt unified addressing mode, has improved the speed of the outer data-carrier store of visit sheet; The present invention has dormant state, and when dormant state, the king oscillator of microcontroller quits work, and greatly reduces the power consumption of CPU; The present invention adopts SOC (SOC (system on a chip)) technology, has characteristics such as volume is little, compact conformation, reliability height; The present invention can soft kernel form provide, and compares with existing 8 bit processors, and the wiring area is little, provides good support to the low end subscriber in the SOC design.
Description of drawings
Fig. 1 is the structured flowchart of 8 8-digit microcontrollers;
Fig. 2 is the sequential chart of 8 8-digit microcontrollers;
Fig. 3 is the instruction execution graph of 8 8-digit microcontrollers.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is done more detailed explanation.
The present invention adopts the inside and outside data-carrier store of sheet to unify addressing, the unified numbering of the register address of microcontroller kernel and microcontroller peripheral, and all operations such as read-write are also just the same, and speed improves a lot when reading the external data random access memory like this.
The present invention adopts the reduced instruction structure set, guarantees original function again when shortening instruction length.Instruction set of the present invention comprises 60 instructions, and every instruction length is 16, is divided into logical operation operational order, arithmetical operation operational order, data transfer operation instruction, other operational orders according to the function of instructing.Described other operational orders comprise that conditional transfer, bit manipulation, the program storage page are selected, the data-carrier store page is selected, enters sleep pattern, returned and interrupt return instruction, have formed the complete instruction set of a cover.
Described instruction set comprises 9 logical operation operational orders.When described instruction is carried out, the operand in the instruction is carried out corresponding logical operation according to the result of instruction decode, the result is written back in the destination register.
Described instruction set comprises 27 arithmetical operation operational orders.When described instruction is carried out, the operand in the instruction is carried out corresponding arithmetical operation according to the result of instruction decode, the result is written back in the destination register.Instruction then judges whether to satisfy the redirect condition according to operation result for judging transfer instruction as described, if satisfy the redirect condition then the numerical value of update routine counter, if do not satisfy the redirect condition then order execution bar instruction down.
Described instruction set comprises 8 data transfer operation instructions.When described instruction is carried out, source operand is reached in destination register or the storer according to the instruction decode result.
Comprise in other operational orders of described instruction set that 1 enters sleep pattern instruction SLEP, this instruction is used to stop the vibration of king oscillator.The major clock of circuit is not worked, and micro-controller instructions stops.
Comprise 1 house dog clear instruction WDTC in other operational orders of described instruction set, this instruction is used for the data zero clearing with the house dog register.
Comprise 1 unconditional jump instruction JUMP in described other operational orders, this instruction is used for the numerical value of reprogramming counter, gives programmable counter with the assignment of counting immediately in the instruction.
Comprise 1 table-look-up instruction MOVC#a in described other operational orders.When described instruction is carried out, 16 bit data of the program storage at a place, address of specified page are read, send into internal register then.If specified page just is not defaulted as current page, 16 bit data of internal processes reservoir are sent into internal register.
Comprise 1 table-look-up instruction MOVC R in described other operational orders.When described instruction is carried out, configure the address earlier, execution command is sent internal processes reservoir 16 bit data into internal register again.
Comprise link order RET and RETI in described other operations.When described RET instruction is carried out, go out stack operation, give programmable counter with 16 bit data assignment in the storehouse, program is returned from subroutine address, and stack pointer subtracts 1 simultaneously; When described RETI instruction is carried out, go out stack operation, give programmable counter with 16 bit data assignment in the storehouse, program is returned from interrupting subroutine address, and stack pointer subtracts 1 simultaneously.
Comprise locked memory pages selection instruction PAGE and BANK in described other operations.Described PAGE instruction is used for the program storage page to be selected, and described BANK instruction is used for the data-carrier store page and selects.
Fig. 1 is a structured flowchart of the present invention, the present invention includes data-carrier store and clock generator in ALU, command decoder, MUX, totalizer, programmable counter, program storage, the outer data-carrier store of sheet, the sheet.ALU is used for according to decode results operand being carried out corresponding arithmetic logical operation; Command decoder is used for the code stored by the translation program reservoir, carry out with decision add, subtract, operations such as multiplication and division, displacement, redirect, and provide the address of operand or directly provide and count immediately; MUX is used for selecting arithmetical logic operation necessary operations number according to the result of instruction decode; Totalizer is used for the special function register of the transmission exclusive disjunction of data; Programmable counter is the address of program storage; Program storage is used for the storage of data; The outer data-carrier store of sheet is used for the storage of the outer data of sheet; Data-carrier store in the sheet is used for the storage of data in the sheet; Clock generator, clock generator produces 4 phase clocks according to the microcontroller major clock.
As shown in Figure 1, specific implementation of the present invention is as follows:
Instruction fetch phase (ST_0): carried out instruction fetch operation when first clock period, (ST_0) was for high level.According to the program storage address that programmable counter points to, in program storage, take out the instruction that is about to execution.Result's decision after described programmable counter is deciphered by command decoder.If interrupt operation is arranged, will interrupt the entry address and send programmable counter to.If the binary cycle instruction is arranged, then program counter value remains unchanged in second period.If when jump instruction being arranged and satisfy the redirect condition, send jump address to programmable counter, and address pointer is stacked when preserving the current address if desired.When if link order or interrupt return instruction are arranged, with the processing of popping of the content program Counter Value in the storehouse; If no, then program counter value adds 1.
The decoding stage (ST_1): the second clock cycle deciphers when (ST_1) is for high level with the read data storage address and operates.The present invention adopts the inside and outside data-carrier store of sheet to unify the mode of addressing.At first by instruction decode as a result the decision operation number be immediately the number or data-carrier store in numerical value.If count immediately, in then directly will instructing back 8 as pending data; If operand is the numerical value in the data-carrier store, then back 9 of instruction promptly is the address of the data-carrier store of the addressing of wanting.Judge it is data-carrier store or the outer data-carrier store of sheet in the sheet according to the address of described data-carrier store.Then the data of data-carrier store are taken out as operand to be operated.During data-carrier store, with respect to the mode of non-unified addressing, speed has great raising to described disposal route outside the addressing sheet.
The arithmetic operation stage (ST_2): carried out arithmetic logical operation operation when the 3rd clock period, (ST_2) was for high level, operand is carried out operations such as arithmetic, logic, position and data transmission according to the result of decoder for decoding.The operand of arithmetic logical operation is the content of MUX output and the numerical value of totalizer, makes the result decision of which kind of arithmetic logical operation operation by command decoder decoding.
Write data storer, common work register or totalizer stage (ST_3): carried out write back operations when the 4th clock period, (ST_3) was for high level.Judge that according to result the result with ALU (arithmetical logic) operation writes back data-carrier store, common work register or totalizer to instruction decode.
In sum, mutually just 4 clock period have just been finished the execution of an ordinary instruction by 4.The specific conditions transfer instruction also is to need eight clock period because need the operation of condition judgment or two bytes so need two machine cycles.
Fig. 2 is a sequential chart of the present invention, and as shown in Figure 2, clk is a clock signal; Pwrite is a read-write control signal, and low level is for to carry out write operation to microcontroller peripheral, and high level is for to carry out read operation to microcontroller peripheral; Penable promptly enters microcontroller peripheral read-write state control signal for the read-write enable signal, and low level is effective; Ram_en is the data-carrier store enable signal, promptly enters data-carrier store read-write state control signal, and low level is effective; Ram_addr is the address bus of data-carrier store and microcontroller peripheral register; Dw is for carrying out the data bus of write operation to microcontroller peripheral; The data bus of dr_x for reading from microcontroller peripheral; Addr (rom) is the address of program storage; The content that Ins (rom) stores for program storage.
Read the microcontroller peripheral operation at first, saltus step takes place in address signal ram_addr, read-write control signal pwrite and read-write enable signal penable when rising edge clock.When read-write control signal pwrite is a high level, when read-write enable signal penable is low level, read the data in the microcontroller peripheral.The data of reading are only kept phase place of ST_2, so microcontroller must be deposited at register with the data of reading when the rising edge of the 4th clock period (ST_3).Microcontroller determines read to liking microcontroller peripheral, data-carrier store or internal register according to address signal ram_addr.
When microcontroller peripheral was carried out write operation, saltus step took place in address signal ram_addr, read-write control signal pwrite and read-write enable signal penable when rising edge clock.When read-write control signal pwrite and read-write enable signal penable are all low level the time, data are write peripheral hardware.The data that need write must be ready to before the ST_0 phase place, and kept a period of time after the ST_0 phase place.
The data storer is carried out read-write operation and microcontroller peripheral to be carried out read-write operation similar.When the data storer was carried out read operation, saltus step took place in address signal ram_addr, read-write control signal pwrite and data-carrier store enable signal ram_en when rising edge clock.When read-write control signal pwrite is a high level, when data-carrier store enable signal ram_en is low level, the data in the read data memory.The data of reading are only kept phase place of ST_2, and MCU must be deposited at register with the data of reading when the rising edge of the 4th clock period (ST_3).
When the data storer was carried out write operation, address signal ram_addr, read-write control signal pwrite and data-carrier store enable signal ram_en changed when rising edge clock.When read-write control signal pwrite is a low level, when data-carrier store enable signal ram_en also is low level simultaneously, data are write entry data memory.The data that need write must be ready to before the ST_0 phase place, and kept a period of time after the ST_0 phase place.
The present invention adopts 4 phase clocks at a high speed.
Fig. 3 is an instruction execution graph of the present invention.As shown in Figure 3, clock generator 9 provides first clock period (ST_0), second clock cycle (ST_1), the 3rd clock period (ST_2), the 4th clock period (ST_3) 4 phase clock signal, system finishes corresponding operation in the clock of correspondence, as follows:
Get and refer to operation: in first clock period (ST_0) is to finish from the operation of program storage 6 instruction fetch between high period.
Decoded operation: decipher for the instruction that will take out between high period in the second clock cycle (ST_1), and from data-carrier store read operation number.
The ALU operation: in the 3rd clock period (ST_2) is to carry out arithmetic operation between high period.
Write back operations: carry out write back operations in the 4th clock period (ST_3) between high period, the ALU result calculated is written back into data-carrier store or internal register.
In sum, an one-cycle instruction only needs 4 clock period promptly can finish, and the shortening of machine cycle has improved the efficient that instruction is carried out greatly.
The above is the specific embodiment of the present invention only, and is not used in qualification the present invention.Any replacement, combination, discrete all should being included within protection scope of the present invention of the present invention being made step well know in the art.
Claims (16)
1. 8-digit microcontroller, its structure comprises:
ALU is used for according to decode results operand being carried out corresponding arithmetic logical operation;
Command decoder is used for the code stored by the translation program reservoir, carry out with decision add, subtract, operations such as multiplication and division, displacement, redirect, and provide the address of operand or directly provide and count immediately;
MUX is used for selecting arithmetical logic operation necessary operations number according to the result of instruction decode;
Totalizer is used for the special function register of the transmission exclusive disjunction of data;
Programmable counter is the address of program storage;
Program storage is used for the storage of data;
The outer data-carrier store of sheet is used for the storage of the outer data of sheet;
Data-carrier store in the sheet is used for the storage of data in the sheet;
Clock generator, clock generator produces 4 phase clocks according to the microcontroller major clock;
It is characterized in that: ALU links to each other with data-carrier store in the sheet with totalizer, the outer data-carrier store of sheet respectively by data bus; MUX links to each other with ALU by data bus; Command decoder links to each other by the outer data-carrier store of data-carrier store in Ram address bus and the sheet and sheet, ALU is carried out logical operation control, and programmable counter is carried out the pointer counter controls; The programmable counter pointer links to each other with program storage by the Rom address bus; The outer data-carrier store of sheet links to each other with MUX by data bus with the interior data-carrier store of sheet; Clock generator acts on program storage in first clock period (ST_0), act on outside the sheet data-carrier store in the data-carrier store and sheet in the second clock cycle (ST_1), (ST_2) acts on ALU in the 3rd clock period, acts in totalizer, the sheet data-carrier store outside the data-carrier store and sheet in the 4th clock period (ST_3).
2. 8 8-digit microcontrollers as claimed in claim 1 is characterized in that: adopt the inside and outside data-carrier store of sheet to unify the mode of addressing.
3. 8 8-digit microcontrollers as claimed in claim 1 is characterized in that: adopt 4 phase clocks at a high speed, per 4 clock period are 1 machine cycle.
4. 8 8-digit microcontrollers as claimed in claim 1, it is characterized in that: the reduced instruction structure set of described 8 8-digit microcontrollers comprises 60 instructions, instruction length is 16, function according to instruction is divided into logical operation operational order, arithmetical operation operational order, data transfer operation instruction and other operational orders, and described other operational orders comprise that table-look-up instruction, conditional transfer, bit manipulation, the program storage page are selected, the data-carrier store page is selected, enters sleep pattern, returned and interrupt return instruction.
5. reduced instruction structure set as claimed in claim 4 is characterized in that: described reduced instruction set computer comprises the operand in the instruction is carried out the respective logic computing according to the result of instruction decode logical operation operational order.
6. reduced instruction structure set as claimed in claim 4 is characterized in that: described reduced instruction set computer comprises the operand in the instruction is carried out corresponding arithmetical operation according to the instruction decode result arithmetical operation operational order.
7. reduced instruction structure set as claimed in claim 4 is characterized in that: described reduced instruction set computer comprises source operand is reached data transfer operation instruction in order register or the storer according to the instruction decode result.
8. reduced instruction structure set as claimed in claim 4 is characterized in that: comprise in other operational orders of described reduced instruction set computer stop king oscillator vibration enter the sleep pattern instruction.
9. reduced instruction structure set as claimed in claim 4 is characterized in that: comprise the door dog clear instruction with the zero clearing of house dog register data in other operational orders of described reduced instruction set computer.
10. reduced instruction structure set as claimed in claim 4 is characterized in that: comprise the numerical value of reprogramming counter in other operational orders of described reduced instruction set computer, the several immediately assignment in the instruction are given the unconditional jump instruction of programmable counter.
11. reduced instruction structure set as claimed in claim 4 is characterized in that: comprise the table-look-up instruction of 16 bit data of program storage being read or internal processes reservoir 16 bit data are sent into internal register in other operational orders of described reduced instruction set computer.
12. reduced instruction structure set as claimed in claim 4 is characterized in that: comprise in other operational orders of described reduced instruction set computer and give programmable counter, simultaneously current programmable counter exponential quantity is added the transfer instruction of carrying out stacked processing after 1 with the random number assignment.
13. reduced instruction structure set as claimed in claim 4 is characterized in that: comprise in other operational orders of described reduced instruction set computer with program from subroutine address return or with program from interrupting the link order that subroutine address returns.
14. reduced instruction structure set as claimed in claim 4 is characterized in that: comprise locked memory pages selection instruction in other operational orders of described reduced instruction set computer with the program storage page is selected or the data-carrier store page is selected.
15. 8 8-digit microcontrollers as claimed in claim 1 is characterized in that: the highest frequency of 8 8-digit microcontrollers reaches 50MHZ.
16. 8 8-digit microcontrollers as claimed in claim 1 is characterized in that: the operating voltage of 8 8-digit microcontrollers is 2.6V-5.5V.
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| CNB2006101193558A CN100538623C (en) | 2006-12-08 | 2006-12-08 | A kind of 8 8-digit microcontrollers |
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| CNB2006101193558A CN100538623C (en) | 2006-12-08 | 2006-12-08 | A kind of 8 8-digit microcontrollers |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011109958A1 (en) * | 2010-03-10 | 2011-09-15 | 上海海尔集成电路有限公司 | Processing method of jump instructions and microcontroller |
| CN101853236B (en) * | 2010-02-05 | 2011-12-21 | 谭洪舟 | Microcontroller peripheral expansion method based on dual buses |
| CN106020017A (en) * | 2016-05-16 | 2016-10-12 | 深圳清华大学研究院 | Microcontroller and control method thereof |
| CN106648033A (en) * | 2017-01-03 | 2017-05-10 | 深圳市博巨兴实业发展有限公司 | Low-power-consumption microcontroller SOC |
| CN107844321A (en) * | 2016-09-21 | 2018-03-27 | 上海芯旺微电子技术有限公司 | A kind of MCU processing systems |
| CN111258644A (en) * | 2018-11-30 | 2020-06-09 | 上海寒武纪信息科技有限公司 | Data processing method, processor, data processing device and storage medium |
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2006
- 2006-12-08 CN CNB2006101193558A patent/CN100538623C/en active Active
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101853236B (en) * | 2010-02-05 | 2011-12-21 | 谭洪舟 | Microcontroller peripheral expansion method based on dual buses |
| WO2011109958A1 (en) * | 2010-03-10 | 2011-09-15 | 上海海尔集成电路有限公司 | Processing method of jump instructions and microcontroller |
| CN102193776A (en) * | 2010-03-10 | 2011-09-21 | 上海海尔集成电路有限公司 | Method for processing skip instruction and microcontroller |
| CN102193776B (en) * | 2010-03-10 | 2014-06-18 | 上海海尔集成电路有限公司 | Method for processing skip instruction and microcontroller |
| CN106020017A (en) * | 2016-05-16 | 2016-10-12 | 深圳清华大学研究院 | Microcontroller and control method thereof |
| CN106020017B (en) * | 2016-05-16 | 2019-02-01 | 深圳清华大学研究院 | Microcontroller and its control method |
| CN107844321A (en) * | 2016-09-21 | 2018-03-27 | 上海芯旺微电子技术有限公司 | A kind of MCU processing systems |
| CN106648033A (en) * | 2017-01-03 | 2017-05-10 | 深圳市博巨兴实业发展有限公司 | Low-power-consumption microcontroller SOC |
| CN111258644A (en) * | 2018-11-30 | 2020-06-09 | 上海寒武纪信息科技有限公司 | Data processing method, processor, data processing device and storage medium |
| CN111258644B (en) * | 2018-11-30 | 2022-08-09 | 上海寒武纪信息科技有限公司 | Data processing method, processor, data processing device and storage medium |
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|---|---|
| CN100538623C (en) | 2009-09-09 |
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Address after: 214135 -6, Linghu Avenue, Wuxi Taihu international science and Technology Park, Wuxi, Jiangsu, China, 180 Patentee after: China Resources micro integrated circuit (Wuxi) Co., Ltd Address before: 214000 information room, Wuxi New District, Jiangsu, China 301 Patentee before: WUXI CHINA RESOURCES SEMICO Co.,Ltd. |
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