CN111258644B

CN111258644B - Data processing method, processor, data processing device and storage medium

Info

Publication number: CN111258644B
Application number: CN201811457694.6A
Authority: CN
Inventors: 不公告发明人
Original assignee: Shanghai Cambricon Information Technology Co Ltd
Current assignee: Shanghai Cambricon Information Technology Co Ltd
Priority date: 2018-11-30
Filing date: 2018-11-30
Publication date: 2022-08-09
Anticipated expiration: 2038-11-30
Also published as: CN111258644A

Abstract

The application relates to a data processing method, a processor, a data processing device and a storage medium. The data processing method comprises the following steps: reading first subdata from a first storage device according to the operation instruction, storing the currently read first subdata into a second storage device, obtaining second subdata, adding the currently read first subdata and the second subdata to obtain a current operation result, storing the current operation result into the first storage device, and then returning to continuously read the first subdata from the first storage device until the relevant operation corresponding to the operation instruction is completed. The big data is divided into the small data to be subjected to circular operation processing, and the operand is circularly read according to the data reading capacity, so that the size of the data which can be accommodated during the operation processing meets the requirement, and the operation speed is accelerated.

Description

Data processing method, processor, data processing device and storage medium

Technical Field

The present application relates to the field of data processing technologies, and in particular, to a data processing method, a processor, a data processing apparatus, and a storage medium.

Background

Atomic operation refers to an operation that is not interrupted by a thread scheduling mechanism, and once the operation is started, the operation is run to the end, and no thread switching is performed in the middle (for example, the shared variable i performs accumulation, and the result of i + + is generated by multiple cores at the same time in the case of non-atomic operation, and the error occurs). In a multi-core processor system, a plurality of processor cores share the same memory space, and a common data transmission technology may not guarantee atomicity, that is, a plurality of processor cores may access the same address at the same time.

In an actual program, an operation result is stored in a memory space, the memory space has a certain address range, and since the memory space may be accessed by other processor cores before the operation is completed, the conventional method is to read data in the memory space to a memory unit, then store the operation result in the memory unit, and write the result of the memory unit back to the memory space after the instruction operation is completed. However, if other processor cores access the memory space during operation, an erroneous result is obtained, destroying the atomicity of the accumulation.

Disclosure of Invention

In view of the foregoing, it is desirable to provide a data processing method, a processor, a data processing apparatus, and a storage medium, which are capable of achieving independent access to an off-chip storage space during an atomic operation.

A method of data processing, the method comprising:

the method comprises the steps of obtaining an operation instruction, wherein the operation instruction is used for realizing addition operation of a first source operand and a second source operand, the first source operand comprises at least one first subdata, and the second source operand comprises at least one second subdata;

reading the first subdata from a first storage device according to data reading capacity and the operation instruction and a preset data reading mode, and storing the currently read first subdata into a second storage device, wherein the first storage device is an off-chip storage device, and the second storage device is an on-chip storage device;

acquiring the second subdata according to the operation instruction, adding the currently read first subdata and the second subdata to obtain a current operation result, and storing the current operation result into the second storage device and the first storage device;

and then, returning to the step of reading the first subdata from the first storage device according to the data reading capacity and the operation instruction and a preset data reading mode until the operation corresponding to the operation instruction is completed.

In one embodiment, each time the current operation result is stored in the first storage device, the method further comprises the following steps:

and controlling the counter to accumulate once or decrement once, and then returning to the step of reading the first subdata from the first storage device according to the data reading capacity and the operation instruction and a preset data reading mode until the counter accumulates to the target cycle number from an initial value or the counter decrements to the initial value from the target cycle number, so as to finish the operation corresponding to the operation instruction.

In one embodiment, the instruction format of the operation instruction comprises an instruction type, a first source operand, a second source operand, a target operand, and an opcode;

the instruction type is used for determining whether the operation instruction is an atomic operation instruction;

the instruction type is used for determining the operation type of the operation instruction;

the operation code is used for configuring the number of source operands;

the target operand is used for representing the current operation result.

A processor for use in a data processing method, the processor comprising an arithmetic circuitry, a read-write circuitry and a second storage means disposed adjacent the arithmetic circuitry, the second storage means being connectable by the read-write circuitry to a first storage means external to the processor;

the arithmetic circuit is used for acquiring an arithmetic instruction and sending a read-write request to the first storage device according to the arithmetic instruction;

the operation instruction is used for realizing addition operation of a first source operand and a second source operand, wherein the first source operand comprises at least one first subdata, and the second source operand comprises at least one second subdata;

the read-write circuit is used for reading first subdata from the first storage device according to the read-write request and storing the first subdata to the second storage device;

the arithmetic circuit is configured to obtain the second sub data, add the currently read first sub data and the second sub data to obtain a current arithmetic result, and store the current arithmetic result in the second storage device and the first storage device; and then, sending a read-write request to the first storage device again until the operation corresponding to the operation instruction is completed.

In one embodiment, the arithmetic circuit comprises a master processing circuit and more than one slave processing circuits, and the more than one slave processing circuits are all connected to the master processing circuit;

the addition operation module is arranged in the main processing circuit.

A computer-readable storage medium, on which a computer program is stored which, when executed by a processor, carries out the steps of:

According to the data processing method, the processor, the data processing device and the storage medium, according to an operation instruction, according to a preset data reading mode, reading first sub-data from a first storage device, storing the currently read first sub-data into a second storage device, then according to the operation instruction, obtaining second sub-data, adding the currently read first sub-data and the second sub-data to obtain a current operation result, storing the current operation result into the second storage device and the first storage device, and then returning to continue reading the first sub-data from the first storage device until a related operation corresponding to the operation instruction is completed. The data are read circularly and compared, the comparison result of each circulation is continuously stored in the first storage device, exclusive access to the first storage device is realized, other processor cores are prevented from accessing the first storage device, and atomicity of atomic operation is guaranteed. The arithmetic operation function of the processor is further expanded, and the operation efficiency during the atomic operation is improved by realizing exclusive access to the first storage device.

Drawings

FIG. 1 is a block diagram of a processor in one embodiment;

FIG. 2 is a block diagram of an embodiment of an operational module;

FIG. 3 is a schematic diagram of a processor according to another embodiment;

FIG. 4 is a schematic diagram of a processor according to another embodiment;

FIG. 5 is a schematic diagram of a processor according to another embodiment;

FIG. 6 is a flow diagram illustrating a data processing method according to one embodiment;

FIG. 7 is a flow chart illustrating a data processing method according to another embodiment;

FIG. 8 is a flowchart illustrating a method for instruction disassembly in accordance with another embodiment;

FIG. 9 is a flowchart illustrating step S300 according to an embodiment;

FIG. 10 is a flowchart illustrating step S300 according to another embodiment;

FIG. 11 is a schematic flow chart of the Atomic ADD method in one embodiment;

FIG. 12 is a block diagram showing the structure of a data processing apparatus according to an embodiment;

FIG. 13 is a block diagram of an instruction disassembly apparatus according to an embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

The terms "first," "second," and "third," etc. in the description and claims of this application and in the accompanying drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus. Off-chip refers to the outside of the processor, i.e., off-chip memory means a memory device disposed outside the processor; on-chip refers to the inside of the processor, i.e. on-chip memory means refers to memory means arranged inside the processor.

The data processing method provided by the present application can be applied to the processor 1000 shown in fig. 1. The processor 1000 includes an arithmetic circuit 12, a read/write circuit 203, and a second storage device 201. The second storage means 201 may be a buffer and/or a register arranged inside the processor 1000. The second storage device 201 may be connected to the first storage device 13 provided outside the processor 1000 through the read-write circuit 203. The first storage device 13 and the second storage device 201 may be a non-volatile memory or a volatile memory, and are not limited herein. The read and write circuits 203 may be I/O circuits.

The operation circuit 12 and the read/write circuit 203 can be connected to the second storage device 201, respectively, and the read/write circuit 203 can be connected to the first storage device 13. The second storage device 201 can be connected to the first storage device 13 outside the processor 1000 via the read/write circuit 203. The second storage device 201 can read the first source operand from the first storage device 13 through the read-write circuit 203 and transmit the first source operand to the operation circuit 12 for operation. The arithmetic circuit 12 may store the obtained arithmetic result and the intermediate arithmetic result in the second storage device 201, and the second storage device 201 may write the arithmetic result back to the first storage device 13 through the read/write circuit 203. In the embodiment of the present application, the intermediate operation result is continuously written back from the second storage device 201 to the first storage device 13 outside the processor 1000, so that the operation circuit 12 can exclusively use the first storage device 13, and the atomicity of the operation and the accuracy of the operation result can be ensured.

The arithmetic circuit 12 is configured to receive an arithmetic instruction, analyze the arithmetic instruction, and implement a corresponding arithmetic operation according to the arithmetic instruction. Optionally, the operation instruction may have a specific instruction format, and the operation circuit may analyze the instruction format according to the operation instruction to obtain instruction information such as an instruction type, a source operand, and an operation code of the operation instruction, so as to implement a corresponding operation according to the operation instruction.

Alternatively, the operation instruction in the embodiment of the present application may be an atomic operation instruction, and as shown in table 1 below, the instruction format of the operation instruction may include an instruction type Name, an instruction type Op, a first source operand, a second source operand, a destination operand Dst, an opcode Src Op, and the like.

The instruction type Name is used for determining the type of the instruction (the type of the instruction includes an atomic operation instruction and other common operation instructions), that is, the instruction type is used for determining whether the operation instruction is an atomic operation instruction. The instruction type Op is used to determine an operation type of the operation instruction, and the operation type is used to indicate what operation is performed by the operation instruction to distinguish specific functions of the operation, for example, the operation type may be an accumulation operation, a decrement operation, a maximum operation, a minimum operation, a logical and operation, a logical or operation, a logical xor operation, a substitution operation, a swap operation, and the like. The operation code Src Op is used to configure the number of source operands involved in the operation instruction. The target operand dstaddr is used to indicate a current operation result obtained after at least one source operand is operated, specifically, the target operand dstaddr may refer to a storage address of the current comparison result, and an operation result corresponding to the operation instruction may be stored in a storage space indicated by the storage address corresponding to the dstaddr. The first and second source operands may represent data participating in an operation, the first source operand may be data stored on the off-chip first storage means 13, i.e. the first source operand may represent data stored in the address Src0 addr. The second source operand may represent data stored in an address in an immediate or instruction.

Further, the instruction format of the operation instruction may further include an identification bit Src1vec for identifying whether the source operand a is an immediate or an address, and an identification bit Src2vec for identifying whether the source operand B is an immediate or an address.

Specifically, when Src1vec is 0, it indicates that the source operand a is an immediate number, and when Src1vec is 1, it indicates that the source operand a is data stored in an address; when Src2vec is 0, it indicates that the source operand B is an immediate number, and when Src2vec is 1, it indicates that the source operand B is data stored in an address.

Furthermore, the instruction format of the arithmetic instruction further includes a Data size Data for indicating the first source operand and a Data stream IO config for requesting the splitting and identifying the target loop times.

The instruction format of the operation instruction may be as follows, as shown in table 1:

where Src0addr represents the address of the first source operand and dstaddr represents the storage address of the target operand.

In one embodiment, the source operand A or the source operand B is used as the second source operand according to the operation instruction.

Optionally, the second source operand includes source operand A (Src1), source operand B (Src2), source operand A selected identification bits, and source operand B selected identification bits. Specifically, when the selected identification bit of the source operand A is valid, the source operand A is taken as a second source operand; and when the selected identification bit of the source operand B is valid, using the source operand B as a second source operand. When the selected identification bit of the source operand A is valid and the selected identification bit of the source operand B is valid, the source operand A and the source operand B can be simultaneously used as second source operands, and the number of the second source operands is two. Further, the bit width of the operation code Scr Op may include 3 bits, where 2 bits are used to distinguish the number of source operands participating in the operation, and 1 bit is used to select the source operand a (Src1) and/or the source operand B (Src2) as the second source operand to participate in the operation. Reference may be made to table 2:

source operand	Op
		Src0	000
Src0、Src1	010
		Src0、Src2	011
Src0、Src1、Src2	100

When the operation code Scr Op is "000", it indicates that the source operand of the operation instruction is 1, which is the first source operand Src 0. When the opcode Scr Op is "010", it indicates that the source operands of the operation instruction are 2, including the first source operand Src0 and the second source operand, and the selected identification bit of the source operand a is valid, and the second source operand is the source operand a (Src 1). When the opcode Scr Op is "011", it indicates that the source operands of the operation instruction are 2, including the first source operand Src0 and the second source operand, and the selected identification bit of the source operand B is valid, and the second source operand is the source operand B (Src 2). When the opcode Scr Op is "100", it indicates that the source operands of the operation instruction are 3, including the first source operand Src0, the source operand a (Src1), and the source operand B (Src 2).

In the embodiment of the present application, it may be default that the first source operand Src0 is always valid.

Optionally, the Data Type represents a Data Type, and the instruction supports, but is not limited to, the following Data types:

data type	Data Type
		Int16	000
Uint16	001
		Int32	010
Uint32	011

Optionally, the operation instruction may include an arithmetic operation instruction, and may also include a logic operation instruction: the arithmetic operation instruction may include: the system comprises a monocular maximum value operation instruction Atomic MAX _ SCALAR, a monocular minimum value operation instruction Atomic MIN _ SCALAR, a binocular maximum value operation instruction Atomic MAX _ VEC, a binocular minimum value operation instruction Atomic MIN _ VEC, a replacement operation instruction Atomic CAS, an exchange operation instruction Atomic EXCH, an addition operation instruction Atomic ADD, an accumulation operation instruction Atomic INC and a subtraction operation instruction Atomic DEC. The logical operation instruction may include: the logical AND operation instruction Atomic AND, the logical OR operation instruction Atomic OR, the logical XOR operation instruction Atomic XOR, AND the logical NOT operation instruction Atomic NOT.

The monocular maximum value operation instruction Atomic MAX _ SCALAR is used for solving the maximum value of the plurality of first subdata in the first source operand.

And the monocular minimum value operation instruction Atomic MIN _ SCALAR is used for solving the minimum value of the plurality of first subdata in the first source operand.

The binary maximum value operation instruction Atomic MAX _ VEC is used for calculating the maximum value of the first source operand and the second source operand.

The binary minimum value operation instruction Atomic MIN _ VEC is used for calculating the minimum value of the first source operand and the second source operand.

The ADD operation instruction Atomic ADD is used for adding a first source operand and a second source operand.

And the accumulation operation instruction Atomic INC is used for performing accumulation operation between the first source operand and the second source operand.

A subtraction instruction Atomic DEC for performing a subtraction operation between a first source operand and a second source operand.

AND the logic AND operation instruction Atomic AND is used for carrying out AND logic operation between the first source operand AND the second source operand.

The logical OR instruction Atomic OR is used for carrying out logical OR operation between the first source operand and the second source operand.

And the logic exclusive-OR operation instruction Atomic XOR is used for performing logic exclusive-OR operation between the first source operand and the second source operand.

And the logic NOT instruction Atomic NOT is used for carrying out NOT operation between the first source operand and the second source operand.

The replacement operation instruction Atomic CAS is used for replacing among the first source operand, the second source operand and the third source operand.

The system comprises an exchange operation instruction Atomic EXCH and an operation instruction used for exchanging between a first source operand and a second source operand.

In the embodiment of the present application, to ensure atomicity of operation, the operation instruction may be implemented by dividing the same operation into multiple sub-operations, and the exclusive ownership of the first storage device is implemented by continuously writing back the intermediate calculation result to the first storage device.

Specifically, the first source operand includes at least one first subdata, the arithmetic circuit 12 receives an arithmetic instruction, sends a read-write request to the first storage device 13 according to the arithmetic instruction, the read-write circuit 203 reads the first subdata from the first storage device 13 according to the read-write request and stores the first subdata into the second storage device 201 according to a data reading mode, the arithmetic circuit 12 obtains the second source operand according to the arithmetic instruction, executes an arithmetic operation to obtain a current arithmetic result, stores the obtained current arithmetic result into the second storage device 201, and stores the current arithmetic result of the second storage device 201 into the first storage device 13 through the read-write circuit 203. After that, the arithmetic circuit 12 may send a read/write request to the first storage device 13 again to read the first sub-data from the first storage device 13 again, and execute the arithmetic operation for multiple times in a loop until the arithmetic operation corresponding to the arithmetic instruction is completed.

Optionally, the processor may further comprise a counter, which may be connected to the arithmetic circuitry 12, for recording a target number of cycles of the arithmetic instruction. Specifically, each time the read/write circuit 203 stores the current operation result of the second storage device 201 in the first storage device 13, the operation circuit 12 may control the counter to increment once, and send the read/write request to the first storage device 13 again until the counter is incremented from the initial value to the target cycle number. In this embodiment, the initial value of the counter may be 0, that is, when the counter is incremented from 0 to the target cycle number, the corresponding operation of the operation instruction is completed. Alternatively, the arithmetic circuit 12 may control the counter to decrement once, and send the read/write request to the first storage device 13 again until the counter is decremented from the target number of cycles to the initial value. In this embodiment, the initial value of the counter may be 0, that is, when the counter is decremented from the target cycle number to 0, the corresponding operation of the operation instruction is completed.

Further, the arithmetic circuit 12 may be provided with an arithmetic module corresponding to each arithmetic instruction. Specifically, referring to fig. 2, the arithmetic circuit 12 may include a binoculus maximum value operation module 121, a binoculus minimum value operation module 122, a logical and operation module 123, a logical or operation module 124, a logical exclusive-or operation module 125, an exchange operation module 126, a replacement operation module 127, a monocular maximum value operation module 128, a monocular minimum value operation module 129, an addition operation module 130, an accumulation operation module 131, a subtraction operation module 132, a logical not operation module 133, and the like.

The two-purpose maximum value operation module 121 is configured to implement the operation of the two-purpose maximum value operation instruction Atomic MAX _ VEC, that is, to implement the maximum value operation of the first source operand and the second source operand.

The binary minimum operation module 122 is configured to implement the operation of the binary minimum operation instruction Atomic MIN _ VEC, that is, to implement the minimum operation of the first source operand and the second source operand.

The AND logic module 123 is configured to implement the operation of the AND logic instruction Atomic AND, that is, to implement the AND logic operation between the first source operand AND the second source operand.

The OR logic module 124 is configured to implement the operation of the above-mentioned OR logic instruction Atomic OR, that is, to implement a logical OR operation between the first source operand and the second source operand.

The XOR operation module 125 is configured to implement the operation of the above XOR operation instruction Atomic XOR, that is, to implement a XOR operation between the first source operand and the second source operand.

The swap operation module 126 is used to implement the operation of the swap operation instruction Atomic EXCH, i.e. the swap operation between the first source operand and the second source operand.

The replacement operation module 127 is configured to implement the operation of the replacement operation instruction Atomic CAS, that is, to implement the replacement operation among the first source operand, the second source operand, and the third source operand.

The monocular maximum value operation module 128 is configured to implement the operation of the above-mentioned monocular maximum value operation instruction Atomic MAX _ SCALAR, that is, to implement the maximum value operation of the plurality of first sub-data in the first source operand.

The monocular minimum value operation module 129 is configured to implement the operation of the above-mentioned monocular minimum value operation instruction Atomic MIN _ SCALAR, that is, to implement the minimum value operation of the plurality of first sub-data in the first source operand.

The addition operation module 130 is configured to implement the operation of the above-mentioned addition operation instruction Atomic ADD, that is, to implement the operation of adding the first source operand and the second source operand.

The accumulation operation module 131 is configured to implement the operation of the accumulation operation instruction Atomic INC, that is, to implement the operation of accumulating between the first source operand and the second source operand.

The subtraction module 132 is configured to implement the operation of the subtraction instruction Atomic DEC, that is, to implement the subtraction operation between the first source operand and the second source operand.

The logical NOT operation module 133 is configured to implement the operation of the above-mentioned logical NOT operation instruction Atomic NOT, that is, to implement a logical NOT operation between the first source operand and the second source operand.

Alternatively, each operation module may include an operation unit and a result output unit connected to the operation unit. The operation unit is used for executing specific operation steps, and the result output unit is used for taking the result obtained in the operation steps as the current operation result.

Further, as shown in fig. 1 and 2, the processor may further include a data selector 14, and the data selector 14 is connected between the arithmetic circuit 12 and the read-write circuit 203. The data selector 14 is configured to gate the connection paths between the operation blocks in the operation circuit 12 and the read/write circuit 203. For example, if the operation command is an Atomic MAX _ VEC, the data selector 14 is used to gate the connection path between the binary maximum operation module 121 and the read/write circuit 203. At this time, the maximum two-entry operation module 121 is configured to obtain the second subdata, determine whether the currently read first subdata is greater than or equal to the second subdata according to the operation instruction, store the obtained current comparison result in the second storage device 201, and store the current comparison result of the second storage device 201 in the first storage device 13 through the read/write circuit 203 and the data selector 14.

If the operation command is an Atomic MIN _ VEC, the data selector 14 is configured to gate a connection path between the minimum two-way operation module 122 and the read/write circuit 203. At this time, the two-entry minimum value operation module 122 is configured to obtain the second sub data, determine whether the currently read first sub data is smaller than the second sub data according to the operation instruction, store the obtained current comparison result in the second storage device 201, and store the current comparison result of the second storage device 201 in the first storage device 13 through the read/write circuit 203 and the data selector 14.

If the operation instruction is an AND operation instruction Atomic AND, the data selector 14 is configured to gate a connection path between the AND operation block 123 AND the read/write circuit 203. At this time, the and logic module 123 is configured to obtain the second sub-data, perform and logic operation on the currently read first sub-data and second sub-data according to the operation instruction, store the obtained current operation result in the second storage device 201, and store the current operation result of the second storage device 201 in the first storage device 13 through the read/write circuit 203 and the data selector 14.

If the operation instruction is an and operation instruction Atomic OR, the data selector 14 is configured to gate the connection path between the OR operation module 124 and the read/write circuit 203. At this time, the or logic module 124 is configured to obtain the second sub data, perform a or logic operation on the currently read first sub data and second sub data according to the operation instruction, store the obtained current operation result in the second storage device 201, and store the current operation result of the second storage device 201 in the first storage device 13 through the read/write circuit 203 and the data selector 14.

If the operation instruction is the logical and operation instruction Atomic XOR, the data selector 14 is configured to gate the connection path between the logical exclusive-or operation module 125 and the read/write circuit 203. At this time, the xor operation module 125 is configured to obtain the second sub data, perform xor operation on the currently read first sub data and second sub data according to the operation instruction, store the obtained current operation result in the second storage device 201, and store the current operation result of the second storage device 201 in the first storage device 13 through the read/write circuit 203 and the data selector 14.

If the operation instruction is the replacement operation instruction Atomic CAS, the data selector 14 is used for gating the connection path between the replacement operation module 127 and the read/write circuit 203. At this time, the replacement operation module 127 is configured to obtain the second sub-data and the third sub-data, perform replacement operation on the currently read first sub-data, second sub-data, and third sub-data according to the operation instruction, store the obtained current operation result in the second storage device 201, and store the current operation result of the second storage device 201 in the first storage device 13 through the read/write circuit 203 and the data selector 14.

If the operation instruction is an exchange operation instruction Atomic EXCH, the data selector 14 is used for gating the connection path between the exchange operation module 126 and the read/write circuit 203. At this time, the exchange operation module 126 is configured to obtain the second sub data, perform an exchange operation on the currently read first sub data and second sub data according to the operation instruction, store the obtained current operation result in the second storage device 201, and store the current operation result of the second storage device 201 in the first storage device 13 through the read/write circuit 203 and the data selector 14.

If the operation command is the monocular maximum value operation command Atomic MAX _ SCALAR, the data selector 14 is configured to gate the connection path between the monocular maximum value operation module 128 and the read/write circuit 203. At this time, the monocular maximum value operation module 128 is configured to compare N pieces of sub data in the sub data segments of the source operand one by one to obtain a maximum value of the N pieces of sub data, store the maximum value as a current comparison result in the second storage device 201, and store the current comparison result of the second storage device 201 in the first storage device 13 through the read/write circuit 203 and the data selector 14.

If the operation command is the monocular minimum value operation command Atomic MIN _ SCALAR, the data selector 14 is configured to gate the connection path between the monocular minimum value operation module 129 and the read/write circuit 203. At this time, the monocular minimum value operation module 129 is configured to compare the N pieces of sub data in the sub data segments of the source operand one by one to obtain a minimum value of the N pieces of sub data, store the minimum value as a current comparison result in the second storage device 201, and store the current comparison result of the second storage device 201 in the first storage device 13 through the read/write circuit 203 and the data selector 14.

If the operation instruction is an addition operation instruction Atomic ADD, the data selector 14 is configured to gate a connection path between the addition operation module 130 and the read/write circuit 203. At this time, the addition operation module 130 is configured to obtain the second sub data, add the currently read first sub data and the second sub data according to the operation instruction to obtain a current operation result, store the current operation result in the second storage device 201, and store the current operation result of the second storage device 201 in the first storage device 13 through the read/write circuit 203 and the data selector 14.

If the operation instruction is an accumulation operation instruction Atomic INC, the data selector 14 is configured to gate a connection path between the accumulation operation module 131 and the read/write circuit 203. At this time, the accumulation operation module 131 is configured to obtain the second sub-data, determine whether the currently read first sub-data is greater than or equal to the second sub-data according to the operation instruction, reset the first sub-data when the first sub-data is greater than or equal to the second sub-data, store the reset first sub-data as a current comparison result in the second storage device 201, and store the current comparison result of the second storage device 201 in the first storage device 13 through the read-write circuit 203 and the data selector 14.

If the operation instruction is the subtraction instruction Atomic DEC, the data selector 14 is configured to gate a connection path between the subtraction module 132 and the read/write circuit 203. At this time, the subtraction module 132 is configured to obtain second sub-data, determine whether the currently read first sub-data is larger than the second sub-data according to the operation instruction, and store the second sub-data as a current comparison result in the second storage device 201 when the first sub-data is larger than the second sub-data; when the first subdata is smaller than or equal to the second subdata, subtracting the first subdata from the first preset value, storing the subtracted first subdata into the second storage device 201 as a current comparison result, and storing the current comparison result of the second storage device 201 into the first storage device 13 through the read-write circuit 203 and the data selector 14.

If the operation instruction is an Atomic NOT instruction, the data selector 14 is configured to gate a connection path between the logical NOT operation module 133 and the read/write circuit 203. At this time, the logical negation operation module 133 is configured to obtain the second sub data, perform a logical negation operation on the currently read first sub data and second sub data according to the operation instruction, store the obtained current operation result in the second storage device 201, and store the current operation result of the second storage device 201 in the first storage device 13 through the read/write circuit 203 and the data selector 14.

In one embodiment, with continued reference to fig. 3-5, the second memory device 201 and the read/write circuit 203 may be packaged as a memory circuit 10. The arithmetic circuit 12 includes a master processing circuit 101 and at least one slave processing circuit 102, the at least one slave processing circuit 102 each being connected to the master processing circuit 101, the master processing circuit 101 being connected to a branch processing circuit(s) 103, the branch processing circuit 103 being connected to the one or more slave processing circuits 102; the branch processing circuit 103 is configured to execute forwarding of data or instructions between the master processing circuit 101 and the slave processing circuit 102. The main processing circuit 101 is used for performing preamble processing on a source operand and transmitting data and an operation instruction with a plurality of slave processing circuits; the plurality of slave processing circuits 102 are configured to perform an intermediate operation in parallel according to the data and the operation instruction transmitted from the master processing circuit to obtain a plurality of intermediate results, and transmit the plurality of intermediate results to the master processing circuit; the main processing circuit 101 is configured to perform subsequent processing on the plurality of intermediate results to obtain a calculation result of the calculation instruction.

The main processing circuit 101 may include the aforementioned two-purpose maximum operation module 121, two-purpose minimum operation module 122, logical and operation module 123, logical or operation module 124, logical exclusive or operation module 125, replacement operation module 126, swap operation module 127, one-purpose maximum operation module 128, one-purpose minimum operation module 129, addition operation module 130, accumulation operation module 131, subtraction operation module 132, and logical not operation module 133. The data selector 14 described above may be connected between the main processing circuit 101 and the read/write circuit 203.

In one embodiment, the processor may further include a controller circuit 11, the controller circuit 11 including: instruction cache circuitry 110, instruction processing circuitry 111 and store queue circuitry 113.

The instruction cache circuit 110 is configured to store a calculation instruction associated with an artificial neural network operation.

The instruction processing circuit 111 is configured to analyze the calculation instruction to obtain a plurality of operation instructions.

A store queue circuit 113 for storing an instruction queue, the instruction queue comprising: and a plurality of operation instructions or calculation instructions to be executed according to the front and back sequence of the queue.

Further, the controller circuit 11 may include a split granularity circuit 114, a cycle number processing circuit 115, and a data read capacity calculation circuit 116.

The split granularity circuit 114 is connected to the cycle number processing circuit 115, the cycle number processing circuit 115 is connected to the instruction processing circuit 111 and the data reading capacity calculation circuit 116, the data reading capacity calculation circuit 116 is connected to the operation circuit 12, and the second storage device 201 can be connected to the first storage device 13 outside the processor through the read/write circuit 203.

The instruction processing circuit 111 is configured to obtain an operation instruction, parse the data size of the first source operand according to the operation instruction, and transmit the data size of the first source operand to the loop number processing circuit 115.

The split granularity circuit 114 is used to store a preset split granularity. In this embodiment, the split-granularity circuit 114 may be a buffer or a segment of a storage space in the second storage device, for example, the split-granularity circuit 114 may be a storage space corresponding to a specified address interval in the second storage device.

The cycle number processing circuit 115 is configured to obtain a target cycle number according to the size of the first operand and a preset splitting granularity, and transmit the target cycle number to the operation circuit 12. In this embodiment, the loop number processing circuit 115 may be a counter.

The data reading capacity calculation circuit 116 is configured to obtain a data reading capacity according to the size of the first operand and a preset splitting granularity, and transmit the data reading capacity to the operation circuit 12. The arithmetic circuit 12 is configured to send a read/write request to the first storage device 13 according to an arithmetic instruction to read first sub-data from the first storage device 13, where the size of the first sub-data is equal to the data reading capacity. After that, the operation circuit 12 may perform an operation according to the read first sub data and second sub data, and after the current operation is completed, the cycle number processing circuit 115 increments the target cycle number once from the initial value, and sends the read/write request to the first storage device 13 again until the counter increments from the initial value to the target cycle number. In this embodiment, the initial value may be 0, that is, until the current cycle number is accumulated from 0 to the target cycle number, the corresponding operation of the operation instruction is completed. Alternatively, the loop count processing circuit 115 decrements the target loop count once, and transmits the read/write request to the first storage device 13 again until the target loop count is decremented to 0. Namely, when the current cycle number is decreased to 0, the corresponding operation of the operation instruction is completed.

In the embodiment, the data is split by adding the split granularity circuit 114, the cycle number processing circuit 115 and the data reading capacity calculation circuit 116, so that the size of the processed data is larger than the memory access bandwidth which can be accommodated in a single clock cycle.

Referring to fig. 6 or fig. 7, when receiving the operation instruction, the processor may perform the following steps:

s100, an operation instruction is obtained.

The operation instruction is used for realizing operation among source operands, and the first source operand comprises at least one first subdata.

And S200, reading the first subdata from the first storage device according to the data reading capacity and the operation instruction and a preset data reading mode, and storing the currently read first subdata into the second storage device.

The data reading capacity represents the number of data read at a time, and can be calculated. The first storage device 13 is an off-chip storage device and the second storage device 201 is an on-chip storage device. Specifically, after the arithmetic circuit 12 obtains the arithmetic instruction, it sends a read-write request to the first storage device 13 according to the arithmetic instruction, and then the read-write circuit 203 reads the first sub-data from the first storage device 13 according to the preset data reading mode and according to the read-write request, and stores the currently read first sub-data in the second storage device 201.

S300, executing operation according to the operation instruction, and storing the obtained current operation result into the second storage device and the first storage device.

Specifically, the arithmetic circuit 12 performs a corresponding arithmetic operation according to the obtained arithmetic instruction, so as to obtain a current arithmetic result, and then stores the obtained current arithmetic result in the second storage device 201, and then stores the current arithmetic result of the second storage device 201 in the first storage device 13 through the read/write circuit 203.

And S400, returning to the step of reading the first subdata from the first storage device according to the data reading capacity and the operation instruction and a preset data reading mode until the operation corresponding to the operation instruction is completed.

Specifically, step S400 may include: and controlling the counter to accumulate once or decrement once, and then returning to the step S200, reading the first subdata from the first storage device according to the operation instruction and the data reading capacity and a preset data reading mode until the counter is accumulated to the target cycle number from the initial value or the counter is decremented to the initial value from the target cycle number. In the embodiment of the present application, the initial value of the counter may be 0.

Further, the target number of cycles is calculated according to the data size of the first source operand. After the current operation result of the second storage device 201 is stored in the first storage device 13 through the read-write circuit 203, the counter is controlled to accumulate once, and then the first subdata is continuously read from the first storage device 13 according to the operation instruction and the data reading capacity until the counter is accumulated from 0 to the target cycle number. Or controls the counter to decrement once until the counter decrements the target number of cycles to 0, and stops reading the first sub data from the first storage device 13.

In another embodiment, referring to fig. 8, the data processing method may further include the following steps:

s500, an operation instruction is obtained, and the data size of the first source operand is analyzed according to the operation instruction.

Specifically, the instruction processing circuit 111 obtains the operation instruction, parses the data size of the first source operand according to the operation instruction, and sends the data size of the first source operand to the loop number processing circuit 115.

And S600, obtaining the cycle number and the data reading capacity according to the data size of the first source operand and the preset splitting granularity.

Specifically, the preset split granularity is stored in the split granularity circuit 114, which may be a certain storage space in the static memory on the chip. The cycle number processing circuit 115 receives the data size of the first source operand, and calculates the target cycle number according to the data size of the first source operand and the preset splitting granularity. The data read capacity calculation circuit 116 calculates the data read capacity according to the cycle count sent by the cycle count processing circuit 115, the data size of the first source operand sent by the instruction processing circuit 111, and the preset split granularity, and sends the data read capacity and the target cycle count to the operation circuit 12.

Alternatively, the loop number processing circuit 115 may calculate the target loop number according to the following formula:

wherein, Count is expressed as a target cycle number, data size is expressed as a data size of the first source operand, and the splitting granularity is a preset splitting granularity. In the embodiment of the application, the quotient obtained by dividing the data size by the preset splitting granularity is rounded up to obtain the target cycle number Count.

The data read capacity calculation circuit 116 may calculate the data read capacity according to the following formula:

data real size ═ min { unprocessed data size, split granularity }

The data real size represents data reading capacity, the splitting granularity is preset splitting granularity, and the unprocessed data size represents the data size of the first source operand minus the data reading capacity.

For example, the controller circuit 11 analyzes that the data size of the first source operand is 1000 bytes, the preset splitting granularity is 512 bytes, the number of cycles is 2, and the data reading capacities of the two times are 512 bytes and 488 bytes, respectively, according to the operation instruction.

Further, the data processing method may further include:

according to the operation instruction, the number of source operands included in the operation instruction is determined. Wherein the number of source operands may comprise one, two or three.

Specifically, the operation circuit 12 may perform the determination according to the operation code Scr Op in the operation instruction, and when the operation code Scr Op is "000", it indicates that the source operand of the operation instruction is 1, which is the first source operand Src 0. When the opcode Scr Op is "010", it indicates that the source operands of the operation instruction are 2, including the first source operand Src0 and the second source operand, and the second source operand is the source operand a (Src). When the opcode Scr Op is "011", it indicates that the source operands of the operation instruction are 2, including the first source operand Src0 and the second source operand, and the second source operand is source operand B (Src 2). When the opcode Scr Op is "100", it indicates that the source operands of the operation instruction are 3, including the first source operand Src0, the source operand a (Src) and the source operand B (Src 2).

Optionally, when there is one source operand, the step S300 may further include the following steps:

and executing the operation according to the operation instruction and the sub-data segment, and storing the obtained current operation result/comparison result into the second storage device and the first storage device.

Specifically, the arithmetic circuit 12 executes corresponding operations according to the received instructions and the sub-data segments to obtain current operation results/comparison results, stores the obtained current operation results/comparison results in the second storage device 201, and stores the current operation results/comparison results in the second storage device 201 in the first storage device 13 through the read/write circuit 203.

Specifically, when the number of the source operands is one, the operation instruction may be a monocular maximum value operation instruction Atomic MAX _ SCALAR, a monocular minimum value operation instruction Atomic MIN _ SCALAR, a logical NOT operation instruction Atomic NOT, and the like, and the specific execution process of each operation instruction may specifically refer to the above description.

Optionally, when the number of the source operands is two, referring to fig. 9 together, the two source operands are a first source operand and a second source operand, respectively, the step S300 may further include the following steps:

s310, acquiring second subdata according to the operation instruction.

Specifically, two source operands participating in the operation are determined according to the operation instruction, and the operation circuit 12 obtains the second sub-data according to the operation instruction.

And S320, executing operation according to the operation instruction, the first subdata and the second subdata, and storing the obtained current operation result into a second storage device and a first storage device.

Specifically, the arithmetic circuit 12 executes corresponding operations according to the received instruction, the first sub-data and the second sub-data, obtains a current arithmetic result, stores the obtained current arithmetic result in the second storage device 201, and stores the current arithmetic result in the second storage device 201 in the first storage device 13 through the read/write circuit 203.

Specifically, when the number of the source operands is two, the operation instruction may be an Atomic maximum operation instruction Atomic MAX _ VEC, an Atomic minimum operation instruction Atomic MIN _ VEC, an Atomic AND operation instruction Atomic AND, an Atomic OR operation instruction Atomic OR, an exclusive OR operation instruction Atomic XOR, an exchanging operation instruction Atomic EXCH, an adding operation instruction Atomic ADD, an accumulating operation instruction Atomic INC, a subtracting operation instruction Atomic DEC, AND the like, AND the specific execution process of each operation instruction is described above.

Optionally, when the number of the source operands is three, referring to fig. 10, the three source operands are a first source operand, a second source operand, and a third source operand, respectively, the step S300 may further include the following steps:

s330, acquiring the second sub data and the third sub data according to the operation instruction.

Wherein the third source operand includes at least one third child data.

Specifically, three source operands participating in the operation are determined according to the operation instruction, and the operation circuit 12 obtains the second sub data and the third sub data according to the operation instruction.

And S340, executing operation according to the operation instruction, the first sub-data, the second sub-data and the third sub-data, and storing the obtained current operation result into the second storage device and the first storage device.

Specifically, the arithmetic circuit 12 executes corresponding operations according to the received instruction, the first sub-data, the second sub-data, and the third sub-data, obtains a current operation result, stores the obtained current operation result in the second storage device 201, and stores the current operation result in the second storage device 201 in the first storage device 13 through the read/write circuit 203.

In one embodiment, the source operand A or the source operand B is used as the second source operand according to the instruction format of the operation instruction.

Specifically, referring to the format of Src Op in table 2, when Src Op in the received operation instruction is 010, which indicates that the source operand a is valid, the source operand a is used as the second source operand; when Src Op in the received operation instruction corresponds to 011, indicating that source operand B is valid, and using source operand B as a second source operand; when Src Op in the received operation instruction corresponds to 100, which indicates that source operand a is valid and source operand B is valid, source operand a is used as the second source operand and source operand B is used as the third source operand.

In this embodiment, the source operand a or the source operand B is selected as the second source operand for selection according to the format of the operation code Src Op in the instruction format.

Specifically, when the above operation instruction is Atomic ADD, the data processing method shown in fig. 11 may include the following steps:

s932, an operation instruction is acquired.

The operation instruction is used for realizing an addition operation between a first source operand and a second source operand, wherein the first source operand comprises at least one first subdata, and the second source operand comprises at least one second subdata.

Specifically, the arithmetic circuit 12 obtains an arithmetic instruction for implementing an addition operation between a first source operand and a second source operand.

And S934, reading the first subdata from the first storage device according to the data reading capacity and the operation instruction and a preset data reading mode, and storing the currently read first subdata to the second storage device.

The first storage device 13 is an off-chip storage device, and the second storage device 201 is an on-chip storage device.

Specifically, after the arithmetic circuit 12 obtains the arithmetic instruction, it sends a read-write request to the first storage device 13 according to the arithmetic instruction and the data reading capacity, and then the read-write circuit 203 reads the first sub-data from the first storage device 13 according to the read-write request in a preset data reading manner, and stores the currently read first sub-data in the second storage device 201.

S936, obtaining second subdata according to the operation instruction, adding the currently read first subdata and the second subdata to obtain a current operation result, and storing the current operation result into the second storage device and the first storage device.

And the number of the obtained second sub-data is equal to that of the currently read first sub-data.

Specifically, the arithmetic circuit 12 obtains second sub-data required for addition operation according to the obtained arithmetic instruction, adds the currently read first sub-data and the second sub-data to obtain a current arithmetic result after obtaining the second sub-data, stores the obtained current arithmetic result in the second storage device 201, and stores the current arithmetic result in the first storage device 13 through the read-write circuit 203.

And S938, returning to the step of reading the first subdata from the first storage device according to the data reading capacity and the operation instruction and the preset data reading mode until the operation corresponding to the operation instruction is completed.

Specifically, step S938 may include: and controlling the counter to accumulate once or decrement once, and then returning to the step S934, reading the first subdata from the first storage device according to the operation instruction and the data reading capacity and a preset data reading mode until the counter is accumulated to the target cycle number from the initial value or the counter is decremented to the initial value from the target cycle number. In the embodiment of the present application, the initial value of the counter may be 0.

In one embodiment, the step S936 may further include:

and carrying out alignment addition on the currently read first subdata and the second subdata to obtain a current operation result.

Specifically, after acquiring the first sub-data and the second sub-data, the arithmetic circuit 12 obtains a first sub-data set and a second sub-data set, where a plurality of first sub-data in the first sub-data set are sequentially arranged; the plurality of second sub-data in the second sub-data set are sequentially arranged. And comparing the currently read first subdata with the second subdata, namely adding the first subdata in the first subdata set and the second subdata with corresponding sequence numbers in the second subdata set according to the sequence numbers of the arrangement sequence.

For example, the currently read first sub-data and second sub-data are multiple data, where the first sub-data has a of {1, 2, 3, 4, 5, 6, 7, 8}, and the second sub-data has b of {0, 3, 4, 5, 2, 1, 7, 2}, and each bit of the first sub-data in a is added to each bit of the second sub-data in b, that is, the first bit of the first sub-data 1 in a is added to the first bit of the second sub-data 0 in b to obtain a current operation result 1; and adding the second bit 2 in the a and the second bit 3 in the b to obtain a current operation result 5, and in the same way, after the first subdata in the a and the second subdata in the b are added, obtaining a current operation result of {1, 5, 7, 9, 7, 7, 14, 10 }.

In this embodiment, the first sub-data and the second sub-data are added in a bit-to-bit manner, and the current operation result is stored in the first storage device 11, so that the addition operation of the operation instruction is completed.

In one embodiment, with continued reference to fig. 8, an instruction unpacking method is provided and may include:

S600, obtaining target cycle times and data reading capacity according to the data size of the first source operand and preset splitting granularity.

The preset splitting granularity is stored in the splitting granularity circuit 114, and may be a certain storage space in the on-chip static memory.

Specifically, the cycle count processing circuit 115 receives the data size of the first source operand, and calculates the target cycle count according to the data size of the first source operand and the preset splitting granularity. The data reading capacity calculation circuit 116 calculates the data reading capacity according to the cycle count sent by the cycle count processing circuit 115, the data size of the first source operand sent by the instruction processing circuit 111, and the preset splitting granularity. And sends the data read capacity and the number of cycles to the arithmetic circuit 12.

Alternatively, the formula for calculating the target cycle number may be:

wherein, Count is expressed as a target cycle number, data size is expressed as a data size of the first source operand, and the splitting granularity is a preset splitting granularity.

The formula for calculating the data read capacity may be:

data real size ═ min { unprocessed data size, split granularity }

And S700, reading the first subdata from the first storage device according to the operation instruction and the data reading capacity and a preset data reading mode, and storing the currently read first subdata into the second storage device.

Specifically, the arithmetic circuit 12 receives the arithmetic instruction, initiates a read-write request to the first storage device 13 according to the arithmetic instruction and the data reading capacity, reads the first subdata from the first storage device 13 through the read-write circuit 203 according to a preset data reading mode, and stores the currently read first subdata into the second storage device 201.

And S800, executing operation according to the operation instruction, and storing the obtained current operation result into the second storage device and the first storage device.

Specifically, the arithmetic circuit 12 executes a corresponding arithmetic operation according to the received arithmetic instruction, obtains a current arithmetic result, stores the current arithmetic result in the second storage device 201, and stores the current arithmetic result in the second storage device 201 in the first storage device 13.

And S900, returning to the step of obtaining the target cycle number and the data reading capacity according to the data size of the first source operand and the preset splitting granularity until the current cycle number is equal to the initial value or the current cycle number is equal to the target cycle number, and finishing the operation corresponding to the operation instruction.

Specifically, the steps may include: and decreasing the target cycle number once or accumulating the target cycle number once from the initial value, returning to the step S600, and determining the data reading capacity according to the data size of the first operand and the preset splitting granularity until the target cycle number is decreased to the initial value or accumulated from the initial value to the target cycle number. In the embodiment of the present application, the initial value of the counter may be 0.

Further, after the arithmetic circuit 12 finishes executing the arithmetic operation and stores the current arithmetic result in the first storage device 13, the loop time processing circuit 115 decrements the target loop time by one time, and then continues to execute step S600 until the target loop time is decremented to 0. Or once from 0, and then continues to step S600 until the target number of cycles is reached.

Further, the arithmetic circuit 12 may perform a judgment according to the operation code Scr Op in the arithmetic instruction, determine the number of the source operands, and when the number of the source operands is two, obtain the second sub-data according to the instruction, and then perform the arithmetic operation. And when the number of the source operands is three, acquiring second subdata and third subdata according to the instruction, and then executing the operation. For reading the second sub data and/or the third sub data, the above description may be specifically referred to.

In the instruction disassembling method in this embodiment, the data size of the first source operand is obtained in the decoding stage, the first source operand is disassembled and cyclically read, the large data is disassembled into the small data for operation, and the operand is cyclically read according to the data reading capacity, so that the size of the data that can be accommodated during operation meets the requirement, and the operation speed is increased.

When it is determined that three source operands participate in the operation according to the operation instruction, according to the instruction format of the operation instruction, the source operand a is used as the second source operand, and the source operand B is used as the third source operand.

Specifically, referring to the format of Src Op in table 2, when Src Op in the received operation instruction is 010, which indicates that the source operand a is valid, the source operand a is used as the second source operand; when the Src Op in the received operation instruction corresponds to 011, indicating that the source operand B is valid, taking the source operand B as a second source operand; when Src Op in the received operation instruction corresponds to 100, which indicates that source operand a is valid and source operand B is valid, source operand a is used as the second source operand and source operand B is used as the third source operand.

It should be understood that although the various steps in the flow charts of fig. 6-11 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Also, at least some of the steps in fig. 6-11 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performing the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

In one embodiment, as shown in fig. 12, there is provided a data processing apparatus including: an obtaining module 100, a reading module 200, an operation module 300 and a counting module 400, wherein:

the obtaining module 100 is configured to obtain an operation instruction.

The reading module 200 is configured to read first subdata from a first storage device according to a data reading capacity and an operation instruction in a preset data reading manner, and store the currently read first subdata in a second storage device.

The operation module 300 is configured to execute an operation according to the operation instruction, obtain a current operation result, store the current operation result in the second storage device and the first storage device, and then circularly call the reading module 200 and the operation module 300 until the operation corresponding to the operation instruction is completed.

Further, the data processing apparatus may include a counting module 400 for controlling the counter to increment or decrement once after the current operation result in the second storage device is stored in the first storage device, and then, the reading module 200, the operation module 300, and the counting module 400 are called in a loop until the counter is incremented from the initial value to the target number of cycles or the counter is decremented from the target number of cycles to the initial value. In the embodiment of the present application, the initial value may be 0.

For specific limitations of the data processing apparatus, reference may be made to the above limitations of the data processing method, which are not described herein again. The various modules in the data processing apparatus described above may be implemented in whole or in part by software, hardware, and combinations thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.

When the operation instruction is Atomic ADD, the operation module 300 may include an addition operation module, where the obtaining module 100 is configured to obtain the operation instruction, where the operation instruction is configured to implement a comparison operation between a first source operand and a second source operand, where the first source operand includes at least one first sub-data, and the second source operand includes at least one second sub-data; the reading module is used for reading first subdata from a first storage device according to data reading capacity and an operation instruction and a preset data reading mode, and storing the currently read first subdata into a second storage device, wherein the first storage device is an off-chip storage device, and the second storage device is an on-chip storage device; the subtraction operation module 310 is configured to obtain second sub data according to the operation instruction, add the currently read first sub data and the second sub data to obtain a current operation result, and store the current operation result in the second storage device and the first storage device. Then, the reading module 200 and the addition operation module 310 are called circularly until the operation corresponding to the operation instruction is completed. Further, the data processing apparatus may include a counting module 400 for controlling the counter to increment or decrement once after the current operation result in the second storage apparatus is stored in the first storage apparatus, and then, the reading module 200, the addition operation module 310, and the counting module 400 are called in a loop until the counter is incremented from the initial value to the target number of cycles or the counter is decremented from the target number of cycles to the initial value. In the embodiment of the present application, the initial value may be 0.

In the embodiment of the present invention, the specific structure of the operation module is similar to that of the operation circuit in the embodiment, and refer to fig. 2 and the description above.

In one embodiment, as shown in fig. 13, there is provided an instruction dismantling device including: an obtaining module 500, a cycle number processing module 600, a data reading capacity calculating module 700, a reading module 800, and an operation module 900, wherein:

the obtaining module 500 is configured to obtain an operation instruction, and analyze the data size of the first source operand according to the operation instruction.

The cycle number processing module 600 is configured to obtain a cycle number according to the data size of the first source operand and a preset splitting granularity. The data reading capacity calculation module 700 is configured to obtain a data reading capacity according to the data size of the first source operand and a preset splitting granularity. The reading module 800 is configured to read the first subdata from the first storage device according to the operation instruction and the data reading capacity and according to a preset data reading manner, and store the currently read first subdata into the second storage device. The operation module 900 is configured to execute an operation according to the operation instruction, and store the obtained current operation result in the second storage device and the first storage device. The cycle number processing module 600 is configured to decrement the cycle number once or accumulate the cycle number once from 0, and then call the data reading capacity calculation module 700, the reading module 800, and the operation module 900 until the current cycle number is equal to the initial value or the current cycle number is equal to the target cycle number, so as to complete the operation corresponding to the operation instruction.

In the embodiment of the present application, the operation principle of the operation module 900 is the same as the operation principle of the operation module 300 and the operation circuit, and the description thereof can be referred to specifically. For specific limitations of the instruction disassembling device, reference may be made to the above limitations of the instruction disassembling method, which is not described herein again. The various modules in the data processing apparatus described above may be implemented in whole or in part by software, hardware, and combinations thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.

In one embodiment, a computer-readable storage medium is provided, having a computer program stored thereon, which when executed by a processor, performs the steps of:

and acquiring an operation instruction, wherein the operation instruction is used for realizing operation among source operands, and the first source operand comprises at least one first subdata.

Reading first subdata from a first storage device according to the data reading capacity and the operation instruction and a preset data reading mode, and storing the currently read first subdata into a second storage device; the first storage device 13 is an off-chip storage device, and the second storage device 201 is an on-chip storage device.

And executing the operation according to the operation instruction, and storing the obtained current operation result into the second storage device and the first storage device.

It should be clear that, the steps implemented when the computer program in the embodiment of the present application is executed by the processor are consistent with the execution process of each step of the method in the above embodiments, and specific reference may be made to the above description, and no further description is given here.

acquiring an operation instruction, and analyzing the data size of a first source operand according to the operation instruction, wherein the first source operand comprises at least one first subdata;

obtaining cycle times and data reading capacity according to the data size of the first source operand and a preset splitting granularity;

reading first subdata from a first storage device according to an operation instruction and a data reading capacity and a preset data reading mode, and storing the currently read first subdata into a second storage device;

executing operation according to the operation instruction, storing the obtained current operation result into the second storage device, and storing the current operation result in the second storage device into the first storage device;

and then, returning to the step of determining the data reading capacity according to the data size of the first source operand and the preset splitting granularity until the operation corresponding to the operation instruction is completed.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A method of data processing, the method comprising:

2. The data processing method of claim 1, wherein the step of adding the currently read first sub data and the second sub data to obtain a current operation result comprises:

and carrying out alignment addition on the currently read first subdata and the second subdata to obtain the current operation result.

3. A data processing method according to claim 1 or 2, wherein the second source operand is an immediate or data stored in the second storage means, the method further comprising:

if the second source operand is an immediate, copying the immediate, copying a plurality of obtained immediate as second subdata, wherein the number of the second subdata is equal to that of the currently read first subdata;

and if the second source operand is data stored in the second storage device, reading the second subdata from a preset storage address of the second storage device, wherein the number of the currently read second subdata is equal to that of the first subdata.

4. A data processing method according to claim 3, characterized in that the method further comprises the steps of:

and according to the operation instruction, taking a source operand A and/or a source operand B as the second source operand.

5. The data processing method of claim 1, wherein the method further comprises:

and after the current operation result is stored in the first storage device, taking the next address of the last read end address of the first subdata as the start address of the currently read first subdata.

6. The data processing method of claim 1, wherein the method further comprises:

and when the current operation result is stored in the first storage device, the storage address of the current operation result is consistent with the storage address of the currently read first subdata.

7. The data processing method according to claim 1, wherein the step of storing the current operation result in the second storage device and the first storage device comprises:

storing the current operation result into the second storage device;

and storing the current operation result in the second storage device into the first storage device.

8. The data processing method of claim 1, wherein the method further comprises:

obtaining the data size of the first source operand according to the operation instruction;

and obtaining the target cycle number according to the data size of the first source operand and a preset splitting granularity.

9. The data processing method of claim 1,

the instruction format of the operation instruction comprises an instruction type, a first source operand, a second source operand, a target operand and an operation code;

the operation code is used for configuring the number of source operands;

the target operand is used for representing the current operation result.

10. A processor for use in a data processing method, the processor comprising an arithmetic circuit, a read-write circuit, and a second storage device disposed adjacent to the arithmetic circuit, the second storage device being connectable to a first storage device external to the processor via the read-write circuit;

the arithmetic circuit is configured to obtain the second sub data, add the currently read first sub data and the second sub data to obtain a current arithmetic result, and store the current arithmetic result in the second storage device and the first storage device; and controlling the counter to accumulate once or decrement once, then sending a read-write request to the first storage device again, reading the first subdata from the first storage device according to the data reading capacity and the operation instruction and a preset data reading mode until the counter accumulates from an initial value to a target cycle time or the counter decrements from the target cycle time to the initial value, and finishing the operation corresponding to the operation instruction.

11. The processor of claim 10, further comprising a data selector, wherein the arithmetic circuit comprises an addition operation module, and wherein the data selector is connected between the arithmetic circuit and the read/write circuit, and wherein the data selector is configured to gate a connection path between the addition operation module and the read/write circuit;

the addition operation module is used for acquiring the second subdata, adding the currently read first subdata and the second subdata according to the operation instruction to obtain a current operation result, and storing the current operation result into the second storage device; and storing the current operation result of the second storage device into the first storage device through the read-write circuit and the data selector.

12. The processor of claim 11, wherein the add operation module comprises an add unit and a result output unit coupled to the add unit;

the adding unit is used for performing alignment addition on the currently read first subdata and the second subdata;

the result output unit is configured to perform a bit-wise addition on the currently read first sub data and the second sub data to obtain a result, which is used as the current operation result.

13. The processor of claim 11,

the addition operation module is further used for determining the second source operand to be an immediate or data stored in the second storage device according to the operation instruction,

if the second source operand is determined to be an immediate, the addition operation module copies the immediate, and copies a plurality of obtained immediate as the second subdata, wherein the number of the second subdata is equal to the number of the currently read first subdata;

if the second source operand is determined to be the data stored in the second storage device, the read-write circuit reads the second subdata from a preset storage address of the second storage device, and the number of the currently read second subdata is equal to the number of the first subdata.

14. The processor according to any one of claims 11 to 13, wherein the arithmetic circuitry comprises a master processing circuit and one or more slave processing circuits, each of the one or more slave processing circuits being connected to the master processing circuit;

the addition operation module is arranged in the main processing circuit.

15. A data processing apparatus, characterized in that the apparatus comprises:

the apparatus comprises an obtaining module, a calculating module and a judging module, wherein the obtaining module is used for obtaining an operation instruction, the operation instruction is used for realizing addition operation of a first source operand and a second source operand, the first source operand comprises at least one first subdata, and the second source operand comprises at least one second subdata;

a reading module, configured to read the first subdata from a first storage device according to a data reading capacity and the operation instruction and according to a preset data reading manner, and store the currently read first subdata into a second storage device, where the first storage device is an off-chip storage device and the second storage device is an on-chip storage device;

the operation module is used for acquiring the second subdata according to the operation instruction, adding the currently read first subdata and the second subdata to obtain a current operation result, and storing the current operation result into the second storage device and the first storage device;

the operation module is further configured to control the counter to increment or decrement once, and then return to the step of reading the first sub-data from the first storage device according to the data reading capacity and the operation instruction and in a preset data reading manner until the counter increments from an initial value to a target cycle number or the counter decrements from the target cycle number to the initial value, so as to complete an operation corresponding to the operation instruction.

16. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 9.