CN101221494B

CN101221494B - Novel 8-digit RISC microcontroller framework

Info

Publication number: CN101221494B
Application number: CN200710187213XA
Authority: CN
Inventors: 潘松; 陈光胜; 岳卫杰; 刘桂蓉
Original assignee: Shanghai Hair Group Integated Circuit Co Ltd
Current assignee: Shanghai Hair Group Integated Circuit Co Ltd; Shanghai Haier Integrated Circuit Co Ltd
Priority date: 2005-08-31
Filing date: 2005-08-31
Publication date: 2010-12-29
Anticipated expiration: 2025-08-31
Also published as: CN101221494A

Abstract

The present invention discloses a novel 8-bit RISC microcontroller framework, comprising a two-stage four-segment pipeline structure. The two-stage four-segment pipeline structure comprises an instruction processing device, a data readout device, a data operation device, a data writing device, a state machine and a clock generator. Due to the structure, clocks are not coupled crosswise; steady clocks can be generated for sure; the devices depend on and backup each other. The preprocessing and processing to data greatly improve the anti-interference ability of the structure, so as to realize high productivity.

Description

A kind of 8 digit RISC micro controller frames

The application is to be on August 31st, 2005 applying date, and application number is 200510029281.4, and denomination of invention is divided an application for the application for a patent for invention of " a kind of 8 novel digit RISC micro controller frames ".

Technical field

The invention belongs to the SIC (semiconductor integrated circuit) design field, relate in particular to a kind of microcontroller (MCU) system architecture.

Background technology

In recent years, the reduced instruction set computer of microcontroller (RISC) structure has obtained to popularize widely.Though what feature risc processor should have and also have different views, various risc architectures all have following these features: (1) most instructions is an one-cycle instruction, so that the implementation structure pipelining; (2) independence and simple loading and storage instruction all are the binary cycle instructions; (3) the instruction decoding all is that hardwired is realized rather than microcycle decoder usually, so that accelerate execution speed; (4) most instructions has set form, with reduction instruction coding and decoding; (5) less instruction set and a few addressing mode; (6) data channel pipelining makes the processing procedure highly-parallel; (7) adopt high-capacity and high-speed register file (or being called register file), avoid the system RAM swap data lower as far as possible with speed.

These features of RISC microcontroller have also been brought some essential defective and deficiencies: (1) instruction set can not be expanded; (2) pipelining segment and progression are more, have brought the complicacy of pipelining segment data dependence criterion, sometimes even have influence on the pipeline data throughput; (3) data-carrier store and program storage are multiplexing, do not have special register file, or specified register heap and general-purpose register influenced the access speed to these registers separating, and have limited the raising of travelling speed; (4) do not adopt design for Measurability (DFT), in application, can't guarantee the manufacturing quality of production of product; (5) and at present still unsolved greatest problem is: for four sections pipeline organizations of two-stage, each intermodule can't back up mutually, rely on mutually, more can not carry out pre-service and processing to data, has had a strong impact on the antijamming capability of this structure.

Summary of the invention

The technical issues that need to address of the present invention are to provide a kind of 8 novel digit RISC micro controller frames, so that instruction is not only complete, and can back up mutually, rely on mutually, and data are carried out pre-service, thereby improve the antijamming capability of total.

Technical scheme of the present invention is: comprise program bus, data bus, program storage, be connected to command decoder, data random access memory (RAM), register file, universal arithmetic logic unit (ALU) and the address bus of program storage by program bus, above-mentioned parts are realized by microcode operation control structure; Also comprise four sections pipeline organizations of a secondary, by four phase clock driving work, each section streamline is finished function at corresponding clock in mutually, it is characterized in that four sections pipeline organizations of described secondary comprise:

Instruction processing unit is used to finish instruction decode, PC backup, binary cycle instruction pre-service, interrupt vector processing, port variation interruption pretreatment operation;

Data fetch device receives the addressing operation number and the data content of the output of instruction reading device, and finishes a plurality of function registers or data register reads, and finishes interrupt request sign pretreatment operation simultaneously;

The data operation device, receive the arithmetic type operational code of instruction processing unit output, the data content of reception data fetch device output, and finish arithmetic logical operation device (ALU) data operation, port variation terminal processes, idle pulley activation pretreatment operation, read next bar instruction simultaneously;

Data are write return device, the operation result of data operation device partly done according to the operand addressing of instruction processing unit write back operations, comprise finish that the ALU data write back, internal interrupt and storehouse handle, and finishes PC simultaneously and handle, PC handles and comprises that PC adds 1, PC pops, the PC redirect;

Clock generator is used to above-mentioned four devices that four phase clock signals are provided, and produces four sections required synchronizing clock signals of pipeline organization of described secondary simultaneously.

Above-mentioned data write the Interrupt Process described in the return device and the internal stack treating apparatus can carry out the PC pop down automatically and the processing of popping.

Above-mentioned instruction processing unit comprises register, command decoder, port pretreater, interrupt handler, Port Multiplier, counts processors immediately.

Above-mentioned data fetch device comprises data register, two function registers, Port Multiplier.

Above-mentioned data operation device comprises arithmetic logical unit, Port Multiplier, instruction reader, the whole processor of port.

Above-mentioned data are write return device and are comprised data register, two function registers, interrupt handler, stack processor, PC processor.

Micro controller frame of the present invention also comprises a cover instruction set, and this instruction set belongs to reduced instruction set computer, comprises 48 instructions; The output order sign indicating number of described instruction processing unit is divided into 3 classes: byte manipulation class, bit manipulation class and several immediately and control generic operation class.

According to micro controller frame of the present invention, its ALU finishes all instructions all only needs a clock period, finishes in the 3rd clock period of instruction cycle.

According to micro controller frame of the present invention, its data register comprises specified register and general-purpose register, utilize the map addresses circuit the physical address map that is distributed in the specified register of different districts and data space and general-purpose register to continuous physical address.

According to micro controller frame of the present invention, described Interrupt Process and internal stack processing mode are carried out the PC pop down automatically and are gone out stack operation when call subroutine or Interrupt Process, realize the efficient processing of interrupting.

Micro controller frame of the present invention also comprises a cover instruction set, belongs to reduced instruction set computer, comprises 48 instructions, and the output order sign indicating number of described instruction processing unit is divided into 3 classes, i.e. byte manipulation class, bit manipulation class and number operation immediately and control class.

Wherein the instruction of byte manipulation class has 28, is respectively arithmetic logical operation operation and blank operation to function register or register R; The result of arithmetic logical operation writes destination register according to zone bit F, if F is 0, destination register is that data are write function register A1 in the return device (A0 herein, A1, B0, B1 are the code name of function register, can replace; Because addressing physically is same class function register A for function register A0/A1, in different devices, be defined as A0/A1 respectively, be about to function register A content and read to be designated as A0, on bus, data write-in functions register A is designated as A1 to data bus; Addressing physically is same class function register B for function register B0/B1, is defined as B0/B1 in different devices respectively, is about to function register B content and reads to be designated as B0 to data bus, on bus data write-in functions register B is designated as B1.); If F is 1, destination register is that R or data are write the function register B1 in the return device.

Wherein bit manipulation class instruction has 4, is to carry out clearly 0 or whether put 1 operation and contraposition be 0 or 1 to carry out decision operation to register R; Clear 0 and put 1 result and do according to F and write back operations, if decision operation will not write back operations.

Wherein number has 18 with control generic operation instruction immediately, is to number operation immediately with to the instruction of microprocessor controls.

As improvement of the present invention, the interruption of described micro controller frame comprises hardware interrupts and software interruption, can select one or more to interrupt entry address, the interrupt type that the differentiation that is more prone to is different, use a plurality of interruptions entry address pattern, soft interrupt priority level is the highest.

As improvement of the present invention, the internal stack of described micro controller frame is handled, and adopts solely heat sign indicating number (One-Hot) state machine, makes that PC pop down and the operation of popping are more reliable and more stable.

As improvement of the present invention, can comprise 8 programs in its byte manipulation class instruction set carries out and does not bring into/the arithmetic logical operation instruction of borrow, these instructions are input to arithmetic operation unit ALU with the function register A0 content in register R and the data fetch device and carry out computing, the result of computing is done according to zone bit F write back operations; These register operational orders comprise addition, subtraction, add 1, subtract 1, logical and, logic with or, logic XOR, logic supplement sign indicating number, the corresponding respectively command character of its operational code is ADD, SUB, INC, DEC, AND, IOR, XOR, COMP.

As improvement of the present invention, can comprise 2 programs in its byte manipulation class instruction set and carry out clear 0 instruction of registers, these instructions comprise to R zero clearing CLRR with to the function register A0 zero clearing in the data reading device and the result is write back the instruction CLRA of A1.

As improvement of the present invention, can comprise 2 programs execution in its byte manipulation class instruction set and add/subtract 1 also decision instruction, these instructions are input to ALU with the R content and carry out computing, to add/subtract 1 operation, whether judged result is 0 to determine whether carrying out next bar instruction, and the result is done according to F write back operations; These instructions comprise that adding 1 judges, subtracts 1 judgement, and the corresponding respectively command character of its operational code is JINC, JDEC.

As improvement of the present invention, can comprise 2 programs in its byte manipulation class instruction set and carry out and bring into/the circulative shift operation instruction of borrow C, these instructions are input to ALU with R content and C and carry out shifting function, and the result are done according to F write back operations; These instructions comprise move to left, right shift instruction, the corresponding respectively command character of its operational code is RL, RR.

As improvement of the present invention, can comprise 3 programs in its byte manipulation class instruction set and carry out non-operation instruction, to carry out these instructions and do not do any operation, the command character that these instruction operation codes are corresponding respectively is NOP, NOP2, NOP3.

As improvement of the present invention, can comprise 2 programs in its byte manipulation class instruction set and carry out the decimal system binary-coded decimal addition adjustment instruction of bringing the position into, these instructions are input to ALU with the content of R after the addition or A and C and DC and carry out the binary-coded decimal computing, and the result is write back data write function register A1 or R operation in the return device; These instructions comprise to register R with to function register A0 carries out binary-coded decimal (the binary code decimal system) adjustment, and the command character that these instruction operation codes are corresponding respectively is DAW, DAR.

As improvement of the present invention, can comprise 2 programs in its byte manipulation class instruction set carries out and brings into/the arithmetic logical operation instruction of borrow, these instructions are input to ALU with the function register A0 content in R and the data fetch device and C and carry out computing, the result of computing is done according to F write back operations; These instructions comprise full add method, band borrow subtraction, and the command character that these instruction operation codes are corresponding respectively is ADDC, SUBC.

As improvement of the present invention, can comprise 1 program in its byte manipulation class instruction set and carry out the multiplying instruction, this instruction is input to ALU with R and function register A0 content and carries out computing, the least-significant byte as a result of computing done according to F write back operations, most-significant byte writes data and writes return device internal strength energy register B1, the register multiplying order is an one-cycle instruction, and this instruction manipulation code sign is MUL.

As improvement of the present invention, can comprise 2 programmed data transfer operational orders in its byte manipulation class instruction set, these instructions are deposited into another register with the function register A0 content in R or the data fetch device, pass through ALU then, data are done according to F write back operations; The command character that these instruction operation codes are corresponding respectively is MOV, MOVA.

As improvement of the present invention, can comprise 1 program in its byte manipulation class instruction set and carry out the function register data movement instruction, this instruction deposits the content of function register A0 function register B1 in or deposits the content of function register B0 in function register A1, and does according to F and to write back operations; F is 0, and with the content write-in functions register A1 of function register B0, F is 1, and with the content write-in functions register B1 of function register A0, this instruction manipulation code sign is MOVAB.

As improvement of the present invention, can comprise data movement instruction in 1 procedure bytes in its byte manipulation class instruction set, this instruction is carried out high 4 and low 4 exchanges with R content input ALU, data is done according to F write back operations, this instruction manipulation code sign SWAP.

As improvement of the present invention, can comprise 2 program execute bits clear 0 in its bit manipulation class instruction set or put 1 instruction, these instructions are input to ALU with the R content, according to appointment carry out clearly 0 or put 1 computing, the result of computing is done according to F writes back operations; These instructions comprise that the position is clear 0, put 1, and the corresponding respectively command character of its operational code is BC, BS.

As improvement of the present invention, can comprise 2 program execute bits in its bit manipulation class instruction set and judge the decision execution command, these instructions are input to ALU with the R content, are 0 or 1 judgements according to the position of appointment, and whether decision carries out next bar is instructed; These instructions comprise judges that the position is 0, judges that the position is 1, and the corresponding respectively command character of its operational code is JBC, JBS.

As improvement of the present invention, its can comprise in number and the control class instruction set immediately 5 programs carry out do not bring into/borrow count function register A0 arithmetic logical operation instruction in I and the data fetch device immediately, these instructions are input to ALU with I and A0 content and carry out computing, with the result of computing write data write the return device internal strength can register A1 operation; These count immediately operational orders comprise addition, subtraction, logical and, logic with or, the logic XOR, the corresponding respectively command character of its operational code is ADDI, SUBI, ANDI, IORI, XORI.

As improvement of the present invention, it comprises 2 programs immediately in number and the control class instruction set and carries out and bring into/I and the function register A0 arithmetic logical operation instruction of borrow, these instructions are input to ALU with I and A0 content and carry out computing, with the register of the write-in functions as a result A1 operation of computing; These instructions comprise full add method, band borrow subtraction, and the corresponding respectively command character of its operational code is ADDCI, SUBCI.

As improvement of the present invention, it is counted immediately and controls in the class instruction set and comprises 1 program to the function register A0 assignment directive in the data reading device, will count the instruction that assignment are given function register A1 immediately, this instruction operation code correspondence command character MOVI.

As improvement of the present invention, it comprises 1 program immediately in number and the control class instruction set and carries out and count the multiplyings instruction immediately, this instruction will be counted immediately and function register A0 content is input to ALU and carries out computing, the write-in functions of least-significant byte as a result register A1 with computing, most-significant byte write-in functions register B1, counting multiplying order immediately is one-cycle instruction, the corresponding command character MULI of this instruction operation code.

As improvement of the present invention, it is counted immediately and controls and comprises the instruction of 2 programs execution call subroutines in the class instruction set, and these instructions will be counted assignment programmable counter PC immediately, then the PC value will be pressed into storehouse; These instructions comprise call subroutine, location call subroutine longways, and the corresponding respectively command character of its operational code is CALL, LCALL.

As improvement of the present invention, it is counted immediately and controls and comprises 2 programs execution jump instructions in the class instruction set, and these instructions will be counted assignment immediately and be given PC; These instructions comprise redirect, short address redirect, and the corresponding respectively command character of its operational code is GOTO, JUMP.

As improvement of the present invention, it is counted immediately and controls in the class instruction set and comprises 1 program execution subroutine link order, and this instruction will be jumped out subroutine, and the command character of its operational code correspondence is RET.

As improvement of the present invention, it is counted immediately and controls and comprises 1 several immediately subroutine return instruction of program execution band in the class instruction set, this instruction will be jumped out subroutine, will count assignment simultaneously immediately and give function register A1, and the command character of its operational code correspondence is RETI.

As improvement of the present invention, it is counted immediately and controls and comprises 1 program execution interrupt routine link order in the class instruction set, and this instruction will be jumped out interruption subroutine, and the command character of its operational code correspondence is RETINT.

As improvement of the present invention, it comprises 1 program to clear 0 instruction of house dog WDT in number and the control class instruction set immediately, and this instruction is clear 0 with WDT, and the corresponding respectively command character of its operational code is CWDT.

As improvement of the present invention, it comprises 1 program in number and the control class instruction set immediately and enters idle mode instruction, and the corresponding respectively command character of its operational code is IDLE.

As improvement of the present invention, it is counted immediately and controls and comprises 1 program executive chairman call subroutine instruction LCALL in the class instruction set, and this instruction need not to stride page operations by setting, directly realizes the subroutine call in the program storage 8k scope.

As improvement of the present invention, it is counted immediately and controls and comprises 1 program execution short address jump instruction JUMP in the class instruction set, and this instruction will realize the redirect in program storage-255～+ 255 scopes.

The present invention is a kind of novel RISC streamline micro controller frame and realization, the instruction set of this micro controller frame is reduced instruction set computer (RISC), data-bus width is 8, adopt the two-stage pipeline parallel method to handle and execution command, data storage adopts single-ended asynchronous RAM mode to realize, as general-purpose register, and the inner register file that also has d type flip flop to form, formed data register jointly, its physical address is mapped on the logical address by a mapping table.

Technique effect of the present invention is: when streamline was worked, clock generator was divided into four phase clock Q1/Q2/Q3/Q4 to external clock, promptly controls the clock of 4 pipelining segments.And four phase clocks are to control realization by the state machine of two-stage trigger, can make its every clock can cross-couplings, and possesses very strong anti-interference, guarantee to produce stable clock, therefore dependence mutually between each device, backup mutually, and, can make this structure improve a lot again for antijamming capability to the pre-service and the processing of data; In addition,, be fit to adopt the full Synchronization Design of Top-Down, thereby shorten design, proving period, possess design for Measurability DFT and manufacturability design DFM simultaneously, realize higher chip production yield owing to adopt rational flowing water clock and framework setting.

Description of drawings

Fig. 1 is mechanism's block diagram of four sections pipeline organizations of secondary;

Fig. 2 is the system chart of micro controller frame of the present invention;

Fig. 3 is the streamline basic circuit;

Fig. 4 is the applied environment and the peripheral module resource distribution figure of micro controller frame of the present invention;

Fig. 5 is a micro controller frame kernel of the present invention;

Embodiment

Describe the hardware details relevant below in detail with the micro controller frame functional character.

As Fig. 1 is four sections pipeline organizations of a secondary, drive work by four phase clock Q1/Q2/Q2/Q3, each section streamline is finished function at corresponding clock in mutually, it comprises: instruction processing unit, program pointer points to program storage, choose the content of program, make its entry instruction register, the value of order register is carried out decoded operation through code translator, this device also comprise port pretreater that the variation of port is sampled and to number operation immediately count processors immediately, this type of function is finished at the Q1 phase clock; Data fetch device, decoded signal by instruction processing unit output, enter read data addressing processing unit the data register is carried out addressing and the data register reading of data from being addressed to, this device also comprises interrupting interrupt identification bit processor and the bit manipulation processor that handle the request flag position, and this type of function is finished at the Q2 phase clock; The data operation device, comprise the arithmetic logical unit ALU that carries out data operation, determine the whole processing unit of port that port changes, detect the idle pulley processor whether microcontroller is in idle pulley, read the instruction fetch processor of next bar instruction, this type of function is finished at the Q3 phase clock; Data are write return device, comprise the write data addressing processor that the data register is carried out addressing, and the result of data operation device write back by the data register of write data addressing or function register, also comprise stack processor, interrupt handler and PC processor (contain PC adds 1, PC pops, PC redirect) simultaneously, use in order to the next stage streamline, this type of function is finished at the Q4 phase clock; Clock generator, the four phase clock signals that produced by only heat sign indicating number (One-Hot) state machine export each other device respectively to, produce four sections required synchronizing clock signals of pipeline organization of described secondary simultaneously.

With reference to figure 2, this is the system architecture of micro controller frame of the present invention.At first, clock generator provides clock for each device, and 16 program pointers point to program storage and take out instruction, need deliver to instruction in the order register to store, and deciphers accordingly then.Code translator is controlled whole microcontroller duty, and the microcode of the output of code translator is divided into three major types with instruction: the instruction of byte manipulation class, bit manipulation instruction, number operation immediately and the instruction of control operation class.If the instruction of control operation class by the selection of Port Multiplier, will be selected the program pointer of code translator output.The instruction relevant with arithmetic logical operation will be deciphered output and point to ALU, the arithmetic type (comprising arithmetical operation and logical operation) of decision ALU, and concrete operations are with reference to the realization (Fig. 5) of core framework.Interrupt handler is the core component of handling interrupt, when taking place to interrupt, will select interrupt vector as program pointer by Port Multiplier, and the PC processor is imported stack processor with current PC and done the pop down processing simultaneously; When take place interrupting returning, stack processor is done the processing of popping, and exports the data in the stack to the PC processor, and the PC processor will be by Port Multiplier with the data of popping as program pointer.The PC processor is except above-mentioned functions, the PC that also comprises the microcontroller operate as normal adds 1 operation, when carrying out jump instruction, code translator is done skip operation with the jump address assignment to PC, and be the anti-interference PC backup operation that designs, the variation of each PC all backups last PC value, can do some corrective operations when being disturbed in order to PC.So output also can be divided into three major types during decoding, with reference to figure 5.Code translator output is exactly read-write operation for operation registers, and at first, read register needs code translator output to read address signal, specifies certain specific data register and corresponding read signal; Secondly, when the ALU computing finishes, writing register needs code translator output write addressing signal, specifies certain specific data register and corresponding write signal, if the register of appointment is a function register, so directly writes back function register.After finishing an instruction cycle, Port Multiplier will be chosen next transient program pointer and be input to program pointer, take out next bar instruction, and so constantly circulation forms pipelining.The major part of instruction set is an one-cycle instruction among the present invention, and the efficient of execution is higher, the realization stream line operation that is more prone to.

Because it is of the present invention comparatively outstanding that chip operation pattern and port are handled,, handle so arrange Q3 to finish idle pulley so whether microcontroller real-time detection microcontroller in water operation needs to enter the idle pulley of low-power consumption; And being the part ports of detection chip, port pre-service and port aftertreatment whether change, finish pre-service and Q3 finishes whole processing by Q1, judge to guarantee that microcontroller is made accurately the variation of external signal, avoid chip to be interfered after, the phenomenon that can't correctly judge takes place.

Program circuit schematic diagram as shown in Figure 3.After resetting, the PC register value is 0000H, and program pointer points to the 0000H place of program storage.Clock generator is started working, and at the Q1 phase clock, the PC value backups to the PC_TEMP register; Mode of operation by chip judges to learn whether whether chip is operated in the IDLE pattern, if be operated in the IDLE pattern, the PC value backups to the PC_PLUS register equally, backups to the PC_PLUS register otherwise PC adds 1.And PC_PLUS and PC_TEMP value by judging the chip operation pattern, are given the PC register assignment at the Q4 phase clock, if be operated in the IDLE pattern, the PC_TEMP register assignment is given the PC register, otherwise the PC_PLUS register value is composed the register to PC.The instruction of execution call subroutine, at the Q4 phase clock, the direct pop down of PC_TEMP value is to the STACK stack register, and the value of PC register obtains by instruction decode, realizes the PC redirect; This storehouse is multistage storehouse, adopts the solely transfer of heat sign indicating number (One-Hot) state machine realization stack states, makes the pop down of storehouse pop highly stable; When interrupting returning or subroutine interrupts returning, storehouse will be made stack operation, and the stack top value of storehouse is composed the register to PC.The PC register value can be given the PC register with the value indirect assignment of function register A directly by the instruction assignment, realizes the PC redirect; The PC register can also instruct by jump class, and the numerical value assignment is given the PC register immediately, realizes the PC redirect.

Selectable multiple interrupt vector sum interrupt vector table is a key character of the present invention, finds that from Fig. 5 by the interrupt vector gating, can select an interrupt vector pattern, promptly interrupt vector 0, perhaps a plurality of interrupt vectors, and promptly interrupt vector 1 to interrupt vector N.According to practical application, select a suitable interrupt vector table, different interruptions is classified, be assigned to different interrupt vectors respectively, promptly interrupt vector 1 to interrupt vector N.Once interrupt selecting an interrupt vector, interrupt vector is selected the interrupt vector of this interruption by multidirectional amount gating signal, carries out the processing of interruption subroutine, makes the application of interrupting convenient reliable.

Program circuit and program pointer interdepend, at the Q3 phase clock, relatively whether the PC_TEMP register value is the same with program pointer, produces the PC_DIFF marking signal, change if PC_DIFF is 1 representation program pointer, do not change if PC_DIFF is 0 expression PC pointer.When PC_DIFF is 1, representation program is operated in redirect or interruption or call subroutine, and program pointer points to program storage by PC, if PC_DIFF is 0, representation program is carried out in proper order, and promptly PC adds 1 pattern and carries out.

The PC processing that this method realizes, Interrupt Process, storehouse are handled, can reach dependable performance, speed is very fast, such as when execution CALL, RET etc. instruct, interrupt handler and storehouse treatment circuit can carry out the PC pop down and the processing of popping automatically, the present procedure address is taken out from programmable counter, be pressed into storehouse, or the storehouse top is ejected, be loaded in the programmable counter as the current address.This mode has been accelerated Interrupt Process speed greatly.

As shown in Figure 4, be arithmetic logical unit schematic diagram of the present invention.2 select 1 MUX MUX1 be input as register A0 or B0 and constant 01H, be output as alub.Equally, the input K by another MUX MUX3 is from instructing counting immediately that direct decoding comes, and fout represents the data exported in register file.Selection to these inputs need be judged according to the instruction of current execution, selects required output data.MUX MUX3 is output as alua, and it imports into arithmetic logical operation part on the one hand, selects 1 MUX MUX2 by 2 on the other hand, and the arithmetic logical operation part is advanced in input.MUX MUX2 is controlled by signal alubf, and signal alubf is mainly produced by clear command.If have reset signal to produce, import into arithmetic logical operation part A LU with regard to gating alua.Arithmetic logical operation part A LU is the most crucial part of arithmetic logical unit, it includes hardware adder, hardware multiplier, hardware shift unit, logical-arithmetic unit, bit manipulation device etc., can realize shift operation, with non-or non-, XOR, non-, addition, subtraction, multiplication with relatively wait computing.

According to opcode[3:0] to select, the 3-8 code translator is mainly used to carry out bit manipulation.Choose the position of action required by the 3-8 code translator, the bit manipulation device of input ALU carries out the computing and the operation (comprising position 1 and position clear 0) of position.Another signal C is carry or borrow, is used to carry out addition, subtraction, shift operation.Arithmetic logical operation has partly been exported three kinds of signals promptly: computing carry flag aluc, nibble carry flag aludc, computing zero flag aluz, the data 1 of operation result; If carry out multiplying, the operation result that produces most-significant byte is that the operation result of data 2 and least-significant byte is data 2.Because totalizer, multiplier, shift unit, logical-arithmetic unit, bit manipulation device all are to adopt hardware to realize, the line that promptly adopts logic and, line or etc. hardware circuit realize, the chip area of the arithmetic element of Jie Shenging greatly, also improved simultaneously arithmetic speed greatly, only needed an instruction cycle just can finish such as the multiplying order of carrying out by hardware multiplier.

ALU of the present invention finishes all instructions all only needs a clock period, promptly finishes at the Q3 of instruction cycle phase clock.And the result of computing writes corresponding register at the Q4 of instruction cycle phase clock, and data 1 are by selector switch write-in functions register A1 or data register, and selector switch is done selection write-in functions register A1 or data register by the zone bit F of instruction; If execution multiplying order, the most-significant byte of multiplication write-in functions register B1, least-significant byte write-in functions register A1 as a result as a result so; If carry out in the instruction process of computing class, the carry flag aluc that produces, nibble carry flag aludc, zero flag aluz, with write state register STA, be respectively the 0th STA[0 of STA] preservation carry/borrow C, the 1st STA[1 of STA] preservation nibble carry DC, the 2nd STA[2 of STA] preservation zero flag position Z.Addressing physically is same class function register A for function register A0/A1, is defined as A0/A1 respectively at different devices, is about to function register A content and reads to be designated as A0 to data bus, on bus data write-in functions register A is designated as A1; Addressing physically is same class function register B for function register B0/B1, is defined as B0/B1 respectively at different devices, is about to function register B content and reads to be designated as B0 to data bus, on bus data write-in functions register B is designated as B1.

Fig. 5 is the applied environment and the resource distribution figure of micro controller frame of the present invention.

Asynchronous static data storer is the part of register file, as general-purpose data register, separates with the specified register heap, and specified register is realized with D-type edge-trippered flip-flop.Asynchronous static data storer has been formed the general-purpose data register circuit with SRAM interface circuit 3, and asynchronous static data storer 1 is to generate with standard RAM COMPILER when realizing.Program storage adopts asynchronous system and CPU nuclear to carry out exchanges data by configuration interface.As can see from Figure 5, program bus of the present invention and data bus separately belong to Harvard's type structure, and message transmission rate increases by 1 times than shared bus.

Clock generator circuit comprises four phase clock Q1/Q2/Q3/Q4 etc. for chip of the present invention provides all clock signals, and four phase clocks are connected to each functional module, and the clock that provides of each module work is provided.Reset circuit provides the reset signal that is necessary for other parts of the present invention, as electrify restoration circuit, starts back off timer, WDT reset signal, external reset signal etc.

Other peripheral modules of the present invention comprise communication interface, peripheral timer, seizure/comparison/width modulation etc.Communication interface mainly is a serial communication interface, comprises HSSP high-speed synchronous serial line interface and HASRT high-speed synchronous asynchronous transmission received communication interface.Peripheral timer comprises the T1 timer, the T2 timer.Seizure/comparison/width modulation mainly comprises CCP1 first via seizure/comparison/width modulation, the CCP2 the second tunnel seizure/comparison/width modulation.These peripheral circuits make the control ability of microcontroller strengthen greatly, have realized basic communication interface function, powerful timing function, to outside signal handling capacity or the like.

Micro controller frame of the present invention is supported the exemplary program instruction of common microcontroller, comprises that arithmetic sum logical order, branch instruction, data transfer instruction and bit test and position are provided with instruction.These instructions can be realized by the micro controller frame circuit support that provides in front narration and the accompanying drawing.Below be the instruction set of micro controller frame of the present invention, most significant digit can be expanded, and this microcode can be 0 or 1.

(1) instruction: ADD

Coding: 7 ' b1101011

Operation: (A)+(R)-(target)

Grammer: [label] ADD R, F

Describe: the content of register R is added on the content of register A.If F=0, then the result is kept on the register A; If F=1, then the result preserves back register R.

Influence zone bit: C, DC, Z

(2) instruction: SUB

Coding: 7 ' b1101110

Operation: (R)-(A)-(target)

Grammer: [label] SUB R, F

Describe: the content (surplus 2 methods) that the content of register R is deducted register A.If F=0, then the result is kept on the register A; If F=1, then the result preserves back register R.

Influence zone bit: C, DC, Z

(3) instruction: INC

Coding: 7 ' b1100110

Operation: (R)+1-〉(target)

Grammer: [label] INC R, F

Describe: the content of register R is added 1.If F=0, then the result preserves

On register A; If F=1, then the result preserves back register R.

Influence zone bit: Z

(4) instruction: DEC

Coding: 7 ' b1101111

Operation: (R)-1-〉(target)

Grammer: [label] DEC R, F

Describe: the content of register R is added 1.If F=0, then the result is kept on the register A; If F=1, then the result preserves back register R.

Influence zone bit: Z

(5) instruction: AND

Coding: 7 ' b1101001

Operation: (A) .AND. (R)-(target)

Grammer: [label] AND R, F

Describe: the content of register R with the content logic of register A with.If F=0, then the result is kept on the register A; If F=1, then the result preserves back register R.

Influence zone bit: Z

(6) instruction: IOR

Coding: 7 ' b1101000

Operation: (A) .OR. (R)-(target)

Grammer: [label] IOR R, F

Describe: the content of register R with the content logic of register A or.If F=0, then the result is kept on the register A; If F=1, then the result preserves back register R.

Influence zone bit: Z

(7) instruction: XOR

Coding: 7 ' b1101010

Operation: (A) .XOR. (R)-(target)

Grammer: [label] XOR R, F

Describe: the content logic XOR of the content of register A with register R.If F=0, then the result is kept on the register A; If F=1, then the result preserves back register R.

Influence zone bit: Z

(8) instruction: COM

Coding: 7 ' b1100101

Operation :-(R)-(target)

Grammer: [label] COM R, F

Describe: the content negate of register R.If F=0, then the result is kept on the register A; If F=1, then the result preserves back register R.

Influence zone bit: Z

(9) instruction: CLR R

Coding: 8 ' b11011011

Operation: 00h-〉(R)

1->Z

Grammer: [label] CLR R

Describe: remove the content of register R, and zone bit Z is put 1.

Influence zone bit: Z

(10) instruction: CLRA

Coding: 15 ' b110110100000011

Operation: 00h-〉(A)

1->Z

Grammer: [label] CLRA

Describe: remove the content of register A, and zone bit Z is put 1.

Influence zone bit: Z

(11) instruction: JINC

Coding: 7 ' b1100011

Operation: (R)+1-〉(target)

If the result is 0 then skips next instruction

Grammer: [label] JINC R, F

If the result is 1, then then carry out next bar instruction.If the result is 0, then carry out a NOP instruction, occupy 2 clock period.

(12) instruction: JDEC

Coding: 7 ' b1100111

Operation: (R)-1-〉(target)

If the result is 0 then skips next instruction

Grammer: [label] JDEC R, F

Describe: the content of register R is subtracted 1.If F=0, then the result is kept on the register A; If F=1, then the result preserves back register R.

(13) instruction: RL

Coding: 7 ' b1100001

Operation: referring to following description

Grammer: [label] RL R, F

Describe: the content of register R is circulated left by carry flag move one, concrete operations are referring to accompanying drawing 1.If F=0, then the result is kept on the register A; If F=1, then the result preserves back register R.

Influence zone bit: C

(14) instruction: RR

Coding: 7 ' b1100000

Operation: referring to following description

Grammer: [label] RR R, F

Describe: the content of register R is circulated to the right by carry flag move one, concrete operations are referring to accompanying drawing 2.If F=0, then the result is kept on the register A; If F=1, then the result preserves back register R.

Influence zone bit: C

(15) instruction: NOP

Coding: 15 ' b110_1100_0xx0_0000

Operation: blank operation

Grammer: [label] NOP

Describe: blank operation.

When this instruction is carried out, do not carry out any operation.X represents that 0 and 1 can.

(16) instruction: NOP2

Coding: 15 ' b111_1xxx_xxxx_xxxx

Operation: blank operation

Grammer: [label] NOP2

Describe: blank operation.

(17) instruction: NOP3

Coding: 15 ' b000_000x_xxxx_xxxx

Operation: blank operation

Grammer: [label] NOP3

Describe: blank operation.

(18) instruction: DAW

Coding: 15 ' b000_0100_xxxx_xxxx

Operation: referring to following description

Grammer: [label] DAW

Describe: the content of register A is carried out the binary-coded decimal adjustment, and concrete the adjustment operated referring to accompanying drawing 3.And the result preserved back register A.

Influence zone bit: C, DC, Z

(19) instruction: DAR

Coding: 7 ' b0000101

Operation: referring to following description

Grammer: [label] DAR R, F

Describe: the content of register R is carried out the binary-coded decimal adjustment, and concrete the adjustment operated referring to accompanying drawing 3.If F=0, then the result is kept on the register A; If F=1, then the result preserves back register R.

Influence zone bit: C, DC, Z

(20) instruction: ADDC

Coding: 7 ' b111010x

Operation: (A)+(R)+C-〉(target)

Grammer: [label] ADDC R, F

Describe: the content of register R and C are added on the content of register A.If F=0, then the result is kept on the register A; If F=1, then the result preserves back register R.

Influence zone bit: C, DC, Z

(21) instruction: SUBC

Coding: 7 ' b111011x

Operation: (R)-(A)-C-〉(target)

Grammer: [label] SUBC R, F

Describe: the content of register R is deducted the content of register A, deduct C again.If F=0, then the result is kept on the register A; If F=1, then the result preserves back register R.

Influence zone bit: C, DC, Z

(22) instruction: MUL

Coding: 7 ' b1110001

Operation: (R) * (A) least-significant byte-(target), (R) * (A) most-significant byte-(B)

Grammer: [label] MUL R, F

Describe: the content that the content of register R be multiply by register A.If F=0, then the result is kept on the register A; If F=1, then the result preserves back register R.Most-significant byte is saved in B-register, so generally cooperate the MOVAB instruction to use.Multiplying order takies 1 instruction cycle.The introducing of this instruction strengthens computing power of the present invention greatly, has overcome the weak defective of existing micro controller frame data-handling capacity, thereby can be adapted to the calculated amount intensive applications, as air-conditioning frequency conversion algorithm etc.

Influence zone bit: Z

(23) instruction: MOV

Coding: 7 ' b1100100

Operation: (R)-(target)

Grammer: [label] MOV R, F

Describe: the content of mobile register R.If F=0, then target is register A; If F=1, then target is a register file itself." F=1 " is used for coming the scratchpad register heap by state flag bit " Z ".

Influence zone bit: Z

(24) instruction: MOVA

Coding: 8 ' b11011001

Operation: (A)-(R)

Grammer: [label] MOVA R

Describe: the content of mobile register A is to register R.

(25) instruction: MOVAB

Coding: 7 ' b111001x

Operation: (A)-(B) or (B)-(A)

Grammer: [label] MOVAB F

Describe: according to F=1, the content of mobile register A is to register B; According to F=0, the content of mobile register B is to register A.The introducing of this instruction, making the present invention has increased a kind of addressing mode.

(26) instruction: SWAP

Coding: 7 ' b1100010

Operation: (f＜3:0 〉)-(target＜7:4 〉),

(f＜7:4 〉)-(target＜3:0 〉)

Grammer: [label] SWAP R, F

Describe: the upper and lower nibble exchange of the content of register R.If F=0, then the result is kept on the register A; If F=1, then the result preserves back register R.

When this instruction is carried out, exchange the value of first register high position and low level, again register A or R register are deposited back in the output of operation.

(27) instruction: BC

Coding: 5 ' b10011

Operation: 0-〉(R＜BIT 〉)

Grammer: [label] BC R, BI T

Describe: the BIT position of register R is cleared.BIT is from the 7th～0 of 7～0 expression R.

(28) instruction: BS

Coding: 5 ' b10010

Operation: 1-〉(R＜BIT 〉)

Grammer: [label] BC R, BIT

Describe: the BIT position of register R is put 1.

(29) instruction: JBC

Coding: 5 ' b10001

Operation: if (R＜BIT 〉)=0 then skip next instruction

Grammer: [label] JBC R, BIT

Describe:, then carry out next bar instruction if the BIT position of register R is " 1 ".If the BIT position of register R is " 0 ", then abandon next bar instruction, carry out a NOP instruction, occupy 2 clock period altogether.

(30) instruction: JBC

Coding: 5 ' b10000

Operation: if (R＜BIT 〉)=1 then skip next instruction

Grammer: [label] JBC R, BIT

Describe:, then carry out next bar instruction if the BIT position of register R is 0.If the BIT position of register R is 1, then abandon next bar instruction, carry out a NOP instruction, occupy 2 clock period altogether.

(31) instruction: ADDI

Coding: 7 ' b101001x

Operation: (A)+I-〉(A)

Grammer: [label] ADDI I

Describe: the content of register A adds one 8 bit digital I, and the result preserves back register A.

Influence zone bit: C, DC, Z

(32) instruction: SUBI

Coding: 7 ' b101000x

Operation: I-(A)-(A)

Grammer: [label] SUBI I

Describe: 8 bit digital deduct the content of register A, and the result preserves back register A.

Influence zone bit: C, DC, Z

(33) instruction: ANDI

Coding: 7 ' b1010101

Operation: (A) .AND.I-〉(A)

Grammer: [label] ANDI I

Describe: the content of register A is with 8 bit digital I logical ands, and the result preserves back register A.

Influence zone bit: Z

(34) instruction: IORI

Coding: 7 ' b1010100

Operation: (A) .OR.I-〉(A)

Grammer: [label] IROI I

Describe: the content of register A is with 8 bit digital I logical ORs, and the result preserves back register A.

(35) instruction: XORI

Coding: 7 ' b1010110

Operation: (A) .XOR.I-〉(A)

Grammer: [label] XORI I

Describe: the content of register A is with 8 bit digital I XORs.The result preserves back register A.

Influence zone bit: Z

(36) instruction: ADDCI

Coding: 7 ' b0000010

Operation: (A)+I+C-〉(A)

Grammer: [label] ADDCI I

Describe: the content of register A adds 8 bit digital I, adds after the C again, and the result preserves back register A.

Influence zone bit: C, DC, Z

(37) instruction: SUBCI

Coding: 7 ' b0000011

Operation: I-(A) C-〉(A)

Grammer: [label] SUBCI I

Describe: 8 bit digital deduct the content of register A, subtract after the C again, and the result preserves back register A.

Influence zone bit: C, DC, Z

(38) instruction: MOVI

Coding: 7 ' b10111xx

Operation: I-〉(A)

Grammer: [label] MOVI I

Describe: 8 several immediately I loaded into register A, the value of I is empty, is handled as 0.

(39) instruction: CALL

Coding: 4 ' b0001

Operation: (PC)+1-〉TOS,

I->PC<10:0>，

(PCH<7:3>)->PC<15:11>

Grammer: [label] CALL I

Describe: call subroutine.At first, return address (PC+1) is pressed into storehouse.

11 first level addresses are loaded into PC's＜10:0〉position.All the other high position＜15:11 of PC〉from PCH＜4:3〉load.CALL is the binary cycle instruction.

(40) instruction: LCALL

Coding: 4 ' b01

Operation: (PC)+1-〉TOS,

I->PC<12;0>，

Grammer: [label] LCALL I

Low 13 first level addresses are loaded into PC's＜12:0〉position.LCALL is the binary cycle instruction.TOS is the top of storehouse.

(41) instruction: GOTO

Coding: 4 ' b0010

Operation: I-〉PC＜10:0 〉,

(PCH<7:3>)->PC<15:11>

Grammer: [label] GOTO I (0＜I＜2048)

Describe: GOTO is a unconditional branch, can redirect between register file.11 first level addresses are loaded into PC's＜10:0〉position.All the other high position＜15:11 of PC〉from PCH＜7:3〉load.GOTO is the binary cycle instruction.

(42) instruction: JUMP

Coding: 7 ' b1110000

Operation: I-〉PC＜7:0 〉,

(PCH<7:0>)->PC<15:8>

Grammer: [label] GOTO I (0＜I＜256)

Describe: GOTO is a unconditional branch, can redirect between register file.8 first level addresses are loaded into PC's＜7:0〉position.All the other high position＜15:8 of PC〉from PCH＜7:0〉load.JUMP is the binary cycle instruction.

(43) instruction: MULI

Coding: 7 ' b000011x

Operation: I* (A)-(A)

Grammer: [label] MULI I

Describe: number multiply by the content of register A immediately.The result is kept on the register A, and most-significant byte is saved in B-register.Multiplying order takies 1 instruction cycle.The introducing of this instruction strengthens computing power of the present invention greatly, has overcome the weak defective of existing micro controller frame data-handling capacity, thereby can be adapted to the calculated amount intensive applications, as air-conditioning frequency conversion algorithm etc.

Influence zone bit: C, DC, Z

(44) instruction: RET

Coding: 15 ' b110110000000000

Operation: TOS-〉PC

Grammer: [label] RET

Describe: return from subroutine.Stack pop-up, the top of storehouse (TOS) is loaded in the programmable counter.This is the binary cycle instruction.

(45) instruction: RETIA

Coding: 5 ' b10110

Operation: I-〉(A),

TOS->PC

Grammer: [label] RETIAI

Describe: 8 bit digital are loaded on the register A.Programmable counter loads from the top of storehouse (address of returning).This is the binary cycle instruction.

(46) instruction: RETIE

Coding: 15 ' b110110000001001

Operation: TOS-〉PC,

1->GIE

Grammer: [label] RETIE

Describe: return from interruption, and make global interrupt enable effectively.

When above-mentioned instruction CALL, LCALL, GOTO, JUMP, RET, RETIE, RETIA execution, instruction execution unit produces control signal corresponding, can automatically carry out PC and go out stack operation, the value of current program counter is pressed into storehouse, or, be loaded in the programmable counter from ejection current address, storehouse top.

(47) instruction: CWDT

Coding: 15 ' b0000000_0110_0100

Operation: 00h-〉WDT,

0-〉WDT calibrates in advance,

1->OT

1->LP

Grammer: [label] CWDT

Describe: CWDT instruction replacement WatchDog Timer, the pre-calibration factor of the WatchDog Timer of also resetting, set timeout mode position OT and low power consumption status bit LP simultaneously.

(48) instruction: IDLE

Coding: 15 ' b110_1100_0000_0000

Operation: 00h-〉WDT,

0-〉WDT calibrates in advance,

1->OT

0->LP

Grammer: [label] IDLE

Describe: low power consumption status bit LP is eliminated, and timeout mode position OT is set, and WatchDog Timer and pre-frequency division are eliminated, and processor is in idle condition, and clock oscillator quits work.

When above-mentioned instruction CWDT and IDLE carried out, instruction execution unit produced control signal corresponding, the value of house dog of can resetting.

The application program example:

ORG 00H; Definition first address 00H

JINC 21H, 1; Add 1 and judge the content of register 21H, and write back 21H

AND 22H, 0; 22 content of registers and function register A do the logical and operation, write back function register A

CALL 88H; Call the subroutine at 88H place

ORG?88H

RET

The example explanation:

Above-mentioned assembly code is through compiling, and the binary code that obtains the storage of program memory address and program storage memory is as follows:

Program address binary program code 16 carry system codes

0000H 0110001110110001 63B1H

0001H 0110100100100010 6922H

0002H 0000100010001000 0888H

0088H 0110110000001000 6C08H

Be described in further detail below in conjunction with the program address, binary program code and 16 carry system codes that are provided in above-mentioned application program example and the example instructions, therefrom show CPU for the principle of work of functional module in above-mentioned instruction manipulation and each device of using.

At first power on when carrying out initial reset, the numerical value of 16 program pointers is 0000H, and program pointer points to the first address 0000H of program storage 16 bit address simultaneously, and the content of its storage is 63B1H.

The first step, at first clock of first instruction cycle, 63B1H learns that this instruction adds 1 decision instruction for JINC (command character of operational code correspondence is stated) in summary of the invention by decoding, produces the control signal of JINC; The operand of this instruction is a register 21, promptly the content of register 21 is operated; PC register value 0000H is write the operation that backups of PC_TEMP temporary register; Through binary cycle instruction pre-service, this instruction may be instructed for binary cycle; Do not interrupt and the port variation, interrupt the pretreater free time so interrupt vector processor and port change.Simultaneously program pointer 0000H is done the PC register value and backup to the PC_TEMP register, PC_PLUS adds 1 operation and other relevant treatment of CPU.

Second step, at the second clock of first instruction cycle, finish register addressing by the read data addressing device, be about to register 21H content and read to data bus; Do not interrupt and bit manipulation, so interrupt identification bit processor and bit manipulation processor free time.

The 3rd step, the 3rd clock in first instruction cycle, the result of instruction decode shows the operational data of input: the data fout of the output alua of MUX for exporting in register file, be that the content of register 30H mentioned in the embodiment instruction set and the output alub of another MUX are 01H, i.e. the required numerical value 1 of addition; Data are selected to finish, and ALU will carry out additive operation to the data of 2 inputs according to decoded signal, and additive operation is carried out in the hardware adder of ALU; If it is 0 that addition is exported zero flag position Z later on, this instructs and is one-cycle instruction so, and instruction sequences is carried out, and promptly the PC_PLUS register value reads next bar instruction 6922H as program pointer; If it is 1 that addition is exported zero flag position Z later on, instruction is the binary cycle instruction so, and pipelining segment can insert a blank operation NOP (6C00H), and to continue to finish streamline, promptly PC_PLUS does not do the fetch program storage operation; Port changes terminal processes and idle pulley activation pre-service is idle condition at this moment.

In the 4th step, at the 4th clock of first instruction cycle, the data that the ALU computing finishes write back register 21H (mentioning in an embodiment), the STA[2 of zero flag position Z write state register]; Judged whether that interruption just handles in interrupt handler, whether internal stack is for there being operation etc., not interrupt this moment and storehouse is handled, the content of programmable counter will send program pointer to by the Port Multiplier of streamline so, this moment, program pointer became 0001H, entered next streamline circulation.

Because the functional module of every required each device of instruction is different, will be such as above-mentioned CALL instruction by stack manipulation, PC skip operation, the AND instruction needs function register A participation work or the like.Every instruction code is from decoded operation, all must be through four phase clocks of an instruction cycle, and read next bar instruction at the third phase clock of instruction cycle, thus formed four sections pipeline organization methods of two-stage.

Though disclose the preferred embodiments of the present invention; but one of ordinary skill in the art would recognize that; do not deviating from claims disclosed scope of the present invention and saving under the situation of capacitance spirit, any various modifications, interpolation and replacement all belong to protection scope of the present invention.

Claims

1. digit RISC micro controller structure, it is characterized in that this microcontroller architecture comprises: four sections pipeline organizations of secondary, four sections pipeline organizations of described secondary comprise clock generator, and described clock generator comprises state machine, and four sections pipeline organizations of described secondary also comprise:

Instruction processing unit links to each other with state machine, and decoding, PC backup, binary cycle instruction pre-service, the interrupt vector that is used to finish instruction handled, port changes pretreatment operation;

Data fetch device links to each other with state machine, is used to receive the addressing operation number and the data content of instruction processing unit output, and finishes a plurality of function registers or data register reads, and finishes interrupt request sign pretreatment operation simultaneously;

The data operation device, link to each other with state machine, be used to receive the arithmetic type operational code of instruction processing unit output, the data content of reception data fetch device output, and finish arithmetic logical operation device data operation, port variation processing eventually, idle pulley activation pretreatment operation, read next bar instruction simultaneously;

Data are write return device, link to each other with state machine, be used for the operation result of data operation device partly done according to the operand addressing of instruction processing unit and write back operations, comprise finish that arithmetical logic device data write back, internal interrupt and storehouse handle, finish PC simultaneously and handle, PC handles and comprises that PC adds 1, PC pops, the PC redirect;

Described clock generator is used for producing four phase clock signals by described state machine, produces four sections required synchronizing clock signals of pipeline organization of described secondary simultaneously.

2. 8 digit RISC micro controller structures according to claim 1 is characterized in that described state machine is only heat sign indicating number state machine.

3. 8 digit RISC micro controller structures according to claim 1 is characterized in that microcontroller architecture also comprises a cover reduced instruction set computer, and this instruction set comprises 48 instructions; The output order sign indicating number of described instruction processing unit is divided into 3 classes: byte manipulation class, bit manipulation class and number operation immediately and control class.

4. 8 digit RISC micro controller structures according to claim 3 is characterized in that described byte manipulation class instruction has 28, are respectively arithmetic logical operation operation and blank operation to function register or register R; The structure of arithmetic logical operation writes destination register according to zone bit F, if F is 0, destination register is that data are write the function register A1 in the return device; If F is 1, destination register is that register R or data are write the function register B1 in the return device.

5. 8 digit RISC micro controller structures according to claim 4, it is characterized in that comprising in the described instruction set 1 program and carry out the function register data movement instruction, among the content write-in functions register B1 of this instruction with function register A0, or among the content write-in functions register A1 with function register B0, and do according to F and to write back operations, when F is 0, among the content write-in functions register A1 with function register B0, when F is 1, among the content write-in functions register B1 with function register A0, this instruction manipulation code sign is MOVAB.

6. 8 digit RISC micro controller structures according to claim 3 is characterized in that comprising in the described instruction set 2 programs and carry out the call subroutine instruction, and these instructions will be counted the assignment programmable counter immediately, and the value with programmable counter is pressed into storehouse then; These instructions comprise call subroutine, location call subroutine longways, and the corresponding respectively command character of its operational code is CALL, LCALL.