CN101189728A - 利用改进的npn双极晶体管基极接入电阻的方法和器件 - Google Patents

利用改进的npn双极晶体管基极接入电阻的方法和器件 Download PDF

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CN101189728A
CN101189728A CNA2006800193421A CN200680019342A CN101189728A CN 101189728 A CN101189728 A CN 101189728A CN A2006800193421 A CNA2006800193421 A CN A2006800193421A CN 200680019342 A CN200680019342 A CN 200680019342A CN 101189728 A CN101189728 A CN 101189728A
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emitter
transistor
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vertical transistor
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谭博成
彼得·戴克勒
西塞罗·西尔韦拉·沃谢
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Koninklijke Philips NV
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
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    • H01L29/7322—Vertical transistors having emitter-base and base-collector junctions leaving at the same surface of the body, e.g. planar transistor
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H01L29/7371—Vertical transistors
    • H01L29/7378—Vertical transistors comprising lattice mismatched active layers, e.g. SiGe strained layer transistors

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Abstract

本发明涉及一种结构，此结构包括依然共用共同的DTI区和单个大片基极多晶硅的多个短发射极。这种结构允许基极电流向4个方向(即2维)而不是仅2个方向上流动。因而大大减小了晶体管基极电阻，这对于使NPN晶体管获得更好的RF特性和高频噪声特性是至关重要的。

Description

利用改进的NPN双极晶体管基极接入电阻的方法和器件
本申请要求共同未决的于2005年6月1日提出的序列号是60/686502、题目为“METHOD TO IMPROVE BASE ASCCESS RESISTANCEFOR NPN BIPOLAR TRANSISTOR”的美国临时专利申请的优先权，在此其内容以引用方式并入本文。
技术领域
本发明通常涉及半导体器件结构，尤其是用于高速RF设计具有垂直NPN晶体管的半导体器件结构。NPN晶体管出现在很多类型的收发器里，包括手机，车用雷达，超宽频带无线电，无线局域网络(LAN)，卫星接收器和任何对噪声敏感的产品。垂直NPN是用于高速RF设计的重要部件。其高速和低噪声特性大大依赖于基极电阻。
背景技术
当前，垂直NPN晶体管100以双侧基极接触的形式形成，如图1所示。在现有技术中，NPN晶体管采用单个长发射极条101。图2示出NPN晶体管100的截面图A-A。在包含N掩埋层204的P型基片203上形成所述NPN晶体管。深槽隔离(DTI)区211处在N掩埋层204的每侧。浅槽隔离区205限定了n+集电极区206和发射极区207。集电极区206位于N掺杂区208上面。发射极电极209覆盖了氮化物/氧化物隔离层210，此隔离层部分覆盖了P+基极接触区201。单SiGe层处于发射极区207和发射极电极209之间。单个长发射极条101具有相对高的基极电阻，这是由于基极电流被限制在指向所述器件的每个长侧边上的基极接触区202的仅两个侧面方向流动。这种包括单个长发射极条101的布局限制了垂直NPN的特性。
因此，需要一种能提高晶体管RF和噪声特性的垂直NPN晶体管的改进布局。
一种解决办法采用了短发射极长度NPN。然而，此种解决办法不能产生足够的驱动电流用来给晶体管供电。此种办法需要并联连接多个短发射极NPN晶体管。从而可以使短发射极长度的NPN产生同单个长发射极条结构一样的驱动电流。所述方法的主要缺点是寄生电容的大幅度增加，这会大大降低晶体管的性能。
发明内容
把现有技术的单个长发射极条沿其长度方向划分为多个短发射极长度的布局克服了现有技术的局限性。本发明涉及一种结构，此结构包括依然共用共同DTI区和单个大片基极多晶硅的多个短发射极。这种结构允许基极电流向4个方向(即2维)而不是2个方向上流动。因而大大减小了基极电阻，这对于使NPN晶体管获得更好的RF特性和高频噪声特性是至关重要的。而且这种结构不需要额外的会降低晶体管性能的驱动电流。因此改进了RF特性和噪声特性。
通过下面关于本发明各个方面的详细描述，采取同附图结合的方式，本发明的这些以及其它特点将更容易理解。
附图说明
图1描述了具有单个长发射极条的NPN晶体管；
图2描述了图1的NPN晶体管的截面图；
图3描述了具有多个短发射极条的NPN晶体管；
图4描述了图3的NPN晶体管的截面图；
图5描述了最小噪声和频率的关系示图；
图6描述了噪声阻值和频率的关系示图；
图7描述了频率衰减和单个长发射极条结构的电流的关系示图；
图8描述了频率衰减和多个短发射极条结构的电流的关系示图；
具体实施方式
本文所述的实施例提供了一种新的具有晶体管的半导体器件。
特定的设计和加工工艺大大增加了使用双极或BiCMOS工艺形成的垂直NPN或PNP晶体管的基极电流。所述器件提供了一种有效的用于应用在诸如移动电话、无线LAN、超宽频带、或任何收发器产品的收发器。
晶体管的一个例子是垂直晶体管。依据本发明，NPN布局将传统的单个长发射极长度条分为多个短发射极长度。图3描述了具有多个短发射极条301的NPN晶体管300。所述多个短发射极条301共用共同DTI区和单片基极多晶硅。图4描述了图3的横截面图B-B。在包含N掩埋层304的p型基片303上形成所述NPN晶体管。深槽隔离(DTI)区311处在多晶硅层304的两侧，并对短发射极条301是共用的。浅槽隔离区305限定了n+集电极区306和发射极区307。集电极区306位于N掺杂区308上面。发射极电极309覆盖了氮化物/氧化物隔离层310，此隔离层310部分地覆盖了p+基极接触区312。单SiGe层处于发射极区307和发射极电极309之间。多个短发射极条301允许基极电流向4个方向流动(即2维)-侧面地和垂直地朝短发射极条301每侧的基极接触区312流动。注意每个短发射极条301共用DTI区311和基极多晶硅304。这种结构允许更好的电流流动从而减少了晶体管的基极电阻。
图5和图6突出了本发明的噪声改进。图5示出了沿x轴的测量频率和沿y轴的噪声量。曲线501表现现有技术的单条长发射极结构，曲线502示出了短发射极条结构。曲线502示出了比曲线501更好的最小噪声量，显示了低噪声特性。图6描述了沿x轴的测量频率和沿y轴的测量噪声阻抗。曲线601表现现有技术的单条长发射极结构，曲线602示出了短发射极条结构。曲线602示出比曲线601更好的最低噪声量，显示了更好的噪声阻抗。
图7和图8描述了本发明的运算速度改进。图7示出沿x轴单位为安培的测量电流和单位为Hz的fa。Fa是描述用于RF装置的电流型逻辑电路的最大运算速度的极限电路级优值系数。曲线701描述了峰值fa在2V时小于25GHz。此曲线是从单个长线路发射极测量得到的。图8描述了短发射极条结构的沿x轴单位为安培的测量电流和单位为Hz的fa。曲线801描述了峰值fa在2V时大约为20GHz。这显示了超出单个长发射极条结构几乎20％的改进。
所述器件制造过程的步骤基本如下：
(1)在第二导电类型(即p型)的基片303内形成第一导电类型(即n型)区304；
(2)在第一导电类型区周围形成深槽隔离(DTI)区(311)；
(3)在第一导电类型区域的上方，通过形成至少一个基极层、一个发射极区、和一个集电极区来形成至少两个发射极条。发射极条共用DTI区和基极区。
使用NPN或PNP双极工艺流程能形成所述晶体管。也可以使用NPN或PNP双极互补金属氧化物(BiCMOS)工艺流程形成所述晶体管。所述晶体管也可以形成与多个集成方案兼容，例如双层多晶硅、选择性外延、非选择性外延、或者凸起外基极区结构。
呈现本发明的以上描述的目的是描述和说明，而不是为了枚举或将本发明限制为公开的确切形式，并且可以进行很多种修改和变化。这些对所属领域的技术人员很明显的修改和变化应该被包括在由权利要求所限定的本发明的范围内。

Claims (9)

1.一种垂直晶体管，包括：
至少2个发射极条(301)，每个包括：
一个基极区，一个发射极区，和一个集电极区，其中所述的至少2个发射极条(301)共用一个共同DTI区(311)和一个单基极多晶硅(304)。
2.如权利要求1所述的垂直晶体管，其中所述晶体管是NPN晶体管。
3.如权利要求1所述的垂直晶体管，其中所述晶体管是PNP晶体管。
4.一种形成垂直晶体管的方法，包括：
在第二导电类型基片(303)内形成第一导电类型区(304)；
在第一导电类型区(304)的周围形成深槽隔离(DTI)区(311)；
在第一导电类型区(304)的上方通过形成至少一个基极层、一个发射极区、和一个集电极区来形成至少两个发射极条(301)，
其中所述的至少两个发射极条(301)共用一个共同DTI区域(311)和单基极多晶硅。
5.如权利要求4所述的方法，其中所述垂直晶体管使用NPN或PNP双极工艺流程形成。
6.如权利要求4所述的方法，其中所述垂直晶体管使用NPN或PNP双极互补金属氧化物(BiCMOS)工艺流程形成。
7.如权利要求4所述的方法，其中所述晶体管被形成为与多个集成方案兼容。
8.如权利要求7所述的方法，其中多个集成方案选自于包括双层多晶硅、选择性外延、非选择性外延、或者凸起外基极区结构的一组方案。
9.如权利要求4所述，其中所述至少两个发射极条沿一条线形成。
CNA2006800193421A 2005-06-01 2006-06-01 利用改进的npn双极晶体管基极接入电阻的方法和器件 Pending CN101189728A (zh)

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