CN101187765B - Film transistor array substrate for liquid crystal display and manufacture thereof - Google Patents
Film transistor array substrate for liquid crystal display and manufacture thereof Download PDFInfo
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- CN101187765B CN101187765B CN2007101820667A CN200710182066A CN101187765B CN 101187765 B CN101187765 B CN 101187765B CN 2007101820667 A CN2007101820667 A CN 2007101820667A CN 200710182066 A CN200710182066 A CN 200710182066A CN 101187765 B CN101187765 B CN 101187765B
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Abstract
The invention relates to a thin film transistor array base plate of a liquid crystal display and a manufacturing method, wherein a stripping way and a partly-adjustable photomask are utilized, and a first metal layer and a second metal layer are respectively defined by only two photomasks. The process comprising steps: a transparent conducting layer is formed on a base plate, the transparent conducting layer and the base plate are patterned to form at least an active line ditch and at least a capacity line ditch, and the active line ditch comprises at least a TFT region, an active line region and at least a first terminal region, the capacity line ditch comprises at least a capacity line region and at least a second terminal region, and the first metal layer, a dielectric layer, a silicon layer, and a doping silicon layer are formed in turn, and the second metal layer is formed on the upper portions of the doping silicon layer and the transparent conducting layer, moreover, by using a micro shadow etching way of single exposure, a TFT structure is defined in the TFE region, a reservoir capacitor and a datawire are defined in the capacity line region and two terminal structures are respectively defined in the first and the second terminal regions simultaneously.
Description
Technical field
The present invention relates to a kind of LCD and manufacture method thereof, relate in particular to a kind of thin film transistor (TFT) (thin film transistor of LCD; TFT) array base palte and manufacture method thereof.
Background technology
Recently photoelectric technology is constantly weeded out the old and bring forth the new, and adds the arrival of digital times, has promoted the flourish of LCD market.LCD because have that high image quality, volume are little, in light weight, numerous advantages such as low driving voltage and low consumpting power.Therefore be widely used in PDA(Personal Digital Assistant), mobile phone, shoot with video-corder projector, on consumer communication such as mobile computer, desktop display, automobile-used display and projection TV or the electronic product, and replace cathode-ray tube (CRT) gradually, and become the main flow of display.
The manufacture method of the thin film transistor (TFT) array of LCD (TFT Array) substrate mainly is to combine with deposition, little shadow and three kinds of different process of etching now.In these three kinds of technologies, the production cost shared with lithography process is the highest.Therefore to how to reduce the needed lithography process number of tft array substrate whole manufacturing process, also promptly reduce required photomask number, just become panel big factory in various countries' to reduce the primary problem of production of liquid crystal displays cost.
Summary of the invention
Technical matters to be solved by this invention is to provide thin film transistor (TFT) (TFT) array base palte and the manufacture method thereof of several LCD, the whole manufacturing process of thin-film transistor array base-plate only needs the twice photomask just can finish, and can reduce the production cost of LCD and improve its output.
For achieving the above object, the invention provides a kind of thin-film transistor array base-plate of LCD.Above-mentioned thin film transistor base plate comprises following element: a substrate, has a transparency conducting layer on it, utilize the first road photomask in this transparency conducting layer and this substrate, to form parallel staggered at least one sweep trace irrigation canals and ditches and at least one electric capacity duct canal, these at least one sweep trace irrigation canals and ditches have at least one TFT zone, one scan line zone and at least one the first terminal zone, and this at least one electric capacity duct canal has at least one electric capacity line zone and at least one second terminal area; Deposit a first metal layer, a dielectric layer, an amorphous silicon layer and a doped amorphous silicon layer respectively in regular turn among described at least one sweep trace irrigation canals and ditches and this at least one electric capacity duct canal;
One second metal level is formed on described doped amorphous silicon layer and this transparency conducting layer;
One thin film transistor (TFT) is arranged in this TFT zones of this sweep trace irrigation canals and ditches, and this thin film transistor (TFT) has a grid, and one source pole and drain electrode at least;
At least one sweep trace is arranged in this sweep trace zones of this sweep trace irrigation canals and ditches, and is electrically connected with the grid of this thin film transistor (TFT);
One reservior capacitor is arranged in the electric capacity line zone of this electric capacity duct canal;
One data line is arranged in this electric capacity line zone, and crosses over these at least one sweep trace irrigation canals and ditches and this at least one electric capacity duct canal, and an electrode of the source electrode of this at least one data line and this thin film transistor (TFT) or drain electrode is electrically connected; And
At least one pixel electrode between this at least one data line and this at least one sweep trace on this substrate, and is electrically connected with the source electrode of this thin film transistor (TFT) or another electrode of drain electrode;
The two-terminal structure lays respectively in this first and second terminal area;
Wherein, the upper electrode arrangement of described thin film transistor (TFT), described reservior capacitor, described data line and described two-terminal structure are to define out by the second road photomask.
In addition, can also comprise be arranged in above-mentioned electric capacity duct canal and sweep trace irrigation canals and ditches end and terminal substrate on a plurality of weld pads.
For achieving the above object, the present invention proposes a kind of thin-film transistor array base-plate of LCD, and this thin-film transistor array base-plate comprises:
One substrate, has a transparency conducting layer on it, utilize the first road photomask in this transparency conducting layer and this substrate, to form parallel staggered at least one sweep trace irrigation canals and ditches and at least one electric capacity duct canal, these at least one sweep trace irrigation canals and ditches have at least one TFT zone, one scan line zone and at least one the first terminal zone, this at least one electric capacity duct canal has at least one electric capacity line zone and at least one second terminal area, and this first terminal zone is decremented to zero with the irrigation canals and ditches degree of depth of this second terminal area in this substrate toward end direction; Deposit a first metal layer, a dielectric layer, an amorphous silicon layer and a doped amorphous silicon layer respectively in regular turn among described at least one sweep trace irrigation canals and ditches and this at least one electric capacity duct canal and on this substrate around this first terminal zone and the terminal peripheral part of this second terminal area;
One second metal level is formed on sacrifice layer, this transparency conducting layer and this doped amorphous silicon layer that exposes;
One thin film transistor (TFT) is arranged in this TFT zones of this sweep trace irrigation canals and ditches, and this thin film transistor (TFT) has a grid, and one source pole and drain electrode at least;
At least one sweep trace is arranged in this sweep trace zones of this sweep trace irrigation canals and ditches, and is electrically connected with the grid of this thin film transistor (TFT);
One reservior capacitor is arranged in the electric capacity line zone of this electric capacity duct canal;
One data line is arranged in this electric capacity line zone, and crosses over these at least one sweep trace irrigation canals and ditches and this at least one electric capacity duct canal, and an electrode of the source electrode of this at least one data line and this thin film transistor (TFT) or drain electrode is electrically connected; And
At least one pixel electrode between this at least one data line and this at least one sweep trace on this substrate, and is electrically connected with the source electrode of this thin film transistor (TFT) or another electrode of drain electrode;
The two-terminal structure lays respectively in this first and second terminal area;
Wherein, the upper electrode arrangement of described thin film transistor (TFT), described reservior capacitor, described data line and described two-terminal structure are to define out by the second road photomask.
For achieving the above object, the present invention proposes a kind of thin-film transistor array base-plate of LCD, and this thin-film transistor array base-plate comprises:
One substrate, has a transparency conducting layer on it, utilize the first road photomask in this transparency conducting layer and this substrate, to form parallel staggered at least one sweep trace irrigation canals and ditches and at least one electric capacity duct canal, these at least one sweep trace irrigation canals and ditches have at least one TFT zone, one scan line zone and at least one the first terminal zone, and this at least one electric capacity duct canal has at least one electric capacity line zone and at least one second terminal area; Deposit a first metal layer, a dielectric layer, an amorphous silicon layer and a doped amorphous silicon layer and a protective seam respectively in regular turn among described at least one sweep trace irrigation canals and ditches and this at least one electric capacity duct canal;
Have source electrode and drain region in this TFT zone, have top electrode zone and data line zone in this electric capacity line zone;
One doped amorphous silicon layer and one second metal level are formed at respectively on described source electrode and drain region, this top electrode zone, this data line zone, this first and second terminal area and the residual photoresist layer in regular turn;
One thin film transistor (TFT) is arranged in this TFT zones of this sweep trace irrigation canals and ditches, and this thin film transistor (TFT) has a grid, and one source pole and drain electrode at least;
At least one sweep trace is arranged in this sweep trace zones of this sweep trace irrigation canals and ditches, and is electrically connected with the grid of this thin film transistor (TFT);
One reservior capacitor is arranged in the electric capacity line zone of this electric capacity duct canal;
One data line is arranged in this electric capacity line zone, and crosses over these at least one sweep trace irrigation canals and ditches and this at least one electric capacity duct canal, and an electrode of the source electrode of this at least one data line and this thin film transistor (TFT) or drain electrode is electrically connected; And
At least one pixel electrode between this at least one data line and this at least one sweep trace on this substrate, and is electrically connected with the source electrode of this thin film transistor (TFT) or another electrode of drain electrode;
The two-terminal structure lays respectively in this first and second terminal area;
Wherein, the upper electrode arrangement of described thin film transistor (TFT), described reservior capacitor, described data line and described two-terminal structure are to define out by the second road photomask.
And for achieving the above object, the present invention proposes a kind of manufacture method of thin-film transistor array base-plate of LCD.Form earlier transparency conducting layer on substrate, patterned transparent conductive layer and substrate again are to form parallel staggered at least one sweep trace irrigation canals and ditches and at least one electric capacity duct canal therein.In sweep trace irrigation canals and ditches and electric capacity duct canal, form the first metal layer, dielectric layer, silicon layer and doped silicon layer in regular turn then, form second metal level in going up of doped silicon layer and transparency conducting layer again.Then, use the lithography method of half mode exposure to define the TFT structure simultaneously in the TFT zone, storage capacitors and data line are in electric capacity line zone, and terminal structure is finished the manufacturing of tft array substrate respectively in first and second terminal area.
And the present invention also proposes the manufacture method of the thin-film transistor array base-plate of another kind of LCD.Form transparency conducting layer and sacrifice layer on substrate in regular turn, above-mentioned sacrifice layer, transparency conducting layer and the substrate of patterning then is to form parallel staggered at least one sweep trace irrigation canals and ditches and at least one electric capacity duct canal therein.Form the first metal layer, dielectric layer, silicon layer and doped silicon layer in regular turn then in above-mentioned sweep trace irrigation canals and ditches and electric capacity duct canal and on the substrate of the terminal periphery of above-mentioned two kinds of irrigation canals and ditches, wherein above-mentioned dielectric layer is identical with the material of sacrifice layer.Follow the sidewall that above-mentioned sacrifice layer of lateral erosion and dielectric layer expose, its outline is retreated, form second metal level in going up of the sacrifice layer that exposes, transparency conducting layer and doped silicon layer again.Use the lithography method of half mode exposure, define the TFT structure simultaneously in the TFT zone, storage capacitors and data line are in electric capacity line zone, and terminal structure is respectively in first and second terminal area.Go up to form protective seam in each layer that exposes then, remove residual photoresist layer more in regular turn and go up each layer, and each layer on the sacrifice layer that exposes of sidewall, dielectric layer and aforementioned the two its, finish the technology of tft array substrate.
And the present invention also proposes the manufacture method of the thin-film transistor array base-plate of another LCD.Form transparency conducting layer on substrate, above-mentioned transparency conducting layer and the substrate of patterning again is to form parallel staggered at least one sweep trace irrigation canals and ditches and at least one electric capacity duct canal therein.In above-mentioned sweep trace irrigation canals and ditches and electric capacity duct canal, form the first metal layer, dielectric layer, silicon layer and protective seam in regular turn.Then; use the lithography method of half mode exposure; in the TFT zone, remove protective seam and doped amorphous silicon layer to define regions and source; in electric capacity line zone, remove protective seam and doped amorphous silicon layer to define top electrode zone and data line zone, in first and second terminal area, remove protective seam, doped amorphous silicon layer and amorphous silicon layer to expose this first metal layer.
Then, form the doped silicon layer and second metal level in regular turn on regions and source, top electrode zone, data line zone, first and second terminal area and residual photoresist layer.The exposed sidewalls of lateral erosion transparent electrode layer retreats the outline of transparent electrode layer again, and removes this remaining photoresist layer.
The twice photomask by the foregoing description as can be known, utilizes semi-modulation type photomask and divests method (lift-off), as long as can be finished the technology of whole tft array substrate.Therefore be very helpful for the reduction of manufacturing cost and the lifting of production capacity.
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Description of drawings
For above and other objects of the present invention, feature, advantage and embodiment can be become apparent, being described in detail as follows of appended accompanying drawing:
Figure 1A-1D is the manufacturing process cross-sectional view according to a kind of LCD tft array substrate of the embodiment of the invention one;
Fig. 2 A-2B is the schematic top plan view of the LCD tft array substrate of the embodiment of the invention one in the different fabrication phases;
Fig. 3 A-3G is the manufacturing process cross-sectional view according to a kind of LCD tft array substrate of the embodiment of the invention two;
Fig. 4 A-4B is the schematic top plan view of the LCD tft array substrate of the embodiment of the invention two in the different fabrication phases;
Fig. 5 A-5E is the manufacturing process cross-sectional view according to a kind of LCD tft array substrate of the embodiment of the invention three;
Fig. 6 A-6B is the schematic top plan view of the LCD tft array substrate of the embodiment of the invention three in the different fabrication phases.
Wherein, Reference numeral:
100,300,500: substrate
102,302,502: transparency conducting layer
102a, 302a, 502a: pixel electrode
104,306,504: the first photoresist layers
106,308,506: the sweep trace irrigation canals and ditches
106a, 308a, 506a:TFT zone
106b, 308b, 506b: sweep trace zone
106c, 308c, 506c: terminal area
108,310,508: electric capacity duct canal
108b, 310b, 508b: electric capacity line zone
108c, 310c, 508c: terminal area
112,312,512: the first metal layer
114,314,514: dielectric layer
116,316,516: amorphous silicon layer
118,318,518: doped amorphous silicon layer
118a, 318a, 518a: ohmic contact layer
120,320,520: the second metal levels
120a, 320a, 520a: source/drain
120b, 320b, 520b: data line
120c, 320c, 520c: top electrode
520d: weld pad
122,322,522: the second photoresist layers
324,524: protective seam
Embodiment
Below will clearly demonstrate spirit of the present invention with accompanying drawing and detailed description.Those skilled in the art after understanding embodiments of the invention, when can be by the technology of teachings of the present invention, change and modification, it does not break away from spirit of the present invention and scope.
Embodiment one
Figure 1A-1D is the manufacturing process cross-sectional view according to a kind of LCD tft array substrate of the embodiment of the invention, and Fig. 2 A-2B is the schematic top plan view of LCD tft array substrate in the different fabrication phases.
Please be simultaneously with reference to Figure 1A and Fig. 2 A, Fig. 2 A is the schematic top plan view of Figure 1A.On substrate 100, form the transparency conducting layer 102 and first photoresist layer 104 in regular turn, use the first road photomask to carry out lithography technology then, on substrate 100, form sweep trace irrigation canals and ditches 106 and electric capacity duct canal 108 simultaneously.The substrate 100 of part still is covered with by the transparency conducting layer 102 and first photoresist layer 104 in regular turn beyond sweep trace irrigation canals and ditches 106 and the electric capacity duct canal 108.
Sweep trace irrigation canals and ditches 106 can be divided into three zones in Fig. 2 A, and it is respectively TFT zone 106a (the section AA ' of Figure 1A), sweep trace zone 106b and terminal area 106c.108 in electric capacity duct canal only is divided into two zones, and it is respectively electric capacity line zone 108b (the section BB ' of Figure 1A) and terminal area 108c (the section CC ' of Figure 1A).Above-mentioned terminal area 106c is the same with the structure of 108c, and therefore, the back can not distinguished especially to the narration of terminal area 106c and 108c.
Please be simultaneously with reference to Figure 1B and Fig. 2 A, in sweep trace irrigation canals and ditches 106 on substrate 100 and the electric capacity duct canal 108 and deposit the first metal layer 112, dielectric layer 114, amorphous silicon layer 116 and doped amorphous silicon layer 118 in regular turn on first photoresist layer 104.Utilize the appropriate solvent of prior art that first photoresist layer 104 is divested then, the first metal layer 112, dielectric layer 114, amorphous silicon layer 116 and the doped amorphous silicon layer 118 that will be positioned at jointly on first photoresist layer 104 divest together, the first metal layer 112, dielectric layer 114, amorphous silicon layer 116 and doped amorphous silicon layer 118 in only remaining sweep trace irrigation canals and ditches 106 and the electric capacity duct canal 108.
The first metal layer 112 in the 106a of the TFT of sweep trace irrigation canals and ditches 106 zone, dielectric layer 114 and amorphous silicon layer 116 are respectively in regular turn as grid, gate dielectric layer and the channel region of TFT.The first metal layer 112 in the 108b of the reservior capacitor zone of electric capacity duct canal 108 is as the electric capacity line of reservior capacitor, the double usefulness of doing the bottom electrode of reservior capacitor.
In Fig. 1 C, on substrate 100, form second metal level 120 and second photoresist layer 122 in regular turn.Afterwards, be that the second road photomask comes second photoresist layer 122 is carried out lithography process one time for example with semi-modulation type photomask, with patterning second photoresist layer 122, form profile as second photoresist layer 122 of Fig. 1 C.Second photoresist layer 122 on the channel region of pixel region and TFT zone 106a is the part exposure, therefore also stays second photoresist layer 122 of segment thickness.And the area of grid of the zone between pixel region and the data line, TFT zone 106a, sweep trace zone 106b and terminal area 106c, 108c be for exposing fully, so second photoresist layer 122 on these zones is developed liquid fully and removes.Therefore the then not exposure fully of regions and source, reservior capacitor zone 108b and the data line zone of other TFT zone 106a stays the second the thickest photoresist layer 122 of thickness.
Please also refer to Fig. 1 D and Fig. 2 B, Fig. 2 B is the schematic top plan view of Fig. 1 D.Down carry out etching with the anisotropic etching method.Because second photoresist layer 122 is in the variable thickness of zones of different, so the etch depth of zones of different is also different.
In the part of the section AA ' of Fig. 1 D, at the TFT zone 106a that is covered by second photoresist layer 122 of segment thickness, its down etching till exposing amorphous silicon layer 116.At this, define second metal level 120 and doped amorphous silicon layer 118 simultaneously, with the source/drain 120a that forms TFT with and under ohmic contact layer 118a.Zone in that TFT zone 106a has second photoresist layer 122 of segment thickness to be covered on every side only removes second metal level 120.And TFT zone 106a does not cover the zone of second photoresist layer 122 on every side, and then second metal level 120 all is removed with transparency conducting layer 102, and transparency conducting layer 102 is defined pixel electrode 102a.
In the part of the section BB ' of Fig. 1 D, at the electric capacity line zone 108b that exposes, down etching is till exposing the first metal layer 112.The zone that is only covered by second photoresist layer 122 of segment thickness around the 108b of electric capacity line zone then only removes second metal level 120.Therefore, can be in this zone by definition second metal level 120, to form the top electrode 120c of data line 120b and reservior capacitor simultaneously.
In the part of the section CC ' of Fig. 1 D, at the terminal area 108c that exposes, down etching is till exposing the first metal layer 112.And in the peripheral region of terminal area 108c, then second metal level 120 all is removed with transparency conducting layer 102, exposes substrate 100.
Remove at last the second remaining photoresist layer 122 again, finish the technology of tft array substrate.
In embodiment one, utilize the first road photomask to form sweep trace irrigation canals and ditches and electric capacity duct canal earlier in transparency electrode and substrate, preliminary definition goes out the TFT zone relevant with sweep trace and terminal area and reservior capacitor zone and the terminal area relevant with the electric capacity line.Be that sweep trace irrigation canals and ditches and electric capacity duct canal deposit after the required different material layer in regular turn, re-use the second road photomask (for example semi-modulation type photomask) follow-up required TFT structure, capacitor top electrode structure and data line structure are defined out one by one.Therefore, the technology of whole LCD tft array substrate only needs the twice photomask to finish.
Embodiment two
Fig. 3 A-3G is the manufacturing process cross-sectional view according to a kind of LCD tft array substrate of the embodiment of the invention, and Fig. 4 A-4B is the schematic top plan view of LCD tft array substrate in the different fabrication phases.
In Fig. 3 A, at first, on substrate 300, form transparency conducting layer 302, sacrifice layer 304 and first photoresist layer 306 in regular turn.Be that the first road photomask carries out lithography process one time to first photoresist layer 306 for example then,, form the profile of first photoresist layer 306 as shown in Figure 3A with patterning first photoresist layer 306 with semi-modulation type photomask.In electric capacity line zone, sweep trace zone is complete exposure area with the TFT area of grid, so on these zones without any first photoresist layer 306.The terminal area terminal in sweep trace zone and electric capacity line zone be then along the exposure dose that reduces by first photoresist layer 306 on the direction of end gradually, allows the thickness of first photoresist layer 306 that covered on these zones successively decrease gradually.Other zone is then unexposed fully, is coated with the first complete photoresist layer 306 on it.
Please also refer to Fig. 3 B and Fig. 4 A, Fig. 4 A is the schematic top plan view of Fig. 3 B.Serves as cover curtain at this with first photoresist layer 306, and down the sacrifice layer 304, the transparency conducting layer 302 and substrate 300 that go out of etch exposed in regular turn forms sweep trace irrigation canals and ditches 308 and electric capacity duct canal 310 on substrate 300.Sweep trace irrigation canals and ditches 308 can be divided into three zones, are respectively TFT zone 308a (the section AA ' of Fig. 3 B), sweep trace zone 308b and terminal area 308c.310 in electric capacity duct canal can be divided into electric capacity line zone 310b (the section BB ' of Fig. 3 B) and terminal area 310c (the section CC ' of Fig. 3 B).Terminal area 308c, the 310c of sweep trace irrigation canals and ditches 308 and electric capacity duct canal 310 ends, its degree of depth is shallow more for past more end, and is consistent with the height change profile of first photoresist layer 306 of Fig. 3 A section CC '.In addition, because above-mentioned terminal area 308c is the same with the structure of 310c, so other can not divided especially to the narration of terminal area 308c and 310c in the back.
Please refer to Fig. 3 C, follow among sweep trace irrigation canals and ditches 308 and electric capacity duct canal 310, and depositing the first metal layer 312, dielectric layer 314, amorphous silicon layer 316 and doped amorphous silicon layer 318 in regular turn on first photoresist layer 306 with on the transparency conducting layer 302 that exposes.Above-mentioned sacrifice layer 304 is identical with the material of dielectric layer 314.In the section CC ' of Fig. 3 C part, because terminal area 310c has the inclined-plane, the bottom of electric capacity line zone 310b and the upper surface of substrate 300 are coupled together, so above-mentioned the first metal layer 312, dielectric layer 314, amorphous silicon layer 316 and doped amorphous silicon layer 318, whether good successfully the bottom of self-capacitance line zone 310b is connected on the transparency conducting layer 302, and can not be subjected to step coverage rate (step coverage) the restriction of deposition process.
Please refer to Fig. 3 D, earlier, the outline of said two devices is retreated to wait dielectric layer 314 and sacrifice layer 304 that comes the lateral erosion side to have to expose to etching method.And then, first photoresist layer 306 is divested with the appropriate solvent of prior art.Jointly, the first metal layer 312, dielectric layer 314, the amorphous silicon layer 316 that is positioned on first photoresist layer 306 also divested remaining structure shown in Fig. 3 D with doped amorphous silicon layer 318.
The first metal layer 312, dielectric layer 314 that is positioned at TFT zone 308a and amorphous silicon layer 316 are respectively as grid, gate dielectric layer and the channel region of TFT.The first metal layer 312 that is positioned at electric capacity line zone 310b is then as the usefulness of the bottom electrode and the electric capacity line of reservior capacitor.
Please refer to Fig. 3 E, deposition one deck second metal level 320 on sacrifice layer 304 and transparency conducting layer 302 that exposes and doped amorphous silicon layer 318, and then be coated with second photoresist layer 322.Then, be that the second road photomask comes second photoresist layer 322 is carried out lithography process one time for example with semi-modulation type photomask, with patterning second photoresist layer 322, form the profile of second photoresist layer 322 shown in Fig. 3 E.
Please refer to Fig. 3 F, down carry out etching with the anisotropic etching method.Because second photoresist layer 322 is in the variable thickness of zones of different, so the etch depth of zones of different is also different.
In the part of the section AA ' of Fig. 3 F, at the TFT zone 308a that is covered by second photoresist layer 322 of segment thickness, its down etching till exposing amorphous silicon layer 316.At this, define second metal level 320 and doped amorphous silicon layer 318 simultaneously, with the source/drain 320a that forms TFT with and under ohmic contact layer 318a.Do not cover the zone of second photoresist layer 322 around the 308a of TFT zone, second metal level 320, sacrifice layer 304 all are removed with transparency conducting layer 302, so that transparency conducting layer 302 is defined pixel electrode 302a.
In the part of the section BB ' of Fig. 3 F, at the electric capacity line zone 108b that exposes, down etching is till exposing the first metal layer 312.At this, define second metal level 320, to form the top electrode 320c of data line 320b and reservior capacitor simultaneously.
In the part of the section CC ' of Fig. 3 F, at the terminal area 308c that exposes, all down etching till exposing dielectric layer 314.The zone that is not covered by second photoresist layer 322 around terminal area 308c, then substrate each layer more than 300 all is removed, and exposes substrate 300.
Then, deposition layer protective layer 324 on the various material layers that expose.The material of above-mentioned protective seam 324 for example can be dielectric material, as silicon nitride, monox or silicon oxynitride.Divest then second photoresist layer 322 with and on protective seam 324, obtain structure as Fig. 3 F.
Please also refer to Fig. 3 G and Fig. 4 B, Fig. 4 B is the schematic top plan view of Fig. 3 G.Because sacrifice layer 304 is identical with the material of dielectric layer 314, the sacrifice layer 304 and dielectric layer 314 that exposes arranged so can use suitable etching solution to divest side simultaneously.When divesting side the sacrifice layer that exposes 304 and dielectric layer 314 arranged, be positioned at sacrifice layer 304 each material layer on dielectric layer 314 and also and then divested, and obtain structure as Fig. 3 G, finish the technology of tft array substrate.
Above-mentioned protective seam 324 is being protected the amorphous silicon layer 316 and electric capacity line zone 310b dielectric layer 314 as the capacitance dielectric layer of reservior capacitor of TFT zone 308a as channel region, allows it not be subjected to the erosion of etching solution.
Embodiment two still utilizes the first road semi-modulation type photomask to form sweep trace irrigation canals and ditches and electric capacity duct canal earlier in transparency electrode and substrate at this, and the relational pattern of the first metal layer is defined earlier.Wherein, allow sweep trace irrigation canals and ditches and electric capacity duct canal close terminal area end the degree of depth decrescence, allow the weld pad part position of terminal area on substrate, in order to carrying out follow-up routing technology.Then, utilize the etching of stepping back of sacrifice layer, step down in the TFT zone, second metal level and the position in sweep trace zone and electric capacity line zone can overlap with transparency conducting layer respectively at the first metal layer of terminal area.Utilize the second road semi-modulation type photomask again, the top electrode of pixel electrode, source/drain, reservior capacitor and the pattern of data line are defined out one by one.Therefore, the technology of whole LCD tft array substrate only needs the twice photomask to finish.
Embodiment three
Fig. 5 A-5E is the manufacturing process cross-sectional view according to a kind of LCD tft array substrate of the embodiment of the invention, and Fig. 6 A-6B is the schematic top plan view of LCD tft array substrate in the different fabrication phases.
Please be simultaneously with reference to Fig. 5 A and Fig. 6 A, Fig. 6 A is the schematic top plan view of Fig. 5 A.On substrate 500, form the transparency conducting layer 502 and first photoresist layer 504 in regular turn, use the first road photomask to carry out lithography technology then, on substrate 500, form sweep trace irrigation canals and ditches 506 and electric capacity duct canal 508 simultaneously.The substrate 500 of part still is covered with by the transparency conducting layer 502 and first photoresist layer 504 in regular turn beyond sweep trace irrigation canals and ditches 506 and the electric capacity duct canal 508.
Sweep trace irrigation canals and ditches 506 can be divided into three zones in Fig. 5 A, and it is respectively TFT zone 506a (the section AA ' of Fig. 5 A), sweep trace zone 506b and terminal area 506c.508 in electric capacity duct canal only is divided into two zones, and it is respectively electric capacity line zone 508b (the section BB ' of Fig. 5 A) and terminal area 508c (the section CC ' of Fig. 5 A).Above-mentioned terminal area 506c is the same with the structure of 508c, so it can not distinguished especially to the narration of terminal area 506c and 508c in the back.
Please be simultaneously with reference to 5B figure and Fig. 6 A, in the sweep trace irrigation canals and ditches 506 on substrate 500 and the electric capacity duct canal 508 and deposit the first metal layer 512, dielectric layer 514, amorphous silicon layer 516 and protective seam 524 in regular turn on first photoresist layer 504.Utilize existing appropriate solvent that first photoresist layer 504 is divested then; the first metal layer 512, dielectric layer 514, amorphous silicon layer 516 and the protective seam 524 that will be positioned at jointly on first photoresist layer 504 divest together, the first metal layer 512, dielectric layer 514, amorphous silicon layer 516 and protective seam 524 in only remaining sweep trace irrigation canals and ditches 506 and the electric capacity duct canal 508.The material of above-mentioned protective seam 524 for example can be dielectric material, as silicon nitride, monox or silicon oxynitride.
The first metal layer 512 in the 506a of the TFT of sweep trace irrigation canals and ditches 506 zone, dielectric layer 514 and amorphous silicon layer 516 are respectively in regular turn as grid, gate dielectric layer and the channel region of TFT.The first metal layer 512 in the 508b of the reservior capacitor of electric capacity duct canal 508 zone is as the electric capacity line of reservior capacitor, holds concurrently as the usefulness of the bottom electrode of reservior capacitor.
In Fig. 5 C, coating second photoresist layer 522 on substrate 500, be that the second road photomask comes second photoresist layer 522 is carried out lithography process one time for example then,, form the profile of second photoresist layer 522 shown in Fig. 5 C with patterning second photoresist layer 522 with semi-modulation type photomask.
Between TFT zone 506a and adjacent pixel region, second photoresist layer 522 of terminal area 508c is for exposing fully, so without any second photoresist layer 522.Take second place in the regions and source of TFT zone 506a and in the top electrode zone of electric capacity line zone 508b and the exposure of second photoresist layer 522 on the data line zone, therefore leave second photoresist layer 522 of very thin one deck.The exposure of second photoresist layer 522 on the overlap joint zone of the top electrode of the overlap joint zone of TFT zone 506a and pixel electrode and electric capacity line zone 508b and pixel electrode is taken second place again, so leaves the second thicker photoresist layer 522.And the second photoresist layer 522 not exposure fully on the peripheral region of interval region between passage area, capacitor top electrode zone and the data line zone of pixel region, TFT zone 506a (among the 508b of electric capacity line zone) and terminal area 508c, so kept the second complete photoresist layer 322.
In Fig. 5 D, down carry out etching with the anisotropic etching method.Because second photoresist layer 522 is in the variable thickness of zones of different, so the etch depth of zones of different is also different.
In the part of the section AA ' of Fig. 5 D, the TFT zone 506a that has second photoresist layer 522 of segment thickness to cover, its down etching till exposing amorphous silicon layer 516.Do not cover the zone of second photoresist layer 522 around the 506a of TFT zone, transparency conducting layer 502 all is removed with the substrate 500 of partial depth, so that transparency conducting layer 502 is defined pixel electrode 502a.And, then expose transparency conducting layer 502, as the overlap joint zone of TFT zone 506a and pixel electrode in the zone that TFT zone 506a is coated with second photoresist layer 522 of segment thickness on every side.
In the part of the section BB ' of Fig. 5 D, at the electric capacity line zone of second photoresist layer 522 that segment thickness is arranged 508b, its down etching till exposing amorphous silicon layer 516.Around the 508b of electric capacity line zone, be coated with the zone of second photoresist layer 522 of segment thickness, then expose transparency conducting layer 502, as the top electrode of electric capacity line zone 508b and the overlap joint zone of pixel electrode.
In the part of the section CC ' of Fig. 5 D, the terminal area 508c that exposes, the first metal layer each layer more than 512 all is removed.
On the substrate 500 that exposes, amorphous silicon layer 516, transparency conducting layer 502 and second photoresist layer 522, form the doped amorphous silicon layer 518 and second metal level 520 then in regular turn.
Please be simultaneously with reference to Fig. 5 E and Fig. 6 B, Fig. 6 B is the schematic top plan view of Fig. 5 E.To wait side that comes lateral erosion transparent electrode layer 502 to expose to etching method, the outline of transparent electrode layer 502 is retreated earlier, define pixel electrode 502a, in order to avoid should disconnect the problem that part is short-circuited between the transparent electrode layer 502 and second metal level 520.Then divest second photoresist layer 522, jointly the doped amorphous silicon layer 518 on second photoresist layer 522 is divested with second metal level 520, finish the technology of whole tft array substrate.
After finishing, second metal level 520 that stays forms source/drain 520a in the both sides of the protective seam 524 of TFT zone 506a, and 518 of the doped amorphous silicon layers that stays form ohmic contact layer 518a.Second metal level 520 in that electric capacity line zone 508b stays then becomes data line 520b and top electrode 520c respectively.Second metal level 520 that stays at terminal area 508c then becomes weld pad 520d.
In embodiment three, primary lithography technology is identical with embodiment one, all be to utilize the first road photomask to form sweep trace irrigation canals and ditches and electric capacity duct canal earlier in transparency electrode and substrate, preliminary definition goes out the TFT zone relevant with sweep trace and terminal area and reservior capacitor zone and the terminal area relevant with the electric capacity line.Deposit required different material layer in regular turn at sweep trace irrigation canals and ditches and electric capacity duct canal then, but make the doped amorphous silicon layer of embodiment one into protective seam.Utilize the second road photomask to carry out the lithography technology second time then, the protective seam in the zones such as weld pad of top electrode, data line and the terminal area of the source/drain of TFT, reservior capacitor is removed.Just the dopant deposition amorphous silicon layer and second metal level define out with required TFT structure, capacitor top electrode structure and data line structure on above-mentioned zone one by one in regular turn then.Therefore, the technology of whole LCD tft array substrate only needs the twice photomask to finish.
By the invention described above embodiment as can be known, use the disclosed LCD (Liquid Crystal Display) array substrate manufacture method of the present invention, utilize and divest method, as long as the twice photomask can be finished the technology of whole tft array substrate as semi-modulation type photomask and photoresist layer.Therefore be very helpful for the reduction of manufacturing cost and the lifting of production capacity.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.
Claims (9)
1. the manufacture method of the thin-film transistor array base-plate of a LCD is characterized in that, the manufacture method of this thin-film transistor array base-plate comprises:
Form a transparency conducting layer on a substrate;
This transparency conducting layer of patterning and this substrate, in this substrate, to form parallel staggered at least one sweep trace irrigation canals and ditches and at least one electric capacity duct canal, these at least one sweep trace irrigation canals and ditches have at least one TFT zone, one scan line zone and at least one the first terminal zone, and this at least one electric capacity duct canal has at least one electric capacity line zone and at least one second terminal area;
Form a first metal layer, a dielectric layer, an amorphous silicon layer and a doped amorphous silicon layer in regular turn respectively among these at least one sweep trace irrigation canals and ditches and this at least one electric capacity duct canal;
Form one second metal level on this doped amorphous silicon layer and this transparency conducting layer; And
With the lithography method of single exposure, define a TFT structure simultaneously in this TFT zone, a storage capacitors and a data line are in this electric capacity line zone, and the two-terminal structure is respectively in this first and second terminal area.
2. the manufacture method of the thin-film transistor array base-plate of a LCD is characterized in that, the manufacture method of this thin-film transistor array base-plate comprises:
Form a transparency conducting layer on a substrate;
Form a sacrifice layer on this transparency conducting layer;
This sacrifice layer of patterning, this transparency conducting layer and this substrate, in this substrate, to form parallel staggered at least one sweep trace irrigation canals and ditches and at least one electric capacity duct canal, these at least one sweep trace irrigation canals and ditches have at least one TFT zone, one scan line zone and at least one the first terminal zone, this at least one electric capacity duct canal has at least one electric capacity line zone and at least one second terminal area, and this first terminal zone is decremented to zero with the irrigation canals and ditches degree of depth of this second terminal area in this substrate toward end direction;
Form a first metal layer, a dielectric layer, an amorphous silicon layer and a doped amorphous silicon layer in regular turn respectively among these at least one sweep trace irrigation canals and ditches and this at least one electric capacity duct canal and on this substrate around this first terminal zone and the terminal peripheral part of this second terminal area, this dielectric layer is identical with the material of this sacrifice layer;
The exposed sidewalls of this sacrifice layer of lateral erosion and this dielectric layer retreats the outline of this sacrifice layer and this dielectric layer;
Form one second metal level on this sacrifice layer that exposes, this transparency conducting layer and this doped amorphous silicon layer;
Use the lithography method of single exposure, define a TFT structure simultaneously in this TFT zone, a storage capacitors and a data line are in this electric capacity line zone, and the two-terminal structure is respectively in this first and second terminal area;
Form a protective seam on each layer that exposes;
Remove this single exposure the lithography method residual photoresist and go up each layer; And
Remove each layer on this sacrifice layer that sidewall exposes, this dielectric layer and aforementioned the two its.
3. the manufacture method of thin-film transistor array base-plate according to claim 2 is characterized in that, the material of this protective seam is silicon nitride, monox or silicon oxynitride.
4. the manufacture method of the thin-film transistor array base-plate of a LCD is characterized in that, the manufacture method of this thin-film transistor array base-plate comprises:
Form a transparency conducting layer on a substrate;
This transparency conducting layer of patterning and this substrate, in this substrate, to form parallel staggered at least one sweep trace irrigation canals and ditches and at least one electric capacity duct canal, these at least one sweep trace irrigation canals and ditches have at least one TFT zone, one scan line zone and at least one the first terminal zone, and this at least one electric capacity duct canal has at least one electric capacity line zone and at least one second terminal area;
Form a first metal layer, a dielectric layer, an amorphous silicon layer, a doped amorphous silicon layer and a protective seam in regular turn respectively among these at least one sweep trace irrigation canals and ditches and this at least one electric capacity duct canal;
Use the lithography method of single exposure, in this TFT zone, remove this protective seam and this doped amorphous silicon layer to form source electrode and drain region, in this electric capacity line zone, remove this protective seam and this doped amorphous silicon layer to form top electrode zone and data line zone, in this first and second terminal area, remove this protective seam, this doped amorphous silicon layer and this amorphous silicon layer;
Form a doped amorphous silicon layer and one second metal level in regular turn on this source electrode and drain region, this top electrode zone, this data line zone, this first and second terminal area and residual photoresist layer;
The exposed sidewalls of this transparency conducting layer of lateral erosion retreats the outline of this transparent electrode layer; And
Remove this remaining photoresist layer.
5. the manufacture method of thin-film transistor array base-plate according to claim 4 is characterized in that, the material of this protective seam is silicon nitride, monox or silicon oxynitride.
6. the thin-film transistor array base-plate of the LCD made of a method according to claim 1 is characterized in that this thin-film transistor array base-plate comprises:
One substrate, has a transparency conducting layer on it, utilize the first road photomask in this transparency conducting layer and this substrate, to form parallel staggered at least one sweep trace irrigation canals and ditches and at least one electric capacity duct canal, these at least one sweep trace irrigation canals and ditches have at least one TFT zone, one scan line zone and at least one the first terminal zone, and this at least one electric capacity duct canal has at least one electric capacity line zone and at least one second terminal area; Deposit a first metal layer, a dielectric layer, an amorphous silicon layer and a doped amorphous silicon layer respectively in regular turn among described at least one sweep trace irrigation canals and ditches and this at least one electric capacity duct canal;
One second metal level is formed on described doped amorphous silicon layer and this transparency conducting layer;
One thin film transistor (TFT) is arranged in this TFT zones of this sweep trace irrigation canals and ditches, and this thin film transistor (TFT) has a grid, and one source pole and drain electrode at least;
At least one sweep trace is arranged in this sweep trace zones of this sweep trace irrigation canals and ditches, and is electrically connected with the grid of this thin film transistor (TFT); One reservior capacitor is arranged in the electric capacity line zone of this electric capacity duct canal;
One data line is arranged in this electric capacity line zone, and crosses over these at least one sweep trace irrigation canals and ditches and this at least one electric capacity duct canal, and an electrode of the source electrode of this at least one data line and this thin film transistor (TFT) or drain electrode is electrically connected; And
At least one pixel electrode between this at least one data line and this at least one sweep trace on this substrate, and is electrically connected with the source electrode of this thin film transistor (TFT) or another electrode of drain electrode;
The two-terminal structure lays respectively in this first and second terminal area;
Wherein, the upper electrode arrangement of described thin film transistor (TFT), described reservior capacitor, described data line and described two-terminal structure are to define out by the second road photomask.
7. thin-film transistor array base-plate according to claim 6 is characterized in that, comprises that also a plurality of weld pads lay respectively in the stub area of these sweep trace irrigation canals and ditches and this electric capacity duct canal.
8. the thin-film transistor array base-plate of the LCD made of a method according to claim 2 is characterized in that this thin-film transistor array base-plate comprises:
One substrate, has a transparency conducting layer on it, utilize the first road photomask in this transparency conducting layer and this substrate, to form parallel staggered at least one sweep trace irrigation canals and ditches and at least one electric capacity duct canal, these at least one sweep trace irrigation canals and ditches have at least one TFT zone, one scan line zone and at least one the first terminal zone, this at least one electric capacity duct canal has at least one electric capacity line zone and at least one second terminal area, and this first terminal zone is decremented to zero with the irrigation canals and ditches degree of depth of this second terminal area in this substrate toward end direction; Deposit a first metal layer, a dielectric layer, an amorphous silicon layer and a doped amorphous silicon layer respectively in regular turn among described at least one sweep trace irrigation canals and ditches and this at least one electric capacity duct canal and on this substrate around this first terminal zone and the terminal peripheral part of this second terminal area;
One second metal level is formed on sacrifice layer, this transparency conducting layer and this doped amorphous silicon layer that exposes;
One thin film transistor (TFT) is arranged in this TFT zones of this sweep trace irrigation canals and ditches, and this thin film transistor (TFT) has a grid, and one source pole and drain electrode at least;
At least one sweep trace is arranged in this sweep trace zones of this sweep trace irrigation canals and ditches, and is electrically connected with the grid of this thin film transistor (TFT);
One reservior capacitor is arranged in the electric capacity line zone of this electric capacity duct canal;
One data line is arranged in this electric capacity line zone, and crosses over these at least one sweep trace irrigation canals and ditches and this at least one electric capacity duct canal, and an electrode of the source electrode of this at least one data line and this thin film transistor (TFT) or drain electrode is electrically connected; And
At least one pixel electrode between this at least one data line and this at least one sweep trace on this substrate, and is electrically connected with the source electrode of this thin film transistor (TFT) or another electrode of drain electrode;
The two-terminal structure lays respectively in this first and second terminal area;
Wherein, the upper electrode arrangement of described thin film transistor (TFT), described reservior capacitor, described data line and described two-terminal structure are to define out by the second road photomask.
9. the thin-film transistor array base-plate of the LCD made of a method according to claim 4 is characterized in that this thin-film transistor array base-plate comprises:
One substrate, has a transparency conducting layer on it, utilize the first road photomask in this transparency conducting layer and this substrate, to form parallel staggered at least one sweep trace irrigation canals and ditches and at least one electric capacity duct canal, these at least one sweep trace irrigation canals and ditches have at least one TFT zone, one scan line zone and at least one the first terminal zone, and this at least one electric capacity duct canal has at least one electric capacity line zone and at least one second terminal area; Deposit a first metal layer, a dielectric layer, an amorphous silicon layer and a doped amorphous silicon layer and a protective seam respectively in regular turn among described at least one sweep trace irrigation canals and ditches and this at least one electric capacity duct canal;
Have source electrode and drain region in this TFT zone, have top electrode zone and data line zone in this electric capacity line zone;
One doped amorphous silicon layer and one second metal level are formed at respectively on described source electrode and drain region, this top electrode zone, this data line zone, this first and second terminal area and the residual photoresist layer in regular turn;
One thin film transistor (TFT) is arranged in this TFT zones of this sweep trace irrigation canals and ditches, and this thin film transistor (TFT) has a grid, and one source pole and drain electrode at least;
At least one sweep trace is arranged in this sweep trace zones of this sweep trace irrigation canals and ditches, and is electrically connected with the grid of this thin film transistor (TFT);
One reservior capacitor is arranged in the electric capacity line zone of this electric capacity duct canal;
One data line is arranged in this electric capacity line zone, and crosses over these at least one sweep trace irrigation canals and ditches and this at least one electric capacity duct canal, and an electrode of the source electrode of this at least one data line and this thin film transistor (TFT) or drain electrode is electrically connected; And
At least one pixel electrode between this at least one data line and this at least one sweep trace on this substrate, and is electrically connected with the source electrode of this thin film transistor (TFT) or another electrode of drain electrode;
The two-terminal structure lays respectively in this first and second terminal area;
Wherein, the upper electrode arrangement of described thin film transistor (TFT), described reservior capacitor, described data line and described two-terminal structure are to define out by the second road photomask.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2007101820667A CN101187765B (en) | 2006-11-21 | 2007-10-24 | Film transistor array substrate for liquid crystal display and manufacture thereof |
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| CN200610145797.X | 2006-11-21 | ||
| CN 200610145797 CN1963651A (en) | 2006-11-21 | 2006-11-21 | Array base plate of thin film transistor of LCD and manufacturing method of the same |
| CN2007101820667A CN101187765B (en) | 2006-11-21 | 2007-10-24 | Film transistor array substrate for liquid crystal display and manufacture thereof |
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| CN101187765A CN101187765A (en) | 2008-05-28 |
| CN101187765B true CN101187765B (en) | 2010-07-21 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1040381C (en) * | 1994-12-26 | 1998-10-21 | 现代电子产业株式会社 | Double-channel thin-film transistor and making method thereof |
| CN1258357A (en) * | 1998-03-19 | 2000-06-28 | 精工爱普生株式会社 | Liquid crystal display device and projection display device |
| CN1610110A (en) * | 2003-10-14 | 2005-04-27 | Lg.菲利浦Lcd株式会社 | Thin film transistor substrate for display device and fabricating method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1040381C (en) * | 1994-12-26 | 1998-10-21 | 现代电子产业株式会社 | Double-channel thin-film transistor and making method thereof |
| CN1258357A (en) * | 1998-03-19 | 2000-06-28 | 精工爱普生株式会社 | Liquid crystal display device and projection display device |
| CN1610110A (en) * | 2003-10-14 | 2005-04-27 | Lg.菲利浦Lcd株式会社 | Thin film transistor substrate for display device and fabricating method thereof |
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