CN101183328A - Computer universal serial bus interface device time-limited timing controller - Google Patents
Computer universal serial bus interface device time-limited timing controller Download PDFInfo
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- CN101183328A CN101183328A CNA2007101908288A CN200710190828A CN101183328A CN 101183328 A CN101183328 A CN 101183328A CN A2007101908288 A CNA2007101908288 A CN A2007101908288A CN 200710190828 A CN200710190828 A CN 200710190828A CN 101183328 A CN101183328 A CN 101183328A
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Abstract
The invention relates to a limited interval and timing controller for computer USB interface equipment; wherein the low four bits of one four-bit input port P2 of a single-chip microcomputer minimum system (1) are connected with the address outputs A2, A1, A0 and a keyswitch of an encoder in a peripheral control circuit (2). An eight-bit output port P0 and the high four bits of a four-bit output port P2 are respectively connected with eight segment numbers of the digitron eight codes and the four-bit bit selection ends of the digitron of the time display circuit (3). The low six bits of a six-bit output port P1 are connected with a buzzer, a relay, a digitron and an indicator of a peripheral response circuit (4). The peripheral control circuit is connected with the time display circuit through the digitron to display the control state. The invention has the advantage of realizing limited interval and timing operation by software method for the system.
Description
Technical field
The present invention relates to a kind of computer USB (Universal Serial Bus, USB (universal serial bus)) design of the time-limited timing controller of interfacing equipment and device for carrying out said, especially to control service time of computer USB peripheral hardware, the design of use clocking capability, be applicable to that USB device is used, the operating process of use timing in limited time.
Background technology
At present, along with development of science and technology, high-tech finished products such as computer are increasing, its needed peripheral expansion equipment is also more and more simultaneously, the USB peripheral hardware has obtained users' favor as a kind of peripheral interface equipment easily and efficiently, but nearly all computer does not possess the control of timing in limited time to its peripherals, and particularly in the epoch that computer game is spread unchecked, how controlling playtime becomes the head of a family and teacher's urgent problem.The control of running time present stage simultaneously all realizes operation by computer software, these operations have very strong dependence to the ruuning situation of computer, and can only operate the current computer system of moving, and can not some specific USB device be controlled, use to the user and bring inconvenience.
Except utilizing software to carry out, reach purpose to single USB device in limited time, timing control thereby can also control some specific USB device with hardware circuit to the timing of the computer control.So not only solved traditional insurmountable problem of software of using, realized simultaneously USB control new method.
On the one hand, make a certain specific peripheral hardware time-limited operation of computer to finish on time and do not influence the normal operation of other soft, hardware that this has solved the problem of the countless heads of a family and teacher's worry.
On the other hand, to some when needing the timing operating process, for example: timing match, test operation deadline or the like, the time that can read use equipment easily, exactly, finish a certain operating process.
Summary of the invention
Technical matters: the purpose of this invention is to provide a kind of computer universal serial bus interface device time-limited timing controller, can carry out control operation to a certain specific USB device to reach, other of computer are soft, the purpose of the normal operation of hardware and do not influence, and can also come accurate timing as timer, not as controller the time, can be used as the multifunction electronic clock and use.
Technical scheme: tradition is to the timing time-limited operation of USB device, be used computer system to be carried out fixed cycle operator by timing software, setting-up time is then closed computer, thereby reach the purpose that the restriction USB device is used, but this operation has very strong dependence to computer system, influences other normal use soft, hardware in the system simultaneously.And the designed hardware type USB device time-limited timing controller of the utility model has just solved this problem,
This device utilizes computer USB interface to provide controller required power supply, with the 89S52 single-chip microcomputer is that core is in conjunction with imput output circuit and display circuit, provide the three paths of independent timer in the processor part by 89S52, input equipment is input to single-chip microcomputer by toggle switch by scrambler, control USB device by routine processes response control corresponding, on display, show synchronously simultaneously.Like this can be simply, accurately and real-time specific USB device is operated, reach in limited time, the purpose of timing control.
Computer universal serial bus interface device time-limited timing controller involved in the present invention comprises single-chip minimum system (1), peripheral control circuit (2), time display circuit (3), peripheral response circuit (4); Wherein, low four of one of single-chip minimum system (1) group of four input port P2 mouth link to each other with scrambler address output end A2, A1, A0 and keyswitch in the peripheral control circuit; The one group octet output port P0 mouth of single-chip minimum system (1) and the Gao Siwei of one group four output port P2 mouths connect eight sections of charactron of time display circuit (3) and the selecting side, four positions of charactron respectively; Low six of one group six output port P1 mouths of single-chip minimum system (1) are connected with hummer, relay, charactron, the pilot lamp of peripheral response circuit; Peripheral control circuit (4) and time display circuit (3) are by the charactron display control state that links to each other.
Described peripheral control circuit (2) is selection and the switching of the time-division of the time of adjustment that is realized operational mode by eight toggle switchs, and other establishes a keyswitch as the input of adjusting that adds; Eight code switchs connect eight pull-up resistors of a slice, then the tri-bit encoding address is input to three bit data input port P2.0-P2.2 of single-chip minimum system (1) by model for the encoder encodes of " 74LS148 ", keyswitch is connected to (1) data input port P2.3 of single-chip minimum system.
Described time display circuit is to be realized by the charactron of four bit strip point second demonstrations, connect with altogether positive connection, the common oedoeagus A1 of group of four figures pipe wherein, A2, A3, A4 links the four figures of single-chip minimum system (1) according to output terminal P2.4 by triode respectively, P2.5, P2.6, the P2.7 mouth, eight sections of charactron show a, b, c, d, e, f, g, dp is connected respectively to a group octet data output P0.0 of single-chip minimum system (1), P0.1, P0.2, P0.3, P0.4, P0.5, P0.6, the P0.7 mouth, thus the static state that realizes group of four figures pipe shows.Described peripheral response circuit is to be controlled by pattern demonstration, buzzing response and a switch to constitute; Pattern shows that charactron is connected to single-chip minimum system by model for " 74LS164 " charactron chip for driving, wherein the charactron chip for driving /CLR, CLK, A and B end be connected respectively to three bit data delivery outlet P1.2, P1.3, the P1.4 mouth of single-chip minimum system, hummer, relay and pilot lamp are connected to three bit data output terminal P1.0, P1.1, the P1.5 mouth of single-chip minimum system respectively by amplifying circuit, control peripheral response circuit (4) by single-chip minimum system (1) from the output terminal output data.
Described power supply VCC is provided by the builtin voltage of required control USB interface, also add the external power source mode simultaneously, comprise dry cell power supply and mains-supplied mode, single-chip minimum system (1) power supply VCC partly comprises step-down, mu balanced circuit, and dry cell and external power source are connected to the VCC end of single-chip minimum system (1).
Beneficial effect: this design and device for carrying out said have realized controlling with hardware the function of a certain specific USB peripheral hardware, influences other problem soft, the normal use of hardware of system when having solved with software timing control effectively.Because this design be by hardware circuit come to the USB peripheral hardware of needs control prescribe a time limit, timing control, on this device for carrying out said, set the time that this equipment will use, thereby the timer of this device inside moves this USB device is carried out single control then.When the default time then, the use of this USB device of this device end, but do not influence other uncontrolled USB device and other use soft, hardware of computer.The problem that software is prescribed a time limit so this device for carrying out said has solved, timing control only can be controlled whole computer system.
This design circuit is simple, can control the use of USB device convenient, fast, exactly, also has multinomial clocking capability simultaneously, and is easy to use.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention's design is further specified.
Fig. 1 is a hardware system framework synoptic diagram of the present invention.
Have among the figure: single-chip minimum system (1), peripheral control circuit (2), time display circuit (3), peripheral response circuit (4).
Embodiment
At first, the design be with the 89S52 single-chip microcomputer be core mainly by hardware circuit constitute in limited time, timing controller, overcome tradition realized in limited time, can only control during the timing operation total system with software defective.
This device for carrying out said mainly adds that by single-chip minimum system 1 (as shown in Figure 2) peripheral control circuit 2 (as shown in Figure 3), time display circuit 3 (as shown in Figure 4) and peripheral response circuit 4 (as shown in Figure 5) form.
Computer universal serial bus interface device time-limited timing controller of the present invention comprises single-chip minimum system 1, peripheral control circuit 2, time display circuit 3, peripheral response circuit 4; Wherein, low four of one of single-chip minimum system 1 group four input port P2 mouths link to each other with scrambler address output end A2, A1, A0 and keyswitch in the peripheral control circuit 2; The one group octet output port P0 mouth of single-chip minimum system 1 and the Gao Siwei of one group four output port P2 mouths connect eight sections of charactron of time display circuit 3 and the selecting side, four positions of charactron respectively; Low six of one group six output port P1 mouths of single-chip minimum system 1 are connected with hummer, relay, charactron, the pilot lamp of peripheral response circuit 4; Peripheral control circuit 2 and time display circuit 3 are by the charactron display control state that links to each other.
Described peripheral control circuit 2 is selection and the switchings of the time-division of the time of adjustment that realized operational mode by eight toggle switchs, and other establishes a keyswitch as the input of adjusting that adds; Eight code switchs connect eight pull-up resistors of a slice, then the tri-bit encoding address is input to three bit data input port P2.0-P2.2 of single-chip minimum system 1 by model for the encoder encodes of " 74LS148 ", keyswitch is connected to 1 one data input ports of single-chip minimum system P2.3.Described time display circuit 3 is to be realized by the charactron of four bit strip point second demonstrations, connect with altogether positive connection, wherein the common oedoeagus A1 of group of four figures pipe, A2, A3, A4 link the four figures of single-chip minimum system 1 according to output terminal P2.4, P2.5, P2.6, P2.7 mouth by triode respectively, eight sections of charactron show that a, b, c, d, e, f, g, dp are connected respectively to a group octet data output P0.0, P0.1, P0.2, P0.3, P0.4, P0.5, P0.6, the P0.7 mouth of single-chip minimum system 1, thereby the static state that realizes group of four figures pipe shows.Described peripheral response circuit 4 is to be controlled by pattern demonstration, buzzing response and a switch to constitute; Pattern shows that charactron is connected to single-chip minimum system 1 by model for " 74LS164 " charactron chip for driving, wherein the charactron chip for driving /CLR, CLK, A and B end be connected respectively to three bit data delivery outlet P1.2, P1.3, the P1.4 mouth of single-chip minimum system 1, hummer, relay and pilot lamp are connected to three bit data output terminal P1.0, P1.1, the P1.5 mouth of single-chip minimum system 1 respectively by amplifying circuit, control peripheral response circuit 4 by single-chip minimum system 1 from the output terminal output data.Described power supply VCC is provided by the builtin voltage of required control USB interface, also add the external power source mode simultaneously, comprise dry cell power supply and mains-supplied mode, single-chip minimum system 1 power supply VCC partly comprises step-down, mu balanced circuit, and dry cell and external power source are connected to the VCC end of single-chip minimum system 1.
When using this device for carrying out said, by online programming program is write the 89S52 single-chip microcomputer earlier and wait for next step order.
When moving the timing function of this device for carrying out said, by regulating the service time that peripheral control circuit 2 limits certain specific USB device, time set is in time display circuit 3 instant playbacks.After the time configures, open the run switch timing function that brings into operation, when distance finishes also to remain three minutes (time can be set arbitrarily by program according to specific requirement), send and use the prompting that closes to an end, when setting-up time arrives, USB device communication disconnects, and it is bright to forbid pilot lamp simultaneously.
When moving the clocking capability of this device for carrying out said, by the operational mode that peripheral control circuit 2 is opened this state, time display circuit 3 meeting time synchronisations are when end of run, the timing of time display circuit 3 finishes, and the shown time is the working time of USB device.
When moving the time clock feature of this design apparatus, set the current time by peripheral control circuit 2, promptly bring into operation in the time of setting, the clock run indicator can be glimmered synchronously with second simultaneously.
The device for carrying out said of this design is in each difference in functionality operation, and the charactron of peripheral response circuit 4 also can show the status number that is moved.
Claims (5)
1. a computer universal serial bus interface device time-limited timing controller is characterized in that this controller comprises single-chip minimum system (1), peripheral control circuit (2), time display circuit (3), peripheral response circuit (4); Wherein, low four of one of single-chip minimum system (1) group of four input port P2 mouth link to each other with scrambler address output end A2, A1, A0 and keyswitch in the peripheral control circuit (2); The one group octet output port P0 mouth of single-chip minimum system (1) and the Gao Siwei of one group four output port P2 mouths connect eight sections of charactron of time display circuit (3) and the selecting side, four positions of charactron respectively; Low six of one group six output port P1 mouths of single-chip minimum system (1) are connected with hummer, relay, charactron, the pilot lamp of peripheral response circuit (4); Peripheral control circuit (2) and time display circuit (3) are by the charactron display control state that links to each other.
2. computer universal serial bus interface device time-limited timing controller as claimed in claim 1, it is characterized in that described peripheral control circuit (2) is selection and the switching of the time-division of the time of adjustment that is realized operational mode by eight toggle switchs, other establishes a keyswitch as the input of adjusting that adds; Eight code switchs connect eight pull-up resistors of a slice, then the tri-bit encoding address is input to three bit data input port P2.0-P2.2 of single-chip minimum system (1) by model for the encoder encodes of " 74LS148 ", keyswitch is connected to (1) data input port P2.3 of single-chip minimum system.
3. computer universal serial bus interface device time-limited timing controller as claimed in claim 1, it is characterized in that described time display circuit (3) is to be realized by the charactron of four bit strip point second demonstrations, connect with altogether positive connection, the common oedoeagus A1 of group of four figures pipe wherein, A2, A3, A4 links the four figures of single-chip minimum system (1) according to output terminal P2.4 by triode respectively, P2.5, P2.6, the P2.7 mouth, eight sections of charactron show a, b, c, d, e, f, g, dp is connected respectively to a group octet data output P0.0 of single-chip minimum system (1), P0.1, P0.2, P0.3, P0.4, P0.5, P0.6, the P0.7 mouth, thus the static state that realizes group of four figures pipe shows.
4. computer universal serial bus interface device time-limited timing controller as claimed in claim 1 is characterized in that described peripheral response circuit (4) is to be controlled by pattern demonstration, buzzing response and a switch to constitute; Pattern shows that charactron is connected to single-chip minimum system (1) by model for " 74LS164 " charactron chip for driving, wherein the charactron chip for driving /CLR, CLK, A and B end be connected respectively to three bit data delivery outlet P1.2, P1.3, the P1.4 mouth of single-chip minimum system (1), hummer, relay and pilot lamp are connected to three bit data output terminal P1.0, P1.1, the P1.5 mouth of single-chip minimum system (1) respectively by amplifying circuit, control peripheral response circuit (4) by single-chip minimum system (1) from the output terminal output data.
5. computer universal serial bus interface device time-limited timing controller as claimed in claim 1, it is characterized in that described power supply VCC is provided by the builtin voltage of required control USB interface, also add the external power source mode simultaneously, comprise dry cell power supply and mains-supplied mode, single-chip minimum system (1) power supply VCC partly comprises step-down, mu balanced circuit, and dry cell and external power source are connected to the VCC end of single-chip minimum system (1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007101908288A CN100547561C (en) | 2007-11-30 | 2007-11-30 | Computer universal serial bus interface device time-limited timing controller |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2007101908288A CN100547561C (en) | 2007-11-30 | 2007-11-30 | Computer universal serial bus interface device time-limited timing controller |
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| CN101183328A true CN101183328A (en) | 2008-05-21 |
| CN100547561C CN100547561C (en) | 2009-10-07 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2007101908288A Expired - Fee Related CN100547561C (en) | 2007-11-30 | 2007-11-30 | Computer universal serial bus interface device time-limited timing controller |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102253702A (en) * | 2010-05-21 | 2011-11-23 | 鸿富锦精密工业（深圳）有限公司 | Power supply control device |
| CN104700870A (en) * | 2013-12-06 | 2015-06-10 | 鸿富锦精密电子(天津)有限公司 | Hard disk drive with time indication function |
| CN104731685A (en) * | 2013-12-18 | 2015-06-24 | 鸿富锦精密电子(天津)有限公司 | Computer system with hard disk time state indication function |
-
2007
- 2007-11-30 CN CNB2007101908288A patent/CN100547561C/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102253702A (en) * | 2010-05-21 | 2011-11-23 | 鸿富锦精密工业（深圳）有限公司 | Power supply control device |
| CN104700870A (en) * | 2013-12-06 | 2015-06-10 | 鸿富锦精密电子(天津)有限公司 | Hard disk drive with time indication function |
| CN104700870B (en) * | 2013-12-06 | 2017-06-06 | 赛恩倍吉科技顾问（深圳）有限公司 | The hard disk of function is indicated with use time |
| CN104731685A (en) * | 2013-12-18 | 2015-06-24 | 鸿富锦精密电子(天津)有限公司 | Computer system with hard disk time state indication function |
| CN104731685B (en) * | 2013-12-18 | 2019-03-26 | 深圳迈辽技术转移中心有限公司 | Computer system with hard disk time state instruction function |
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| Publication number | Publication date |
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| CN100547561C (en) | 2009-10-07 |
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Granted publication date: 20091007 Termination date: 20121130 |