CN101183213A - Photo mask and manufacturing method of thin-film transistor substrates - Google Patents
Photo mask and manufacturing method of thin-film transistor substrates Download PDFInfo
- Publication number
- CN101183213A CN101183213A CNA2007103018435A CN200710301843A CN101183213A CN 101183213 A CN101183213 A CN 101183213A CN A2007103018435 A CNA2007103018435 A CN A2007103018435A CN 200710301843 A CN200710301843 A CN 200710301843A CN 101183213 A CN101183213 A CN 101183213A
- Authority
- CN
- China
- Prior art keywords
- pattern
- pixels
- exposure region
- overlaps
- photomask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Preparing Plates And Mask In Photomechanical Process (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
The present invention discloses a producing method for a photomask and a thin-film transistor basal plate. The photomask is used to produce the thin-film transistor basal plate and is provided with a first exposure area, a second exposure area and a third exposure area. The second exposure area is placed between the first exposure area and the third exposure area. The photomask comprises a first perimeter circuit pattern, a first virtual lead pattern, a first overlap pixel pattern and the second virtual pixel pattern. The first perimeter circuit pattern is placed at the first exposure area. The first virtual pixel pattern is placed at the first exposure area and is neighbored with the first perimeter circuit pattern; the first overlap pixel pattern is placed at the first exposure area and is neighbored with the first virtual lead pattern. The second overlap pixel pattern is placed at the second exposure area; the first overlap pixel pattern is complemented with the second overlap pixel pattern; wherein, the first overlap pixel pattern is the interfacing of the patterns formed by the first exposure area and the second exposure area after the first overlap pixel pattern and the second overlap pixel pattern are overlapped and exposed.
Description
Technical field
The present invention relates to a kind of photomask and manufacturing method of film transistor base plate, and be particularly related to a kind of photomask and large scale manufacturing method of film transistor base plate that is applicable to the large scale thin film transistor base plate.
Background technology
Along with display panels develops towards large scale, it is difficult that the manufacturing course of thin film transistor base plate also becomes.Generally speaking, thin film transistor base plate is usually so that repeatedly little shadow and etch process are finished.Action by multiple tracks exposure is passed to photoresist layer on the substrate with the pattern on the photomask, to form the patterning photoresist layer.Then, again the patterning photoresist layer is carried out etching for shielding to the film on the substrate, to form the pattern of various elements.
Yet under the trend that the size of thin film transistor base plate increases, the size of photomask also must increase thereupon.Large-sized photomask is difficult for making and its manufacturing cost is grown up along with size becomes multiple, quite is not inconsistent business efficiency.Therefore, how to research and develop a kind of photomask and manufacturing method of film transistor base plate, to meet the arts demand of large scale thin film transistor base plate, real is an important directions of researching and developing at present.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of photomask and manufacturing method of film transistor base plate, and the design that it utilizes the dummy leads pattern and overlaps pattern of pixels is to meet the arts demand of large scale thin film transistor base plate.
For achieving the above object, the present invention proposes a kind of photomask.Photomask is in order to make a thin film transistor base plate.Photomask has one first exposure region, one second exposure region and one the 3rd exposure region.Second exposure region be positioned at first exposure region and the 3rd exposure region between.Photomask comprises that one first perimeter circuit pattern, one first dummy leads pattern, one first overlap pattern of pixels and one second and overlap pattern of pixels.The first perimeter circuit pattern is positioned at first exposure region.The first dummy leads pattern is positioned at first exposure region, and is adjacent to the first perimeter circuit pattern.First overlaps pattern of pixels is positioned at first exposure region, and is adjacent to the first dummy leads pattern.Second overlaps pattern of pixels is positioned at second exposure region, and first overlaps pattern of pixels overlaps the pattern of pixels complementation with second.Wherein first overlap pattern of pixels and after second overlapped the pattern of pixels double exposure, the pattern that first exposure region and second exposure region are exposed was bonded with each other.
And for achieving the above object, the present invention proposes a kind of manufacturing method of film transistor base plate.Manufacturing method of film transistor base plate may further comprise the steps: a substrate is provided.One photomask is provided, and photomask has one first exposure region, one second exposure region and one the 3rd exposure region.Second exposure region is between first exposure region and the 3rd exposure region.Photomask comprises that one first perimeter circuit pattern, one first dummy leads pattern, one first overlap pattern of pixels and one second and overlap pattern of pixels.The first perimeter circuit pattern is positioned at first exposure region, and the first dummy leads pattern is positioned at first exposure region, and is adjacent to the first perimeter circuit pattern.First overlaps pattern of pixels is positioned at first exposure region, and is adjacent to the first dummy leads pattern.First overlaps pattern of pixels overlaps the pattern of pixels complementation with second.Form a photoresist layer on substrate.Overlap the pattern of pixels exposed photoresist layer with the first perimeter circuit pattern, the first dummy leads pattern and first.Overlap the pattern of pixels exposed photoresist layer with second.Wherein second overlap the position of pattern of pixels double exposure in the first coincidence pattern of pixels.The patterning photoresist layer.With the photoresist layer is the shielding etching substrates, to form several perimeter circuit patterns and several pattern of pixels.
Adopt disclosed photomask of the above embodiment of the present invention and manufacturing method of film transistor base plate to utilize the design of dummy leads pattern and coincidence pattern of pixels, make photomask after repeated exposure repeatedly, the pattern that is exposed can be bonded into the thin film transistor base plate of specific dimensions.
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Description of drawings
Fig. 1 illustrates the synoptic diagram of photomask first embodiment of the present invention;
Fig. 2 illustrates the synoptic diagram of the thin film transistor base plate made from the photomask of Fig. 1;
Fig. 3 A～Fig. 3 B illustrates the manufacture method process flow diagram of thin film transistor base plate first embodiment of the present invention;
Fig. 4 A～Fig. 4 H illustrates each step synoptic diagram of Fig. 3; And
Fig. 5 illustrates the synoptic diagram of photomask second embodiment of the present invention.
Wherein, Reference numeral:
110,210: photomask 111: shadow shield
130,230: thin film transistor base plate 131: substrate
132: photoresist layer A11, A21: first exposure region
A12, A22: the second exposure region A13, A23: the 3rd exposure region
CS: common electrode circuit D11, D21: the first dummy leads pattern
D12, D22: the second dummy leads pattern G: grid circuit
L: boundary line L11, L21: the first perimeter circuit pattern
L12, L22: the second perimeter circuit pattern P 10, P20: center pixel line pattern
P11, P21: the first pixel circuit pattern P 12, P22: the second pixel line pattern
P13, P23: the 3rd pixel circuit pattern P 14, P24: the 4th pixel line pattern
P15, P25: the 5th pixel circuit pattern P 16, P26: the 6th pixel line pattern
S: source line WD11: the width of the first dummy leads pattern
WD12: the width of the second dummy leads pattern
Embodiment
First embodiment
Please refer to Fig. 1 and Fig. 2, Fig. 1 illustrates the synoptic diagram of photomask first embodiment of the present invention, and Fig. 2 illustrates the synoptic diagram of the thin film transistor base plate made from the photomask of Fig. 1.Photomask 110 is in order to make a thin film transistor base plate 130.Photomask 110 has one first exposure region A11, one second exposure region A12 and one the 3rd exposure region A13.The second exposure region A12 is between the first exposure region A11 and the 3rd exposure region A13.Photomask 110 comprises that one first perimeter circuit pattern L11, one second perimeter circuit pattern L12, one first dummy leads pattern D11, one second dummy leads pattern D12, one first coincidence pattern of pixels P11, one second coincidence pattern of pixels P12, one the 3rd coincidence pattern of pixels P13, a quadruple are closed pattern of pixels P14, the 5th coincidence pattern of pixels P15, sixfold closes a pattern of pixels P16 and a center pixel pattern P 10.
The first perimeter circuit pattern L11 and the second perimeter circuit pattern L12 are corresponding to the perimeter circuit of thin film transistor base plate 130, for example be grid circuit G (claim not only trace wiring-scan line), common electrode circuit CS or source line (but also claim data circuit-data line, do not illustrate).Generally speaking, grid circuit G and common electrode circuit CS are positioned at the relative dual-side of thin film transistor base plate 130, and source line then is positioned at the in addition relative dual-side of thin film transistor base plate 130.In the present embodiment, the first perimeter circuit pattern L11 is that example explains with the pattern of the grid circuit G that is positioned at a side and the pattern of common electrode circuit CS, and wherein the first perimeter circuit pattern L11 is positioned at the first exposure region A11 of photomask 110.The second perimeter circuit L12 is that example explains with the pattern of the grid circuit G that is positioned at another side and the pattern of common electrode circuit CS then, and wherein the second perimeter circuit pattern L12 is positioned at the 3rd exposure region A13 of photomask 110.
The first dummy leads pattern D11 is positioned at the first exposure region A11 of photomask 110, and is adjacent to the first perimeter circuit pattern L11.The second dummy leads pattern D12 is positioned at the 3rd exposure region A13 of photomask 110, and is adjacent to the second perimeter circuit pattern L12.The first dummy leads pattern D11 and the second dummy leads pattern D12 are respectively the extension of the first perimeter circuit pattern L11 and the second perimeter circuit pattern L12.That is to say that the first dummy leads pattern D11 and the second dummy leads pattern D12 also comprise the pattern of grid circuit G and the pattern of common electrode circuit CS.
First overlaps pattern of pixels P11 is positioned at the first exposure region A11 of photomask 110, and is adjacent to the first dummy leads pattern D11.Quadruple is closed the 3rd exposure region A13 that pattern of pixels P14 is positioned at photomask 110, and is adjacent to the second dummy leads pattern D12.That is to say that the first perimeter circuit pattern L11, the first dummy leads pattern D11 and first overlap pattern of pixels P11 and be positioned at the first exposure region A11, and adjacency in regular turn.The second perimeter circuit pattern L12, the second dummy leads pattern D12 and quadruple are closed pattern of pixels P14 and all are positioned at the 3rd exposure region A13, and adjacency in regular turn.
Second overlaps pattern of pixels P12 and the 5th overlaps the lateral edges place that pattern of pixels P15 is positioned at the second exposure region A12 of photomask 110, and the 5th coincidence pattern of pixels P15 is positioned at the outside.The 3rd overlaps pattern of pixels P13 and sixfold closes the opposite side edge that pattern of pixels P16 is positioned at the second exposure region A12 of photomask 110, and sixfold closes pattern of pixels P16 and is positioned at the outside.10 of center pixel pattern P are positioned at the centre of the second exposure region A12 of photomask 110.That is to say that the 5th overlaps pattern of pixels P15, second overlaps pattern of pixels P12, center pixel pattern P 10, the triple and pattern of pixels P13 and sixfold and close pattern of pixels P16 and all be positioned at the second exposure region A12, and adjacency in regular turn.
First closes the pattern of pattern of pixels P11～P16 corresponding to the pixel of thin film transistor base plate 130 to sixfold.Wherein, close among pattern of pixels P11～P16 to sixfold first, hatched example areas configuration pattern of pixels is only arranged, white space does not then dispose pattern of pixels, just like as mosaic (mosaic) totem.
For instance, the first coincidence pattern of pixels P11 overlaps pattern of pixels P12 complementation with second.That is to say that first hatched example areas that overlaps pattern of pixels P11 is just corresponding to second white space that overlaps pattern of pixels P12; First white space that overlaps pattern of pixels P11 is just corresponding to second hatched example areas that overlaps pattern of pixels P12.After the first coincidence pattern of pixels P11 overlaps pattern of pixels P12 double exposure with second, hatched example areas and white space coincide mutually, and making wins overlaps pattern of pixels P11 and be bonded with each other into complete pattern of pixels with the pattern that the second coincidence pattern of pixels P12 is exposed.
Sixfold closes pattern of pixels P16 and overlaps pattern of pixels P12 complementation with second.In like manner, after sixfold closes pattern of pixels P16 and overlaps pattern of pixels P12 double exposure with second, hatched example areas and white space coincide mutually, make sixfold close pattern of pixels P16 and second and overlap the pattern that pattern of pixels P12 exposed and be bonded with each other into complete pattern of pixels.
In addition, quadruple is closed pattern of pixels P14 and is overlapped pattern of pixels P13 complementation with the 3rd.In like manner, after quadruple is closed pattern of pixels P14 and is overlapped pattern of pixels P13 double exposure with the 3rd, hatched example areas and white space coincide mutually, make quadruple close pattern of pixels P14 and the 3rd and overlap the pattern that pattern of pixels P13 exposed and be bonded with each other into complete pattern of pixels.
The 5th overlaps pattern of pixels P15 overlaps pattern of pixels P13 complementation with the 3rd.In like manner, when the 5th coincidence pattern of pixels P15 overlaps pattern of pixels P13 double exposure with the 3rd after, hatched example areas and white space coincide mutually, and the pattern that makes the 5th coincidence pattern of pixels P15 and the 3rd coincidence pattern of pixels P13 be exposed is bonded with each other into complete pattern of pixels.
Below more describe how photomask 110 is carried out repeated exposure to form thin film transistor base plate 130 in detail with process flow diagram.Please refer to Fig. 3 A～Fig. 3 B and Fig. 4 A～Fig. 4 H, Fig. 3 A～Fig. 3 B illustrate thin film transistor base plate first embodiment of the present invention the manufacture method process flow diagram, Fig. 4 A～Fig. 4 H illustrates each step synoptic diagram of Fig. 3.
Please refer to Fig. 4 A, in step SO2, provide a substrate 131.Substrate 131 for example is a glass substrate.
Then, referring again to Fig. 4 A, in step SO4, provide photomask 110.
Then, please refer to Fig. 4 B, in step SO6, form a photoresist layer 132 on substrate 131.
Then, please refer to Fig. 4 C, in step SO8,, make photomask 110 only expose the first perimeter circuit pattern L11, the first dummy leads pattern D11 and first and overlap pattern of pixels P11 with the subregion of at least one shadow shield 111 shield light masks 110.Overlap pattern of pixels P11 exposed photoresist layer 132 simultaneously and with the first perimeter circuit pattern L11, the first dummy leads pattern D11 and first.This moment, photoresist layer 132 only passed through exposure technology, and did not carry out developing process as yet, was represented by dotted lines not develop as yet but be transferred to the various patterns of photoresist layer 132 in graphic.
Then, please refer to Fig. 4 D, in step S10, mobile photomask 110 is so that the second coincidence pattern of pixels P12 of photomask 110 overlaps the position of pattern of pixels P11 corresponding to first on the substrate 131.And with the subregion of shadow shield 111 shield light masks 110, photomask 110 is exposed second overlaps pattern of pixels P12, center pixel pattern P the 10, the 3rd overlaps pattern of pixels P13 and sixfold closes pattern of pixels P16.
Simultaneously and with second of photomask 110 overlap pattern of pixels P12, center pixel pattern P the 10, the 3rd overlaps pattern of pixels P13 and sixfold closes pattern of pixels P16 exposed photoresist layer 132.Owing to second of photomask 110 overlaps the position of pattern of pixels P12 corresponding to the first coincidence pattern of pixels P11 of substrate 131, therefore on substrate 131, second overlaps the position of pattern of pixels P12 double exposure in the first coincidence pattern of pixels P11.The pattern of the pattern of the first exposure region A11 of photomask 110 and the second exposure region A12 of photomask 110 promptly overlaps pattern of pixels P12 by second and the first coincidence pattern of pixels P11 engages.
Then, please refer to Fig. 4 E, in step S12, mobile photomask 110 is so that the 5th the overlapping pattern of pixels P15 and second and overlap pattern of pixels P12 and overlap the position that pattern of pixels P13 and sixfold close pattern of pixels P16 corresponding to the 3rd on the substrate 131 of photomask 110.And,, photomask 110 overlaps that pattern of pixels P15, second overlaps pattern of pixels P12, center pixel pattern P the 10, the 3rd overlaps pattern of pixels P13 and sixfold closes pattern of pixels P16 so that exposing the 5th with the subregion of shadow shield 111 shield light masks 110.
Simultaneously, overlap that pattern of pixels P15, second overlaps pattern of pixels P12, center pixel pattern P the 10, the 3rd overlaps pattern of pixels P13 and sixfold closes pattern of pixels P16 exposed photoresist layer 132 and with the 5th of photomask 110.Because the 5th of photomask 110 overlaps pattern of pixels P15 and second and overlaps pattern of pixels P12 and overlap the position that pattern of pixels P13 and sixfold close pattern of pixels P16 corresponding to the 3rd of substrate 131, therefore the 5th overlap pattern of pixels P15 and second and overlap pattern of pixels P12 double exposure and overlap the position that pattern of pixels P13 and sixfold close pattern of pixels P16 in the 3rd.
Then, please refer to Fig. 4 F, in step S14, mobile photomask 110 is so that the 5th the overlapping pattern of pixels P15 and second and overlap pattern of pixels P12 and overlap the position that pattern of pixels P13 and sixfold close pattern of pixels P16 corresponding to the 3rd of right side on the substrate 131 of photomask 110.And,, photomask 110 overlaps that pattern of pixels, second overlaps pattern of pixels P12, center pixel pattern P 10 and the 3rd overlaps pattern of pixels P13 so that exposing the 5th with the subregion of shadow shield 111 shield light masks 110.
Overlap pattern of pixels P15, the second coincidence pattern of pixels P12, center pixel pattern P 10 and the 3rd coincidence pattern of pixels P13 exposed photoresist layer 132 simultaneously, and with the 5th of photomask 110.Because the 5th of photomask 110 overlaps pattern of pixels P15 and second and overlaps pattern of pixels P12 and overlap the position that pattern of pixels P13 and sixfold close pattern of pixels P16 corresponding to the 3rd of substrate 131, therefore the 5th overlap pattern of pixels P15 and second and overlap pattern of pixels P12 double exposure and overlap the position that pattern of pixels P13 and sixfold close pattern of pixels P16 in the 3rd.
Then, please refer to Fig. 4 G, in step S16, mobile photomask 110 overlaps pattern of pixels P13 so that the quadruple of photomask 110 is closed pattern of pixels P14 corresponding to the 3rd of right side on the substrate 131.And,, photomask 110 closes pattern of pixels P14, the second dummy leads pattern D12 and the second perimeter circuit pattern L12 so that exposing quadruple with the subregion of shadow shield 111 shield light masks 110.
Simultaneously, close pattern of pixels P14, the second dummy leads pattern D12 and the second perimeter circuit pattern L12 exposed photoresist layer 132 with the quadruple of photomask 100.Because the quadruple of photomask 110 is closed the position of pattern of pixels P14 corresponding to the 3rd coincidence pattern of pixels P13 of substrate 131, therefore quadruple is closed the position of pattern of pixels P14 double exposure in the 3rd coincidence pattern of pixels P13.
Then, please refer to Fig. 4 H, in step S18, with a developer solution patterning photoresist layer 132.
Then, referring again to Fig. 4 H, in step S20, be shade etching substrates 131 with the photoresist layer 132 of patterning.So promptly finish the line pattern of one photo-marsk process of thin film transistor base plate 130.
In addition, in above-mentioned steps, come mobile shade 111 by a travel mechanism (not illustrating), and expose with a light beam.Travel mechanism for example is step motor or servo motor.Under certain precision, travel mechanism has a minimum displacement, and the displacement of travel mechanism can be less than this minimum displacement.That is to say that when travel mechanism desired mobile shade 111 to ad-hoc location, because travel mechanism can't be displaced into shadow shield 111 in the distance less than minimum displacement, so shadow shield 111 may form mechanism's bit errors in minimum displacement.
In addition, light beam has a diffraction scope, and light beam also may will form the optical registration error in this diffraction scope.
In step S10, as Fig. 4 D and shown in Figure 1.The edge of shadow shield 111 (shadow shield 111 is illustrated in Fig. 4 D) overlaps the boundary line L (boundary line L is illustrated in Fig. 1) that pattern of pixels P15 and second overlaps pattern of pixels P12 to being positioned at the 5th of photomask 110, overlaps pattern of pixels P15 and exposes the second heavy pattern of pixels P12 that closes so as to covering the 5th.The influence of the mechanism's bit errors of shadow shield 111 and the optical registration error of light beam may overlap the part the 5th near boundary line L pattern of pixels P15 double exposure on the first dummy leads pattern D11 of substrate 131.Because the first dummy leads pattern D11 is positioned at non-display area, so the bit errors of the bit errors of shadow shield 111 and light beam can't produce bad joint mark in the viewing area, more can not influence the briliancy homogeneity of viewing area.
Moreover, overlap pattern of pixels P15 with the 5th of the first dummy leads pattern D11 double exposure and can't destroy the first dummy leads pattern D11, therefore the first peripheral lead pattern L11 and the first dummy leads pattern D11 still can keep excellent function.
Preferably, as shown in Figure 1, under the influence of the optical registration error of mechanism's bit errors of shadow shield 111 and light beam, the width W D11 of the first dummy leads pattern D11 of present embodiment only needs greater than the minimum displacement of shadow shield 111 and the diffraction scope sum of light beam, can make careless exposed portions the 5th overlap pattern of pixels P15 all double exposure on the first dummy leads pattern D11.
Wherein, the first dummy leads pattern D11 of present embodiment adopts lead pattern and does not adopt the virtual pixel pattern.Under the condition of the diffraction scope sum of the minimum displacement of above-mentioned shadow shield 111 and light beam, the width W D11 of the first dummy leads pattern D11 only needs can meet the requirements at 1～5 millimeter (mm).Compared to adopting the virtual pixel design of patterns, the width W D11 of the first dummy leads pattern D11 of present embodiment can significantly dwindle.
In like manner, in step S14, under the condition of the diffraction scope sum of the minimum displacement of above-mentioned shadow shield 111 and light beam, the width of the second dummy leads pattern D12 only needs can meet the requirements at 1～5 millimeter (mm).Compared to adopting the virtual pixel design of patterns, the width W D12 of the second dummy leads pattern D12 can significantly dwindle.
Moreover in the step of above-mentioned repeated exposure, because first to close pattern of pixels P11～P16 to sixfold all be the mosaic totem, so the pattern on the thin film transistor base plate 130 does not have tangible joint straight line.
Second embodiment
Please refer to Fig. 5, its illustrate photomask second embodiment of the present invention synoptic diagram.The manufacture method difference of the manufacture method of the photomask 210 of present embodiment and thin film transistor base plate (not illustrating) and the photomask 110 of first embodiment and thin film transistor (TFT) 130 is: the first dummy leads pattern D21 is that example explains with the pattern of the source line S (claiming data line again) that is positioned at a side, and the second dummy leads pattern D22 is that example explains with the pattern of the source line S that is positioned at another side then.
The allocation position of the first exposure region A21, the second exposure region A22 and the 3rd exposure region A23 is also along with the first dummy leads pattern D21 and the second dummy leads pattern D22 and dispose along the bearing of trend of source line S.As shown in Figure 5, the first perimeter circuit pattern L21, the first dummy leads pattern D21 and first overlap pattern of pixels P21 and are positioned at the first exposure region A21, and adjacency in regular turn.The 5th overlaps pattern of pixels P25, second overlaps pattern of pixels P22, center pixel pattern P the 20, the 3rd and overlaps pattern of pixels P23 and sixfold and close pattern of pixels P26 and be positioned at the second exposure region A22, and adjacency in regular turn.Quadruple closes pattern of pixels P24, the second dummy leads pattern D22 and the second perimeter circuit pattern L22 is positioned at the 3rd exposure region A23, and adjacency in regular turn.
The method for making of the thin film transistor base plate of the present embodiment then method for making with the thin film transistor base plate 130 of first embodiment is similar, no longer repeats at this.
Though the manufacturing method of film transistor base plate of the foregoing description is that example explains to engage three center pixel patterns, yet the quantity that engages the center pixel pattern is also not subject to the limits, above-mentioned manufacture method also can engage two or three above center pixel patterns, with the size of extension film transistor base.
Moreover the first mosaic totem configuration of closing pixel to sixfold also is not limited to the content of above-mentioned pattern, and the deviser can dispose according to actual demand.
Disclosed photomask of the above embodiment of the present invention and manufacturing method of film transistor base plate are utilized the dummy leads pattern and are overlapped the design of pattern of pixels, make photomask after repeated exposure repeatedly, the pattern that is exposed can be bonded into the thin film transistor base plate of specific dimensions, have more multiple advantages, below only enumerate the part advantage and be described as follows:
1. by the program of repeated exposure, can engage the coincidence pattern of pixels, to make the thin film transistor base plate of specific dimensions.Therefore same photomask can be made the different size thin film transistor base plate.
2. the size of thin film transistor base plate can constantly be extended, and is not subject to the size of photomask.
3. the dummy leads pattern is positioned at non-display area, so the optical registration error of mechanism's bit errors of shadow shield and light beam can't produce bad joint mark in the viewing area, more can not influence the briliancy homogeneity of viewing area.
4. double exposure can't destroy the dummy leads pattern in the coincidence pattern of pixels of dummy leads pattern, makes peripheral lead pattern and dummy leads pattern still can keep the function of lead-in wire.
5. the width of dummy leads pattern only needs greater than the minimum displacement of shadow shield and the diffraction scope sum of light beam, can make not very exposed portions overlap pattern of pixels all double exposure on the dummy leads pattern.
6. the dummy leads pattern does not adopt the virtual pixel pattern adopting lead pattern, and under the condition of the diffraction scope sum of the minimum displacement of above-mentioned shadow shield and light beam, the width of dummy leads pattern only needs can meet the requirements at 1～5 millimeter (mm).Compared to adopting the virtual pixel design of patterns, the width of dummy leads pattern significantly dwindles.
7. after the reduced width of dummy leads pattern, increase the space of backguy, and reduced the overall impedance value of thin film transistor base plate.
8. first exposure region only disposes the dummy leads pattern that engages usefulness and overlaps pattern of pixels, so the configurable large-area center pixel pattern of second exposure region.Therefore in the manufacture process of thin film transistor base plate, can once engage large-area center pixel pattern, reduce the processing step number of times significantly, more promote production capacity.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.
Claims (12)
1. photomask, in order to make a thin film transistor base plate, this photomask has one first exposure region, one second exposure region and one the 3rd exposure region, and this second exposure region is between this first exposure region and the 3rd exposure region, it is characterized in that this photomask comprises:
One first perimeter circuit pattern is positioned at this first exposure region;
One first dummy leads pattern is positioned at this first exposure region, and is adjacent to this first perimeter circuit pattern;
One first overlaps pattern of pixels, is positioned at this first exposure region, and is adjacent to this first dummy leads pattern; And
One second overlaps pattern of pixels, be positioned at this second exposure region, this first overlaps pattern of pixels and second overlaps the pattern of pixels complementation with this, wherein this first overlap pattern of pixels with this second overlap the pattern of pixels double exposure after, the pattern that this first exposure region and this second exposure region are exposed is bonded with each other.
2. photomask according to claim 1 is characterized in that, also comprises:
One the 3rd overlaps pattern of pixels, is positioned at this second exposure region;
One second perimeter circuit pattern is positioned at the 3rd exposure region;
One second dummy leads pattern is positioned at the 3rd exposure region, and is adjacent to this second perimeter circuit pattern; And
One quadruple is closed pattern of pixels, be positioned at the 3rd exposure region, and be adjacent to this second dummy leads pattern, this quadruple is closed pattern of pixels and is overlapped the pattern of pixels complementation with the 3rd, wherein this quadruple is closed after pattern of pixels overlaps the pattern of pixels double exposure with the 3rd, and the pattern that this second exposure region and the 3rd exposure region are exposed is bonded with each other.
3. photomask according to claim 2 is characterized in that, also comprises:
One the 5th overlaps pattern of pixels, is positioned at this second exposure region, and is adjacent to the outside of this second coincidence pattern of pixels, and overlaps the pattern of pixels complementation with the 3rd; And
One sixfold closes pattern of pixels, be positioned at this second exposure region, and be adjacent to the 3rd outside that overlaps pattern of pixels, and second overlap the pattern of pixels complementation with this, wherein the 5th overlap pattern of pixels overlap with the 3rd pattern of pixels double exposure and this sixfold close pattern of pixels with this second overlap the pattern of pixels double exposure after, the secondary pattern that this second exposure region is exposed is bonded with each other.
4. photomask according to claim 1, it is characterized in that, this photomask passes through the zone of a shadow shield shaded portions, and exposes with a light beam, and the width of this first dummy leads pattern is more than or equal to minimum displacement and this light beam diffraction scope sum of this shadow shield.
5. photomask according to claim 1 is characterized in that, the width of this first dummy leads pattern is less than or equal to the width of this first coincidence pattern of pixels or this second coincidence pattern of pixels.
6. photomask according to claim 1 is characterized in that, the width of this first dummy leads pattern is 1～5 millimeter.
7. photomask according to claim 1 is characterized in that, this first dummy leads pattern comprises the data line pattern.
8. photomask according to claim 1 is characterized in that, this first dummy leads pattern comprises scan line pattern.
9. a manufacturing method of film transistor base plate is characterized in that, comprising:
One substrate is provided;
One photomask is provided, this photomask has one first exposure region, one second exposure region and one the 3rd exposure region, this second exposure region is between this first exposure region and the 3rd exposure region, this photomask comprises one first perimeter circuit pattern, one first dummy leads pattern, one first overlaps pattern of pixels and one second overlaps pattern of pixels, this first perimeter circuit pattern is positioned at this first exposure region, this first dummy leads pattern is positioned at this first exposure region, and be adjacent to this first perimeter circuit pattern, this first coincidence pattern of pixels is positioned at this first exposure region, and being adjacent to this first dummy leads pattern, this first overlaps pattern of pixels and second overlaps the pattern of pixels complementation with this;
Form a photoresist layer on this substrate;
Overlap pattern of pixels this photoresist layer that exposes with this first perimeter circuit pattern, this first dummy leads pattern and this first;
Second overlap pattern of pixels this photoresist layer that exposes with this, this second overlaps pattern of pixels double exposure in this first position that overlaps pattern of pixels;
This photoresist layer of patterning; And
With this photoresist layer is this substrate of shielding etching, to form a plurality of perimeter circuit patterns and a plurality of pattern of pixels.
10. manufacturing method of film transistor base plate according to claim 9; it is characterized in that; this photomask also comprises one the 3rd and overlaps pattern of pixels; one second perimeter circuit pattern; one second a dummy leads pattern and a quadruple are closed pattern of pixels; the 3rd overlaps pattern of pixels is positioned at this second exposure region; this second perimeter circuit pattern is positioned at the 3rd exposure region; this second dummy leads pattern is positioned at the 3rd exposure region; and be adjacent to this second perimeter circuit pattern; this quadruple is closed pattern of pixels and is positioned at the 3rd exposure region; and be adjacent to this second dummy leads pattern; this quadruple is closed pattern of pixels and is overlapped the pattern of pixels complementation with the 3rd, and this manufacturing method of film transistor base plate also comprises:
Overlap pattern of pixels this photoresist layer that exposes with the 3rd; And
Close pattern of pixels and this this photoresist layer of second dummy leads pattern exposure with this second perimeter circuit pattern, this quadruple, this quadruple is closed the position of pattern of pixels double exposure in the 3rd coincidence pattern of pixels.
11. manufacturing method of film transistor base plate according to claim 9; it is characterized in that; this photomask also comprises one the 5th coincidence pattern of pixels and a sixfold closes pattern of pixels; the 5th overlaps pattern of pixels is positioned at this second exposure region; and be adjacent to this second outside that overlaps pattern of pixels; and overlap the pattern of pixels complementation with the 3rd; this sixfold closes pattern of pixels and is positioned at this second exposure region; and be adjacent to the 3rd outside that overlaps pattern of pixels; and second overlap the pattern of pixels complementation with this, this manufacturing method of film transistor base plate also comprises:
Overlap pattern of pixels and this sixfold with the 3rd and close pattern of pixels this photoresist layer that exposes;
Overlap pattern of pixels and this second with the 5th and overlap pattern of pixels this photoresist layer that exposes, the 5th overlaps the position of pattern of pixels double exposure in the 3rd coincidence pattern of pixels, and this second coincidence pattern of pixels double exposure closes the position of pattern of pixels in this sixfold.
12. manufacturing method of film transistor base plate according to claim 9 is characterized in that, also comprises: all the other zones of covering this photomask desire exposure with at least one shadow shield.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007103018435A CN100561339C (en) | 2007-12-18 | 2007-12-18 | Photomask and manufacturing method of film transistor base plate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007103018435A CN100561339C (en) | 2007-12-18 | 2007-12-18 | Photomask and manufacturing method of film transistor base plate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101183213A true CN101183213A (en) | 2008-05-21 |
| CN100561339C CN100561339C (en) | 2009-11-18 |
Family
ID=39448533
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2007103018435A Active CN100561339C (en) | 2007-12-18 | 2007-12-18 | Photomask and manufacturing method of film transistor base plate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100561339C (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101986206A (en) * | 2010-07-30 | 2011-03-16 | 南京中电熊猫液晶显示科技有限公司 | Method for utilizing functional mask board to manufacture mask substrate for solidifying sealing glue |
| CN103869602A (en) * | 2012-12-14 | 2014-06-18 | 京东方科技集团股份有限公司 | Mask plate, and method of mask plate used for realizing exposure joint |
| CN105093753A (en) * | 2015-08-21 | 2015-11-25 | 武汉华星光电技术有限公司 | Mask plate, array substrate and manufacturing method of array substrate |
| CN107290879A (en) * | 2017-08-11 | 2017-10-24 | 深圳市华星光电技术有限公司 | Light shield for liquid crystal display panel |
| CN110398848A (en) * | 2019-07-22 | 2019-11-01 | 深圳市华星光电半导体显示技术有限公司 | A kind of light shield, array substrate and preparation method thereof |
| CN111427231A (en) * | 2020-04-09 | 2020-07-17 | 深圳市华星光电半导体显示技术有限公司 | Mask plate and novel production line |
| WO2021190396A1 (en) * | 2020-03-23 | 2021-09-30 | 长鑫存储技术有限公司 | Mask |
| CN113671789A (en) * | 2020-05-14 | 2021-11-19 | 咸阳彩虹光电科技有限公司 | Photomask, exposure method and exposure system |
| WO2023160410A1 (en) * | 2022-02-28 | 2023-08-31 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method therefor, and liquid crystal panel |
-
2007
- 2007-12-18 CN CNB2007103018435A patent/CN100561339C/en active Active
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101986206A (en) * | 2010-07-30 | 2011-03-16 | 南京中电熊猫液晶显示科技有限公司 | Method for utilizing functional mask board to manufacture mask substrate for solidifying sealing glue |
| CN101986206B (en) * | 2010-07-30 | 2012-08-08 | 南京中电熊猫液晶显示科技有限公司 | Method for utilizing functional mask board to manufacture mask substrate for solidifying sealing glue |
| CN103869602A (en) * | 2012-12-14 | 2014-06-18 | 京东方科技集团股份有限公司 | Mask plate, and method of mask plate used for realizing exposure joint |
| CN105093753A (en) * | 2015-08-21 | 2015-11-25 | 武汉华星光电技术有限公司 | Mask plate, array substrate and manufacturing method of array substrate |
| CN105093753B (en) * | 2015-08-21 | 2019-02-12 | 武汉华星光电技术有限公司 | Mask plate, array substrate and its manufacturing method |
| CN107290879A (en) * | 2017-08-11 | 2017-10-24 | 深圳市华星光电技术有限公司 | Light shield for liquid crystal display panel |
| CN110398848A (en) * | 2019-07-22 | 2019-11-01 | 深圳市华星光电半导体显示技术有限公司 | A kind of light shield, array substrate and preparation method thereof |
| WO2021190396A1 (en) * | 2020-03-23 | 2021-09-30 | 长鑫存储技术有限公司 | Mask |
| CN111427231A (en) * | 2020-04-09 | 2020-07-17 | 深圳市华星光电半导体显示技术有限公司 | Mask plate and novel production line |
| CN113671789A (en) * | 2020-05-14 | 2021-11-19 | 咸阳彩虹光电科技有限公司 | Photomask, exposure method and exposure system |
| WO2023160410A1 (en) * | 2022-02-28 | 2023-08-31 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method therefor, and liquid crystal panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100561339C (en) | 2009-11-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100561339C (en) | Photomask and manufacturing method of film transistor base plate | |
| EP3396443B1 (en) | Manufacturing method for a color film substrate | |
| TWI569425B (en) | Display panel | |
| US10620526B2 (en) | Mask, manufacturing method thereof, patterning method employing mask, optical filter | |
| US9978595B2 (en) | Photo mask and exposure system | |
| KR100502797B1 (en) | Liquid crystal display device and manufacturing method thereof | |
| CN111338144A (en) | Display panel and display device | |
| CN101477318B (en) | Photomask contraposition exposure method and photomask component | |
| KR100611041B1 (en) | photo mask and method for fabricating large scale liquid crystal display device | |
| TWI402918B (en) | Photo-mask and method for manufacturing thin-film transistor substrate | |
| EP3876028A1 (en) | Display substrate motherboard and manufacturing method therefor | |
| US11908804B2 (en) | Array substrate and display panel | |
| CN104040428B (en) | Phase shifting mask and the corrosion-resisting pattern forming method for using the phase shifting mask | |
| KR100468524B1 (en) | Partition exposure method | |
| JP2006235258A (en) | Photomask and method for manufacturing color filter for liquid crystal display apparatus | |
| US20050089770A1 (en) | Printing irregularly-spaced contact holes using phase shift masks | |
| KR20160038189A (en) | Maskless exposure device, maskless exposure method and display substrate manufactured by the maskless exposure device and maskless exposure method | |
| CN113327893B (en) | Preparation method of array substrate, array substrate and liquid crystal display panel | |
| CN110161799B (en) | Phase shift mask plate, array substrate, preparation method of array substrate and display device | |
| WO2021237552A1 (en) | Mask, exposure method and touch panel | |
| JP3714946B2 (en) | Color filter with alignment mark | |
| CN114730850B (en) | Display panel, preparation method thereof and display device | |
| US11809034B2 (en) | Display substrate, display panel and display device | |
| CN113671789A (en) | Photomask, exposure method and exposure system | |
| JP3710964B2 (en) | Display device layout design method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |