CN101174836B - Error reducing comparator-based switch capacitor circuit and method thereof - Google Patents
Error reducing comparator-based switch capacitor circuit and method thereof Download PDFInfo
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- CN101174836B CN101174836B CN2007101819956A CN200710181995A CN101174836B CN 101174836 B CN101174836 B CN 101174836B CN 2007101819956 A CN2007101819956 A CN 2007101819956A CN 200710181995 A CN200710181995 A CN 200710181995A CN 101174836 B CN101174836 B CN 101174836B
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Abstract
An error reducing comparator based switch capacitor (CBSC) circuit comprises: a comparator of a substantial offset, a charge pump controlled by an output of the comparator, and a plurality of capacitors. The CBSC circuit cyclically operates through a sampling phase, and a transfer phase. During the sampling phase, an input voltage is sampled by a first capacitor. During the transfer phase, the charge stored on the first capacitor is transferred to a second capacitor through injecting or draining charge using the charge pump. The amount of the offset is properly set to reduce an error due to circuit delay of the CBSC circuit.
Description
Technical field
The present invention is about a kind of switch capacitor circuit, particularly about (CBSC) circuit of a kind of switch capacitor (comparator based switch capacitor) that reduces the device based on the comparison of error.
Background technology
Compared to the switch capacitor circuit based on operational amplifier, the switch capacitor of device (CBSC) circuit is a kind of emerging technology that more advantage can be provided based on the comparison.As traditional switch capacitor circuit, the CBSC circuit is worked in the two-stage mode equally.Described two stages are " sampling " stage and " transfer " stage, respectively by two non-overlapping clocks (as, Φ
1And Φ
2) institute control.The one typical case's two stages CBSC circuit with sampling frequency f work, the duration in its each stage is 1/2nd slightly little than sampling clock cycle T=1/f's.At sample phase (Φ
1) during, by sampling capacitor device C
1Fetch input voltage V
1Sampled, wherein by C
1"+" end be connected to V
I, and "-" end is connected to common-mode voltage V
CM.At transition phase (Φ
2) during, as shown in Figure 1, by charge transfer circuit, will be stored in sampling capacitor device C
1On electric charge be transferred to integrated capacitor C
2, this charge transfer circuit comprises comparator 130 and charge pump (CP) 140, and charge pump (CP) 140 comprises current source I
1With electric current groove I
2.As shown in Figure 1, C
LThe load capacitor of CBSC circuit 100, V
DDSupply voltage, V
SSThe minimum level in system, and common-mode voltage V
CMBe usually located at V
DDWith V
SSMean value near.Equally, C
LBe connected to V by getting sampling switch 150
CM, and sampling switch 150 is controlled by switching signal S.Charge transfer circuit is to be used to be stored in C
1On electric charge be transferred to C
2, until the current potential at comparator 130 two ends is equal, that is, and V
X=V
CM.CBSC circuit 100 is at transition phase (Φ
2) during operation principle will sketch under.
When charge transfer phase is initial, carries out simply preset (brief preset) and (P) remove C
LThe electric charge of upper storage, to guarantee voltage V
XBe less than V
CM.And by passing through temporarily by output node V
0Be pulled to the minimum level V in system
SSComplete this preset operation.Then, start to enter rough (coarse) charge transfer phase (E1).During rough charge transfer phase, V
X<V
CMAnd CP140 firing current source I
1, and charge injection is included to C
L, C
2And C
1Circuit in, to produce by V
XTo V
CMThe voltage faster climbed is slow to be risen.CP140 continues iunjected charge, until comparator 130 detects V
X>V
CMTill.Detect V at comparator 130
X>V
CMMoment, meticulous (fine) charge transfer phase (E
2) by cut-off current source I
1And firing current groove I
2, with from including C
L, C
2And C
1The circuit electric charge of releasing.If make I
2Be less than I
1, produce V
XTo V
CMThe slower voltage descended is slow to fall.V again detected at comparator 130
X<V
CMMoment, sampling switch 150 is opened to sample and maintain C
LUpper stored charge.
Fig. 2 means the typical sequential chart of CBSC circuit 100 charge transfer phases.At first, first switching signal S is pulled to high level.Thereby, turn-off sampling switch 150, and by load C
LBe connected to V
CM.In this simultaneously, V
OAlso will maintain the sampling position standard in last cycle, and V
XClose to V
CM.Transition phase Φ
2In time t
1Start and in time t
5Finish, it includes four subs (sub-phase): preset (P), rough electric charge shift (E
1), meticulous electric charge shifts (E
2) and keep (Hold) (H).At first CBSC circuit 100 enters the P stage (time t
1), by output node V
OBe pulled to V
SSAnd cause V
XDrop down onto V
XO, V wherein
XOLower than V
CM.In time t
2, enter E
1In the stage, now, comparator detects V
X<V
CM, and CP 140 includes C by charge injection
L, C
2And C
1Circuit in so that V
OWith V
XThere is the slow liter of voltage faster.E
2Stage starts from time t
3, comparator 130 detects V
X>V
CMMoment.Note that due to circuit delay (that is, being reacted to the delay of CP 140 from comparator 130), t
3Slightly be later than V
XRaise and surpass V
CMThat time point.At E
2During stage, CP 140 is from including C
L, C
2And C
1Circuit release electric charge and make V
OWith V
XHave that slower voltage is slow to fall.Finally, CBSC circuit 100 is in time t
4Enter the H stage, that is, comparator 130 detects V again
X<V
CMThe time.Equally, due to circuit delay, t
4Slightly be later than V
XBe reduced to lower than V
CMThat time point.During the H stage, switching signal S is pulled to low level, be stored in C in order to maintain
LOn electric charge, and charge pump circuit CP 140 is imposed to forbidding.
The existing subject matter of the CBSC circuit 100 of known technology is due to circuit delay, and makes final sampling value V
OAlways there is error to exist.From Fig. 2, be not difficult to find, actual sampling value can be slightly lower than desirable sampling value, i.e. V
XBe reduced to lower than V
CMAccurate instantaneous value.
Therefore, need badly and a kind ofly can eliminate the CBSC circuit that produces error because of circuit delay.
Summary of the invention
In an embodiment, disclosed a kind of circuit of the switch capacitor (CBSC) in order to the device based on the comparison that reduces error, this CBSC circuit comprises comparator, charge pump and a plurality of capacitor of being controlled by this comparator with side-play amount, wherein this CBSC circuit is sampled an input voltage by one first capacitor during sample phase, and, during transition phase, by this charge pump, the electric charge be stored on this first capacitor is transferred to this second capacitor.
In an embodiment, disclosed a kind of for reducing the method for the error that the switch capacitor of device (CBSC) circuit based on the comparison produces because of circuit delay, this CBSC circuit comprises a comparator, a charge pump of being controlled by this comparator and a plurality of capacitor, and the method comprises: to introducing a side-play amount in this comparator; During sample phase, provide one first capacitor to be sampled an input voltage; And, during transition phase, utilize this comparator so that the electric charge be stored on this first capacitor is transferred to one second capacitor.
The accompanying drawing explanation
Fig. 1 means to be positioned at switch capacitor (CBSC) circuit of the known device based on the comparison of transition phase.
The typical sequential chart of the CBSC of Fig. 2 presentation graphs 1.
Fig. 3 means specially to introduce to comparator an embodiment of the CBSC circuit of offset voltage.
Fig. 4 means an embodiment of the calibration circuit of the offset voltage used for generation of CBSC circuit in Fig. 3.
One embodiment of the controller calibration of Fig. 5 presentation graphs 4 calibration circuits.
The actual figure of the difference channel of CBSC circuit in Fig. 6 presentation graphs 3.
The main element symbol description
The switch capacitor of 100 known devices based on the comparison (CBSC) circuit
The switch capacitor circuit of 100A device based on the comparison of the present invention
140,140A charge pump 150 sampling switches
160,520 adders 340 add way circuit
400 calibration circuit 410 comparators
420 controller calibration 430 digital to analog converters
510 unit delay circuit
Embodiment
The present invention is relevant for the self calibration switch capacitor of device (CBSC) circuit based on the comparison.Although specification has been described several being regarded as for putting into practice preferred embodiment of the present invention,, should be appreciated that, the present invention is not limited to this.
Application of the present invention is extensive, and it can be applicable to any sampled data analog circuit.For example, the present invention is applicable to pipeline system ADC (analog-digital converter), also is applicable to delta sigma ADC.The sampled data analog circuit is worked in the multistage mode usually.For example (but being not limited to), disclose a kind of according to two-phase switch capacitor circuit of the present invention.Known technology as described above, two stages of saying are sample phase (Φ
1) and transition phase (Φ
2).In sample phase (Φ
1) during, input signal is sampled, and be stored in input capacitor.In transition phase (Φ
2) during, by charge pump to inject/leakage current of the feedback condenser of connecting with input capacitor, so that the electric charge be stored on input capacitor is transferred to feedback condenser.Determine with comparator whether the electric charge be stored on input capacitor all has been transferred to feedback condenser.Complete once the electric charge transfer be detected, be about to charge pump circuit and forbidden, and stop the electric charge transfer.From the above, due to circuit delay, electric charge shifts and there will be error.Different from known CBSC circuit, especially comparator is imposed to offset voltage, to reduce the error produced because of circuit delay.
Fig. 3 means that it is in charge transfer phase (Φ according to CBSC circuit 100A of the present invention
2) state.Wherein, the CBSC circuit 100 of CBSC circuit 100A and known technology is identical, except the reference voltage V of comparator 130
CMWith V '
CMReplace V '
CMBy adding 340 couples of reference voltage V of way circuit
CMWith offset voltage V
OSAdded gross income sum value.By suitable setting offset voltage V
OSValue, can eliminate final sampling value V fully
OThe error produced because of circuit delay.
While supposing without offset voltage (, V
OS=0 o'clock) final sampling value V
OError be ε.This error is defined as final sampling value V
OPoor with desirable sampling value without in the circuit delay situation.For CBSC circuit 100A, as described above, ε is always negative value because of circuit delay.If offset voltage V
OSExist, this final sampling value V
OTherefore middle meeting is introduced into another extra error item.Based on principle of charge conservation, the value of this extra error item is:
ε’＝V
OS·(C
1/C
2)
If by V
OSGet and make V
OS=-ε (C
2/ C
1), this extra error item compensating error ε fully.
Therefore, by specially to comparator, introducing a suitable offset voltage, offset final sampling value V fully
OError.
Although Fig. 3 utilizes the explicit way circuit 340 that adds by offset voltage V
OSAdd V to
OIn, but, in implementation, can, without by adding way circuit, can realize offset voltage.For example, can utilize the high-gain differential pair that includes two input transistors to realize comparator.Mismatch (mismatch) between two input transistors has attracted side-play amount for comparator.Therefore, offset voltage V
OSCan realize by the mismatch differential pair with suitable amount of mismatch.In known technology, for CMOS transistor mismatch and the effectively existing goodish development of analytical technology of offset voltage relation between the two, for example, by McGraw-Hill, in Design of Analog CMOS IntegratedCircuits the 13rd chapter of being shown by Behzad Razavi of calendar year 2001 publication, can learnt.
In one embodiment, according to the estimation circuit delay that will occur and therefore to final sampling value V
OThe impact of error, predetermined corresponding offset voltage V
OSValue.In implementation, due to a variety of causes, as variation of temperature drift and manufacturing technology etc., can't accurately estimate the error produced by circuit delay.Therefore, if only based on estimation, set offset voltage V
OSValue, only can reduce final sampling value V
OError, but and can not be eliminated fully.
In one embodiment, select offset voltage V in one group of predetermined value
OSValue so that by final sampling value V
OError minimized.
In one embodiment, by the calibration circuit started between alignment epoch, when system starts or system not in the period at intermittence in active state to selection offset voltage V in one group of predetermined value
OSValue, in addition, now also without input signal, wait to sample.Between alignment epoch, the CBSC circuit 100A of Fig. 3 still operates with two stage method repeatedly.Each sample phase between alignment epoch, all capacitors (C in Fig. 3
1, C
2And C
L) all by zero setting (that is, removing electric charge).In each transition phase end point, ideal situation is load capacitor C
LOn should be without electric charge, and final sampling value V
OShould with common-mode voltage V
CMEquate.If final sampling value V
OBe less than V
CM(that is, ε<0), need to increase offset voltage V
OSValue, to make up error.If final sampling value V
OBe greater than V
CM(that is, ε>0), need to reduce offset voltage V
OSValue, to make up error.In this way, our re-adjustments offset voltage V
OSValue, to minimize final sampling value V
OError.
Fig. 4 representation case expressivity calibration circuit 400, it comprises: comparator 410, in order to more final sampling value V
OWith V
CM, to produce binary decision value D; Controller calibration 420, for receiving binary decision value D and producing digital control word D
OSAnd digital to analog converter, in order to by digital control word D
OSBe converted to offset voltage V
OS.Binary decision value D is 1 (V
O>V
CMThe time) or-1 (V
O<V
CMThe time).In the embodiment shown in fig. 5, by the controller calibration that comprises unit delay circuit 510 and adder 520, when D=-1, just increase digital control word D
OSValue, and, when D=1, reduce digital control word D
OSValue.In one embodiment, the mismatch by the differential pair in the comparator of core CBSC circuit to be calibrated, realize offset voltage V
OS.In one embodiment, the differential pair in the comparator of core CBSC circuit to be calibrated has multiple configuration, and obviously has the situation of mismatch, and DAC430 is realized by implicit expression by selecting one of described multiple configuration.
Wherein, under the non-ideal circuitry state, output signal need to have in the system of zero mean, though system in active state, we also can select skew is calibrated.In other words, even the CBSC circuit is receiving signal, also can carry out calibration.Because output signal need to have zero mean, we can regulate offset voltage continuously, so that output signal has zero mean.Can use the calibration circuit shown in Fig. 4, but insert the low-pass filter circuit (not shown), be still preferentially and consider, to filter the binary decision value D from comparator 410, make the comparatively smoothing of Adaptive change (adaptation) of offset voltage.
It will be understood by one of ordinary skill in the art that disclosed principle can implement with various forms, comprising:
1. in an embodiment, can be by output voltage V
OBe pulled to preset (P) maximum potential V during the stage in system
ODForce thus and form V
X>V
CMCondition, enter rough transition phase (E afterwards
1).Under this situation, I
1Need become the electric current groove, and I
2Need become current source.
2. in an embodiment, can omit meticulous transition phase E
2, because can be eliminated by offset voltage by the caused error of circuit delay.In the case, can save I
2, and improved the integrated operation speed of switch capacitor circuit.Equally, offset voltage V
OSPolarity need be exchanged, this is because due to the caused final sampling value V of circuit delay
OThe polarity of error is exchanged.
3. in an embodiment, can be with difference channel but not single-end circuit is realized core CBSC circuit and calibration circuit.Difference core CBSC circuit comprises: a pair of input capacitor C
1+And C
1-, a pair of feedback condenser C
2+And C
2-, a pair of load capacitor C
L+And C
L-, a comparator and a charge pump circuit.During sample phase, input capacitor is to C
1+And C
1-One differential voltage is sampled.During transition phase, by input capacitor sampled and differential voltage be transferred to feedback condenser to C
2+And C
2-.Fig. 6 means an exemplary CBSC circuit 100B, during transition phase, and its Differential correspondence part that is the described single-end circuit 100A of Fig. 3.Although note that and save meticulous transition phase E in the CP140A of Fig. 6
2, it will be understood by one of ordinary skill in the art that can be by adding by E
2The current source I controlled
2+With electric current groove I
2-Can reach the same purpose, and this also is included meticulous transition phase.In the difference channel structure, the comparator 410 (referring to Fig. 4) in calibration circuit 400 needs relatively V
O+With V
O-But not compare V
OWith V
CM.
4. in an embodiment, during transition phase, the capacitor C in Fig. 3
1"+" end can be connected to and be different from V
CMVoltage.For example, for pipeline system ADC application, be pursuant to the sampling input voltage range of gained during sample phase, can be by C
1"+" end be connected in a plurality of other pre-defined voltages.Yet the principle of teachings of the present invention equally also is applicable to this class situation.
5. in another embodiment, with a plurality of capacitors, implement capacitor C
1, described a plurality of capacitors are in parallel during sample phase, but during transition phase, its "+" end can be connected to the different voltages that are selected from respectively in a plurality of pre-defined voltage and maybe can be connected to an internal node in system.Yet the principle of teachings of the present invention also is equally applicable to this class situation.
Equally, there is the required switch of a plurality of systems (except switch 150) in system, but do not show in figure.These switches are controlled by a plurality of clock signal, think sample phase (Φ
1) and transition phase (Φ
2) definition circuit structure (that is, the connection between circuit element).Because implying its existence and thinking that the those skilled in the art will be understood that this structure, so do not demonstrate these switches in accompanying drawing.
It would be apparent to someone skilled in the art that, can make numerous variations and modification to apparatus and method of the present invention in the situation that do not break away from teaching of the present invention.Therefore, this paper discloses and is interpreted as only being limited to the scope of patent application and defining.
Claims (13)
1. the switch capacitor circuit of device based on the comparison, this based on the comparison the switch capacitor circuit of device comprise:
One comparison circuit, this comparison circuit has the error that a side-play amount produces to reduce circuit delay;
One charge pump, couple this comparison circuit, and this charge pump is controlled by the output of this comparison circuit; And
A plurality of capacitors, include one first capacitor and one second capacitor;
Wherein, in a sample phase, utilize this first capacitor to sample an input voltage; In a transition phase, the electric charge that utilizes this charge pump will be stored on this first capacitor is transferred to this second capacitor.
2. the switch capacitor circuit of device based on the comparison according to claim 1, wherein in this transition phase, this comparison circuit by the voltage on this first capacitor and this based on the comparison in the switch capacitor circuit of device the voltage of a Nodes compare.
3. the switch capacitor circuit of device based on the comparison according to claim 1, wherein, this comparison circuit includes a comparator and an add circuit.
4. the switch capacitor circuit of device based on the comparison according to claim 1, wherein shift while having completed when electric charge being detected, by this charge pump forbidding.
5. the switch capacitor circuit of device based on the comparison according to claim 1, wherein this side-play amount is a predetermined value.
6. the switch capacitor circuit of device based on the comparison according to claim 1, wherein, between an alignment epoch, this side-play amount is determined by a calibration circuit.
7. the switch capacitor circuit of device based on the comparison according to claim 6, wherein this calibration circuit comprises one second comparison circuit and a controller calibration, and this controller calibration is controlled this side-play amount according to the judgement of this second comparison circuit.
8. the switch capacitor circuit of device based on the comparison according to claim 7, wherein this second comparison circuit by this based on the comparison the switch capacitor circuit of device an output with this based on the comparison the voltage of the node in the switch capacitor circuit of device compare.
9. a method that causes error for reducing a switching capacitor circuit, wherein this switch capacitor circuit includes a comparator, a charge pump of being controlled by the output of this comparator and a plurality of capacitor, and the method comprises:
To introducing the error that a side-play amount produces to reduce circuit delay in this comparator;
During sample phase, provide one first capacitor to be sampled an input voltage; And
During transition phase, utilize this charge pump so that the electric charge be stored on this first capacitor is transferred to one second capacitor.
10. method according to claim 9, the step shifted at electric charge also includes:
Utilize this comparator to compare the voltage of the voltage on this first capacitor and the node in this switch capacitor circuit, to export the output of this comparator.
11. method according to claim 9, wherein this side-play amount is a predetermined value.
12. method according to claim 9 also comprises:
Between an alignment epoch, utilize a calibration circuit to produce this side-play amount.
13. method according to claim 12, the step that wherein produces this side-play amount includes:
The voltage of a node in one of this switch capacitor circuit output and this switch capacitor circuit relatively, to produce a comparison signal; And
To export this side-play amount, wherein, when this comparison signal is first value, increase this side-play amount according to this comparison signal; When this comparison signal is second value, reduce this side-play amount.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/551,244 US7450048B2 (en) | 2006-03-29 | 2006-10-20 | Error reducing comparator-based switch capacitor circuit and method thereof |
| US11/551,244 | 2006-10-20 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101174836A CN101174836A (en) | 2008-05-07 |
| CN101174836B true CN101174836B (en) | 2013-12-04 |
Family
ID=39423143
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007101819956A Active CN101174836B (en) | 2006-10-20 | 2007-10-22 | Error reducing comparator-based switch capacitor circuit and method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN101174836B (en) |
| TW (1) | TW200826502A (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108466485B (en) * | 2018-03-21 | 2019-05-17 | 嘉兴学院 | Near field electrohydrodynamic spray printing operating voltage has the control method of short delaing time |
-
2007
- 2007-10-19 TW TW96139179A patent/TW200826502A/en unknown
- 2007-10-22 CN CN2007101819956A patent/CN101174836B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| TWI349440B (en) | 2011-09-21 |
| TW200826502A (en) | 2008-06-16 |
| CN101174836A (en) | 2008-05-07 |
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