CN101174591A - Production method for memory device and semiconductor element - Google Patents
Production method for memory device and semiconductor element Download PDFInfo
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- CN101174591A CN101174591A CNA2006101433072A CN200610143307A CN101174591A CN 101174591 A CN101174591 A CN 101174591A CN A2006101433072 A CNA2006101433072 A CN A2006101433072A CN 200610143307 A CN200610143307 A CN 200610143307A CN 101174591 A CN101174591 A CN 101174591A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 59
- 239000004065 semiconductor Substances 0.000 title claims description 33
- 238000000034 method Methods 0.000 claims abstract description 122
- 239000002210 silicon-based material Substances 0.000 claims abstract description 68
- 238000002955 isolation Methods 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 238000007667 floating Methods 0.000 claims abstract description 15
- 239000004020 conductor Substances 0.000 claims abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 42
- 229910052710 silicon Inorganic materials 0.000 claims description 42
- 239000010703 silicon Substances 0.000 claims description 42
- 238000010276 construction Methods 0.000 claims description 25
- 239000000463 material Substances 0.000 claims description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 24
- 229920005591 polysilicon Polymers 0.000 claims description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 10
- 238000000059 patterning Methods 0.000 claims description 10
- 229910000077 silane Inorganic materials 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- 238000005229 chemical vapour deposition Methods 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- SVXHDONHRAZOCP-UHFFFAOYSA-N ethane;silicon Chemical compound [Si].CC SVXHDONHRAZOCP-UHFFFAOYSA-N 0.000 claims description 5
- POXCVKMBBFNXLZ-UHFFFAOYSA-N propane;silicon Chemical compound [Si].CCC POXCVKMBBFNXLZ-UHFFFAOYSA-N 0.000 claims description 5
- 238000000407 epitaxy Methods 0.000 claims description 4
- 230000008569 process Effects 0.000 abstract description 12
- 239000000126 substance Substances 0.000 description 12
- 239000013078 crystal Substances 0.000 description 10
- 230000000694 effects Effects 0.000 description 10
- 238000007517 polishing process Methods 0.000 description 8
- 230000008878 coupling Effects 0.000 description 6
- 238000010168 coupling process Methods 0.000 description 6
- 238000005859 coupling reaction Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 238000005498 polishing Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 3
- 239000012774 insulation material Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000001413 cellular effect Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
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Abstract
The invention discloses a manufacturing method for memory elements, which comprises the following steps: first, a tunnel dielectric layer, a first silicon material layer and a mask layer are formed on a substrate in order; second, a plurality of grooves are formed on the substrate and filled with a plurality of isolation structures; third, the mask layer is removed to expose the first silicon material layer; fourth, a second silicon material layer is formed on the first silicon material layer via the selective growth process for fill in the gaps among the isolation structures; fifth, part of the isolation structures are removed to make the surface of the first silicon material layer lower than that of the second silicon material layer; then, an inter-gate dielectric layer is formed on the substrate, on which a conductor layer is formed in turn; finally, patterns are arranged on the conductor layer to form a control gate; at the same time, the first and the second silicon material layers are also patternized to form a floating gate.
Description
Technical field
The present invention relates to a kind of semiconductor element, and be particularly related to a kind of manufacture method of memory and the manufacture method of semiconductor element.
Background technology
Flash element can repeat the characteristic of actions such as data deposit in, read and wipe because of it, and deposits the advantage that still renews after the data outage in, so it is adopted by personal computer and electronic equipment widely.
Typical flash element is a stacked gate structure, is to make floating grid and control grid with doped polycrystalline silicon.Floating grid is in quick condition, does not have any circuit and is connected with it.Floating grid and control gate interpolar are to be separated by with dielectric layer between grid.Floating grid and substrate are to be separated by with tunnel dielectric layer.The control grid then is connected with word line.
Figure 1A to Fig. 1 D is the manufacturing process generalized section that existing memory is shown.At first, please refer to Figure 1A, be divided into memory cell district 102 and periphery circuit region 104 in the substrate 100.Cambium layer tunnel dielectric layer 106, polysilicon layer 108, mask layer 110 and patterning photoresist layer (not shown) successively in substrate 100 then.
Then, please refer to Figure 1B, is etching mask with the patterning photoresist layer, and memory cell district in substrate 100 102 forms a plurality of groove 112a and 114a respectively with periphery circuit region 104, groove 112a distribution comparatively dense wherein, and groove 114a distributes looser.Then, fill insulant in groove 112a and 114a is to form isolation structure 112b and 114b respectively.
Then, please refer to Fig. 1 C, remove the photoresist layer and the mask layer 110 of patterning.
Then, please refer to Fig. 1 D, form the polysilicon layer (not shown), be covered in substrate 100 and isolation structure 112b and 114b.Then, this polysilicon layer of planarization, the mode of using is multi crystal silicon chemical mechanical polishing process (poly CMP), respectively in memory cell district 102 and periphery circuit region 104 form polysilicon layer 116a and 116b.Because the material removal rate of multi crystal silicon chemical mechanical polishing process is relevant with the density of the size of pattern and pattern on the wafer actually.Therefore, when carrying out the multi crystal silicon chemical mechanical polishing process, the situation of excessive polishing is caused in the zone that pattern density is low on the wafer (periphery circuit region 104) easily, and causes the recessed phenomenon of polysilicon layer in the zone, and this is so-called saucer effect (dishing effect).So, the thickness t 1 of formed polysilicon layer 116a and the thickness t 2 of polysilicon layer 116b, the two in uneven thickness causes the surface of entire wafer not good.
Furthermore, the above-mentioned not good problem of wafer flatness that causes because of the multi crystal silicon chemical mechanical polishing process is very big to the usefulness influence of memory component.And in follow-up technology, also in uneven thickness because of polysilicon layer easily, the photoetching or the etch process that cause forming behind the grid structure have problems, and influence the reliability of technology.
Summary of the invention
In view of this, purpose of the present invention is exactly that a kind of manufacture method of memory is being provided, to improve the problem of the in uneven thickness and saucer effect of the polysilicon layer that uses the multi crystal silicon chemical mechanical polishing process to be caused in the existing planarization process.
A further object of the present invention provides a kind of manufacture method of semiconductor element, to improve the problem of the in uneven thickness and saucer effect of the polysilicon layer that uses the multi crystal silicon chemical mechanical polishing process to be caused in the existing planarization process.
The present invention proposes a kind of manufacture method of memory, and the method for example is that substrate is provided earlier, and in substrate, form tunnel dielectric layer successively, first silicon material layer and mask layer.Afterwards, patterned mask layer, first silicon material layer, tunnel dielectric layer and substrate, and in substrate, form a plurality of grooves.Then, form a plurality of isolation structures and fill up groove.Then, remove mask layer to expose first silicon material layer.Next, carry out the selective silicon growth technique, form second silicon material layer on first silicon material layer, second silicon material layer fills up the gap between the isolation structure.Subsequently, remove the part isolation structure, make the isolation structure surface be lower than the second silicon material layer surface.Afterwards, forming between grid dielectric layer in the substrate and on dielectric layer between grid, forming conductor layer, and patterning conductor layer is to form control grid, patterning second silicon material layer and first silicon material layer to form a plurality of floating grids.
According to the manufacture method of the described memory of the preferred embodiments of the present invention, above-mentioned selective silicon growth technique for example is to use silane gas as reacting gas.
According to the manufacture method of the described memory of the preferred embodiments of the present invention, above-mentioned silane gas further comprises silicomethane, silicon ethane or silicon propane.
According to the manufacture method of the described memory of the preferred embodiments of the present invention, above-mentioned selective silicon growth technique with this mask layer as the silicon growth stop layer.
According to the manufacture method of the described memory of the preferred embodiments of the present invention, above-mentioned selective silicon growth technique further comprises epitaxy technique.
According to the manufacture method of the described memory of the preferred embodiments of the present invention, the material of above-mentioned first silicon material layer for example is to mix or unadulterated monocrystalline silicon, doping or unadulterated polysilicon.The material of above-mentioned second silicon material layer for example is to mix or unadulterated monocrystalline silicon, doping or unadulterated polysilicon.
According to the manufacture method of the described memory of the preferred embodiments of the present invention, the formation method of above-mentioned first silicon material layer comprises chemical vapour deposition technique.
According to the manufacture method of the described memory of the preferred embodiments of the present invention, the material of aforementioned mask layer for example is a silicon nitride.
According to the manufacture method of the described memory of the preferred embodiments of the present invention, the material of above-mentioned tunnel dielectric layer for example is a silica.
According to the manufacture method of the described memory of the preferred embodiments of the present invention, the material of dielectric layer comprises silicon oxide/silicon nitride/silicon oxide between above-mentioned grid.
According to the manufacture method of the described memory of the preferred embodiments of the present invention, the formation method of dielectric layer comprises chemical vapour deposition technique between above-mentioned grid.
Memory manufacturing of the present invention is to adopt the selective silicon growth technique to form silicon material layer, and can avoid the problem of and saucer effect in uneven thickness because of the use floating grid that CMP (Chemical Mechanical Polishing) process caused.
In addition, remove the part isolation structure electric capacity contact area between the control gate utmost point and floating grid is increased, therefore also can promote coupling coefficient (gate coupling ratios) between the grid of memory, and then make the operating voltage of element reduce.
The present invention proposes a kind of manufacture method of semiconductor element, and the method for example is that substrate is provided earlier, and substrate has groove compact district and groove puffs.In the substrate of groove compact district, form a plurality of first groove isolation constructions, and in the volume substrate of groove puffs, form a plurality of second groove isolation constructions simultaneously, and form first silicon material layer and mask layer successively between first groove isolation construction and the gap between second groove isolation construction.Then, remove mask layer, expose the first Si semiconductor surface.Subsequently, carry out the selective silicon growth technique, form second silicon material layer on first silicon material layer, second silicon material layer fills up between first groove isolation construction and the gap between second groove isolation construction.
According to the manufacture method of the described semiconductor element of the preferred embodiments of the present invention, the material of aforementioned mask layer for example is a silicon nitride.
According to the manufacture method of the described semiconductor element of the preferred embodiments of the present invention, further be included between this substrate and this mask layer and form bed course.
According to the manufacture method of the described semiconductor element of the preferred embodiments of the present invention, the material of above-mentioned bed course comprises silica.
According to the manufacture method of the described semiconductor element of the preferred embodiments of the present invention, above-mentioned groove compact district and groove puffs comprise memory cell district and periphery circuit region respectively.
According to the manufacture method of the described semiconductor element of the preferred embodiments of the present invention, above-mentioned selective silicon growth technique for example is to use silane gas as reacting gas.
According to the manufacture method of the described semiconductor element of the preferred embodiments of the present invention, above-mentioned silane gas further comprises silicomethane, silicon ethane or silicon propane.
According to the manufacture method of the described semiconductor element of the preferred embodiments of the present invention, above-mentioned selective silicon growth technique with this mask layer as the silicon growth stop layer.
According to the manufacture method of the described semiconductor element of the preferred embodiments of the present invention, above-mentioned selective silicon growth technique further comprises epitaxy technique.
According to the manufacture method of the described semiconductor element of the preferred embodiments of the present invention, the material of above-mentioned first silicon material layer for example is to mix or unadulterated monocrystalline silicon, doping or unadulterated polysilicon.The material of above-mentioned second silicon material layer for example is to mix or unadulterated monocrystalline silicon, doping or unadulterated polysilicon.
According to the manufacture method of the described semiconductor element of the preferred embodiments of the present invention, the formation method of above-mentioned first silicon material layer comprises chemical vapour deposition technique.
The present invention is because of adopting the selective silicon growth technique, therefore can avoid the problem of the in uneven thickness and saucer effect of the polysilicon layer of the groove compact district that caused because of the multi crystal silicon chemical mechanical polishing process and groove puffs.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Figure 1A to Fig. 1 D illustrates existing memory and makes generalized section.
Fig. 2 A to Fig. 2 F is the generalized section that forms the method for control grid and floating grid according to the shown selective silicon growth technique of the embodiment of the invention.
Description of reference numerals
100,200: substrate 102,202: memory cell district
104,204: periphery circuit region 106,206: tunnel dielectric layer
108,116a, 116b: polysilicon layer 110,210: mask layer
112a, 114a, 212a, 214a: groove 112b, 114b, 212b, 214b: isolation structure
216: the second silicon material layers of 208: the first silicon material layers
218: dielectric layer 220 between grid: conductor layer
222: control grid 224: floating grid
Embodiment
Fig. 2 A to Fig. 2 F is the flow process generalized section that a kind of memory manufacturing of the preferred embodiment of the present invention is shown.
At first, please refer to Fig. 2 A, substrate 200 is provided, this substrate for example is a silicon base.Have groove compact district and groove puffs in the substrate 200.Be to be memory cell district 202 in the present embodiment with the groove compact district, the groove puffs be periphery circuit region 204 as an illustration.Yet the present invention is defined in this.In substrate 200, form tunnel dielectric layer 206, first silicon material layer 208 and mask layer 210 then successively.The material of tunnel dielectric layer 206 for example is a silica.The material of first silicon material layer 208 for example is to mix or unadulterated monocrystalline silicon, doping or unadulterated polysilicon, and its formation method for example is a chemical vapour deposition technique.The material of mask layer 210 for example is a silicon nitride, and its formation method for example is a chemical vapour deposition technique.
Then, please refer to Fig. 2 B, after mask layer 210 forms, carry out photoetching and etch process to remove part mask layer 210.Then, mask layer 210 with reservation is an etching mask, etching first silicon material layer 208, tunnel dielectric layer 206 and substrate 200 partly are to form groove 212a respectively and form groove 214a in the substrate 200 of periphery circuit region 204 in the substrate 200 in memory cell district 202.Then, carry out chemical vapor deposition method, to form the insulation material layer (not shown), this insulation material layer fills up groove 212a and 214a.The material of insulating material for example is a silica.Remove groove 212a and groove 214a insulation material layer in addition afterwards, can in the substrate 200 in memory cell district 202, form a plurality of groove isolation construction 212b, and in the substrate 200 of periphery circuit region 204, form a plurality of groove isolation construction 214b simultaneously.Wherein, the pattern density of the groove isolation construction 212b in memory cell district 202 is greater than the pattern density of the groove isolation construction 214b of periphery circuit region 204.
Then, please refer to Fig. 2 C, remove mask layer 210, until exposing first silicon material layer, 208 surfaces.The method that removes mask layer 210 for example is to carry out wet etch process to remove this mask layer.
Subsequently, please refer to Fig. 2 D, on first silicon material layer 208, form second silicon material layer 216, with the gap between the groove isolation construction 214b of the groove isolation construction 212b that fills up memory cell district 202 and periphery circuit region 204.The material of second silicon material layer 216 for example is to mix or unadulterated monocrystalline silicon, doping or unadulterated polysilicon.The formation method of second silicon material layer 216 comprises the selective silicon growth technique.The formation method of second silicon material layer 216 for example is the selective epitaxial method.Epitaxial silicon will optionally be grown in the surface with silicon, and the growth after epitaxial silicon will have with its under the same crystal lattice orientation (crystal orientation) of silicon materials (first silicon material layer 208).The selective silicon growth technique comprises and uses silane gas as reacting gas, and is the silicon growth stop layer with mask layer 210.Silane gas for example is silicomethane, silicon ethane or silicon propane.
Then, remove the groove isolation construction 212b of partial memory cellular zone 202 and the groove isolation construction 214b of part periphery circuit region 204, make its surface be lower than second Si semiconductor, 216 surfaces.The method that removes the groove isolation construction 214b of the groove isolation construction 212b of partial memory cellular zone 202 and part periphery circuit region 204 for example is to carry out etch process to remove these groove isolation constructions.
Then, please refer to Fig. 2 E, forming dielectric layer 218 between grid in this substrate.The material of dielectric layer 218 for example is a silicon oxide/silicon nitride/silicon oxide between grid.The formation method of dielectric layer 218 for example is to form end silicon oxide layer with thermal oxidation method earlier between these grid, then, utilizes chemical vapour deposition technique to form silicon nitride layer again, forms the top silicon oxide layer thereafter again on silicon nitride layer.Afterwards, on dielectric layer between grid 218, form conductor layer 220.
Afterwards, please refer to Fig. 2 F, this conductor layer 220 of patterning to be forming control grid 222, and patterning second silicon material layer 216 and first silicon material layer 208 are to form a plurality of floating grids 224.The follow-up technology of finishing memory is known by technical staff of the prior art, does not repeat them here.
In the manufacture method of memory of the present invention, owing to adopt the selective silicon growth technique to form second silicon material layer 216, and need not be through the planarization of multi crystal silicon chemical mechanical polishing process, therefore can not produce the existing polysilicon layer phenomenon with the saucer effect in uneven thickness.
And, remove the part groove isolation construction, make the surface of groove isolation construction be lower than second silicon material layer, 116 surfaces, the electric capacity contact area of 224 of the control gate utmost point 222 and floating grids is increased, therefore also can promote coupling coefficient (gate coupling ratios) between the grid of memory, and then make the operating voltage of element reduce.
In addition, in the above-described embodiments, the groove compact district is to be that example is done explanation with the memory cell district, and the groove puffs are to be that example is done explanation with the periphery circuit region.Certainly, groove compact district and groove puffs also can be periphery circuit region or memory cell district simultaneously.And, method of the present invention also can be applied in the technology of other semiconductor elements, by adopting the selective silicon growth technique to form the silicon material layer that fills up between the groove, can avoid the problem of the in uneven thickness and saucer effect of the silicon material layer of the groove compact district that causes because of CMP (Chemical Mechanical Polishing) process and groove puffs.
In sum, the manufacture method of memory of the present invention is to adopt the selective silicon growth technique to form silicon material layer, and can avoid the problem of and saucer effect in uneven thickness because of the use floating grid that CMP (Chemical Mechanical Polishing) process caused.
And, remove the part isolation structure electric capacity contact area between the control gate utmost point and floating grid is increased, therefore also can promote coupling coefficient (gate coupling ratios) between the grid of memory, and then make the operating voltage of element reduce.
The manufacture method of semiconductor element of the present invention, adopt the selective silicon growth technique to form the silicon material layer that fills up between the groove, therefore can avoid the problem of the in uneven thickness and saucer effect of the silicon material layer of the groove compact district that causes because of CMP (Chemical Mechanical Polishing) process and groove puffs.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; those skilled in the art without departing from the spirit and scope of the present invention, when can doing a little change and retouching, so protection scope of the present invention is when with being as the criterion that claim was defined.
Claims (23)
1. the manufacture method of a memory comprises:
Substrate is provided;
In this substrate, form tunnel dielectric layer, first silicon material layer and mask layer successively;
This mask layer of patterning, this first silicon material layer, this tunnel dielectric layer and this substrate, and in this substrate, form a plurality of grooves;
Form a plurality of isolation structures and fill up this a plurality of grooves;
Remove this mask layer to expose this first silicon material layer;
Carry out the selective silicon growth technique, form second silicon material layer on this first silicon material layer, this second silicon material layer fills up the gap between these a plurality of isolation structures;
Remove these a plurality of isolation structures of part, make this a plurality of isolation structures surface be lower than this second silicon material layer surface;
Forming dielectric layer between grid in this substrate;
Forming conductor layer on the dielectric layer between these grid; And
This conductor layer of patterning to be forming the control grid, and this second silicon material layer of patterning and this first silicon material layer are to form a plurality of floating grids.
2. the manufacture method of memory as claimed in claim 1, wherein this selective silicon growth technique comprises and uses silane gas as reacting gas.
3. the manufacture method of memory as claimed in claim 2, wherein silane gas comprises silicomethane, silicon ethane or silicon propane.
4. the manufacture method of memory as claimed in claim 1, wherein this selective silicon growth technique with this mask layer as the silicon growth stop layer.
5. the manufacture method of memory as claimed in claim 1, wherein this selective silicon growth technique comprises epitaxy technique.
6. the manufacture method of memory as claimed in claim 1, wherein the material of this second silicon material layer comprises and mixing or unadulterated monocrystalline silicon, doping or unadulterated polysilicon.
7. the manufacture method of memory as claimed in claim 1, wherein the material of this first silicon material layer comprises and mixing or unadulterated monocrystalline silicon, doping or unadulterated polysilicon.
8. the manufacture method of memory as claimed in claim 1, wherein the formation method of this first silicon material layer comprises chemical vapour deposition technique.
9. the manufacture method of memory as claimed in claim 1, wherein the material of this mask layer comprises silicon nitride.
10. the manufacture method of memory as claimed in claim 1, wherein the material of this tunnel dielectric layer comprises silica.
11. the manufacture method of memory as claimed in claim 1, wherein the material of dielectric layer comprises silicon oxide/silicon nitride/silicon oxide between these grid.
12. the manufacture method of a semiconductor element comprises:
Substrate is provided, and this substrate has groove compact district and groove puffs;
In the substrate of this groove compact district, form a plurality of first groove isolation constructions, and in the substrate of these groove puffs, form a plurality of second groove isolation constructions simultaneously, and form first silicon material layer and mask layer successively between these a plurality of first groove isolation constructions and the gap between these a plurality of second groove isolation constructions;
Remove this mask layer, expose this first Si semiconductor surface; And
Carry out the selective silicon growth technique, form second silicon material layer on this first silicon material layer, this second silicon material layer fills up between these a plurality of first groove isolation constructions and the gap between these a plurality of second groove isolation constructions.
13. the manufacture method of semiconductor element as claimed in claim 12, wherein the material of this mask layer comprises silicon nitride.
14. the manufacture method of semiconductor element as claimed in claim 12 further is included between this substrate and this mask layer and forms bed course.
15. the manufacture method of semiconductor element as claimed in claim 12, wherein the material of this bed course comprises silica.
16. the manufacture method of semiconductor element as claimed in claim 12, wherein this groove compact district and this groove puffs comprise memory cell district and periphery circuit region respectively.
17. the manufacture method of semiconductor element as claimed in claim 12, wherein this selective silicon growth technique comprises that the use silane gas is as reacting gas.
18. the manufacture method of semiconductor element as claimed in claim 17, wherein silane gas comprises silicomethane, silicon ethane or silicon propane.
19. the manufacture method of semiconductor element as claimed in claim 12, wherein this selective silicon growth technique with this mask layer as the silicon growth stop layer.
20. the manufacture method of semiconductor element as claimed in claim 12, wherein this selective silicon growth technique comprises epitaxy technique.
21. the manufacture method of semiconductor element as claimed in claim 12, wherein the material of this second silicon material layer comprises doping or unadulterated monocrystalline silicon, doping or unadulterated polysilicon.
22. the manufacture method of semiconductor element as claimed in claim 12, wherein the material of this first silicon material layer comprises doping or unadulterated monocrystalline silicon, doping or unadulterated polysilicon.
23. the manufacture method of semiconductor element as claimed in claim 12, wherein the formation method of this first silicon material layer comprises chemical vapour deposition technique.
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| CNB2006101433072A CN100481398C (en) | 2006-11-03 | 2006-11-03 | Production methods for memory and semiconductor element |
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| CNB2006101433072A CN100481398C (en) | 2006-11-03 | 2006-11-03 | Production methods for memory and semiconductor element |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102142400A (en) * | 2009-12-30 | 2011-08-03 | 海力士半导体有限公司 | Nonvolatile memory device and method of manufacturing the same |
| CN109659275A (en) * | 2017-10-10 | 2019-04-19 | 联华电子股份有限公司 | The production method of dynamic random access memory |
-
2006
- 2006-11-03 CN CNB2006101433072A patent/CN100481398C/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102142400A (en) * | 2009-12-30 | 2011-08-03 | 海力士半导体有限公司 | Nonvolatile memory device and method of manufacturing the same |
| CN109659275A (en) * | 2017-10-10 | 2019-04-19 | 联华电子股份有限公司 | The production method of dynamic random access memory |
| CN109659275B (en) * | 2017-10-10 | 2020-11-03 | 联华电子股份有限公司 | Method for manufacturing dynamic random access memory |
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| CN100481398C (en) | 2009-04-22 |
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