CN101165851A - Method for preventing charge generation of high voltage component machining process - Google Patents
Method for preventing charge generation of high voltage component machining process Download PDFInfo
- Publication number
- CN101165851A CN101165851A CNA2006101171671A CN200610117167A CN101165851A CN 101165851 A CN101165851 A CN 101165851A CN A2006101171671 A CNA2006101171671 A CN A2006101171671A CN 200610117167 A CN200610117167 A CN 200610117167A CN 101165851 A CN101165851 A CN 101165851A
- Authority
- CN
- China
- Prior art keywords
- high voltage
- machining process
- voltage component
- electric charge
- component machining
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Drying Of Semiconductors (AREA)
Abstract
The method comprises: after the etching of passivation layer is completed, firstly using ultraviolet radiation to dry it, and then making the polyimide coating for it.
Description
Technical field
The present invention relates to a kind of method of manufacturing technology of semiconductor integrated circuit, particularly relate to a kind of method that prevents to produce in the high voltage component machining process electric charge.
Background technology
A trap that concentration is very light all can be arranged in present high tension apparatus, so also can be very light in the concentration of channel surface.If in manufacturing process, produce a large amount of electric charges, can cause the high tension apparatus surface to produce much movably electronics, thereby cause element leakage excessive, serious meeting makes component failure.
The reason that produces electric charge is relevant with VUV (vacuum extreme ultraviolet line) effect.This VUV can exist in some HDP usually, in the equipment of DRY... (high-density plasma chemical gas deposition and dry etching equipment).Can obtain the energy of the photon of different wave length according to E=hc/ λ, the photon energy of this VUV is about 30ev.And general SiO
2Energy gap at 8-9ev, so general VUV in metal etch can be easy to pass obstacle (comprising polysilicon), its energy is enough to make the electronics in the gate oxidation silicon (Gate Oxide) to obtain the required energy of enough jump energy gaps.So just make and also brought the hole of equal number with it simultaneously by many free electrons much in the gate oxidation silicon.These holes with positive charge can induce movably free electron in the channel surface of device.The effect of free carrier when these a large amount of free electrons have just served as the raceway groove transoid forms surperficial channel current.The consequence of bringing makes the device cut-in voltage low excessively exactly, even formation exhausts pipe.Make the electric leakage very big (10 of isolation structure in addition
-6A), thus can not play the effective isolation effect.
Existing N
2, H
2Method for annealing is difficult to eliminate electric charge to influence that high tension apparatus produced.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of method that prevents to produce in the high voltage component machining process electric charge, eliminates the influence of electric charge to high tension apparatus.
For solving the problems of the technologies described above, the method that prevents to produce in the high voltage component machining process electric charge of the present invention is to adopt following technical scheme to realize, adds the ultraviolet ray oven dry after the passivation layer etching.
Adopt method of the present invention, after the passivation layer etching, add the ultraviolet ray oven dry, improved because the existence of electric charge can cause device surface raceway groove transoid, and cut-in voltage is low excessively, even formed the phenomenon that exhausts pipe, improved the stability of device under condition of high voltage.Compare with original traditional handicraft, device property is normal, and stability is high.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 is the existing process method flow chart;
Fig. 2 is a method process chart of the present invention.
Embodiment
At the influence of electric charge to high tension apparatus, the present invention adopts the method for ultraviolet ray oven dry to discharge electric charge, promptly compound by the electric charge that is produced in the multiple making technology (utilize ultraviolet energy to neutralize in the oxide layer produced a large amount of electron hole pairs) with the ultraviolet light energy, thus reach the effect that discharges electric charge.
Shown in Fig. 1,2, ultraviolet oven dry of the present invention is carried out after need being placed on back road metal connecting line and passivation layer etching, especially best results after the passivation layer etching.Then carry out polyimide coating technology then.And existing process method is directly carried out polyimide coating technology after the passivation layer etching.
When adopting method of the present invention specifically to implement, need time and the temperature selecting ultraviolet drying unit, carry out the ultraviolet ray oven dry.
The ultraviolet ray drying unit can be selected two kinds of equipment that varying strength can be provided for use:
Equipment one wavelength: 220-320nm intensity:＞650nw/cm
2Or
Equipment two wavelength: 254nm intensity: 25nw/cm
2
The ultraviolet ray drying time: need to select suitable drying time, employing equipment one was generally 80 seconds to 10 minutes; Employing equipment two was generally 12 to 60 minutes.
The ultraviolet ray bake out temperature: employing equipment one is 180 ℃; Employing equipment two is 25 ℃ of normal temperature.
In a specific embodiment of the present invention, adopt and after the passivation layer etching, carry out the ultraviolet ray oven dry, ultraviolet drying time is: equipment one: 80 second or equipment two: 30 minutes.
Claims (5)
1. method that prevents from the high voltage component machining process to produce electric charge, comprise passivation layer etching and polyimide coating processing step, it is characterized in that: after the passivation layer etch step is finished, carry out the ultraviolet ray oven dry earlier, and then carry out the polyimide coating processing step.
2. the method that prevents from the high voltage component machining process to produce electric charge according to claim 1 is characterized in that: the device of described ultraviolet ray oven dry is,
Wavelength: 220-320nm intensity:＞650nw/cm
2Drying time is 80 seconds to 10 minutes; Temperature is: 180 ℃.
3. the method that prevents from the high voltage component machining process to produce electric charge according to claim 1 is characterized in that: the device of described ultraviolet ray oven dry is,
Wavelength: wavelength: 254nm intensity: 25nw/cm
2Drying time is 12 to 60 minutes; Temperature is: 25 ℃.
4. the method that prevents to produce in the high voltage component machining process electric charge according to claim 2, it is characterized in that: described drying time is: 80 seconds.
5. the method that prevents to produce in the high voltage component machining process electric charge according to claim 2, it is characterized in that: described drying time is: 30 minutes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101171671A CN100501916C (en) | 2006-10-16 | 2006-10-16 | Method for preventing charge generation of high voltage component machining process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101171671A CN100501916C (en) | 2006-10-16 | 2006-10-16 | Method for preventing charge generation of high voltage component machining process |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009101184158A Division CN101504912B (en) | 2006-10-16 | 2006-10-16 | Method for preventing electric charge generation in high voltage device manufacturing process |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101165851A true CN101165851A (en) | 2008-04-23 |
| CN100501916C CN100501916C (en) | 2009-06-17 |
Family
ID=39334476
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006101171671A Active CN100501916C (en) | 2006-10-16 | 2006-10-16 | Method for preventing charge generation of high voltage component machining process |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100501916C (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102044481A (en) * | 2009-10-19 | 2011-05-04 | 中芯国际集成电路制造(上海)有限公司 | Method for preventing corrosion of tungsten plug |
| CN102543686A (en) * | 2012-02-10 | 2012-07-04 | 上海先进半导体制造股份有限公司 | Process for photoetching polyimide on semiconductor substrate |
| CN104347367A (en) * | 2013-07-30 | 2015-02-11 | 无锡华润上华半导体有限公司 | Method for improving large electric leakage during gate-oxide breakdown |
| CN113628972A (en) * | 2021-07-07 | 2021-11-09 | 华虹半导体(无锡)有限公司 | Manufacturing method of groove type MOS device |
-
2006
- 2006-10-16 CN CNB2006101171671A patent/CN100501916C/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102044481A (en) * | 2009-10-19 | 2011-05-04 | 中芯国际集成电路制造(上海)有限公司 | Method for preventing corrosion of tungsten plug |
| CN102543686A (en) * | 2012-02-10 | 2012-07-04 | 上海先进半导体制造股份有限公司 | Process for photoetching polyimide on semiconductor substrate |
| CN104347367A (en) * | 2013-07-30 | 2015-02-11 | 无锡华润上华半导体有限公司 | Method for improving large electric leakage during gate-oxide breakdown |
| CN113628972A (en) * | 2021-07-07 | 2021-11-09 | 华虹半导体(无锡)有限公司 | Manufacturing method of groove type MOS device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100501916C (en) | 2009-06-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101459116B (en) | Shallow groove isolation construction manufacturing method | |
| CN101419923B (en) | Manufacturing method for lead wire welding mat | |
| KR20100009654A (en) | Semiconductor device manufacturing method | |
| CN100501916C (en) | Method for preventing charge generation of high voltage component machining process | |
| CN100401502C (en) | Semiconductor element with uv protection layer and method producing the same | |
| JP2013073950A (en) | Semiconductor device manufacturing method | |
| TWI819802B (en) | Formation of bottom isolation | |
| JP2007096002A (en) | Method of manufacturing semiconductor device, and semiconductor device | |
| JP5520834B2 (en) | Method for forming passivation film and method for manufacturing solar cell element | |
| CN102054745A (en) | Method for forming contact hole | |
| US20050255669A1 (en) | Semiconductor device including isolation trench and method for fabricating the same | |
| CN101504912B (en) | Method for preventing electric charge generation in high voltage device manufacturing process | |
| CN101592873A (en) | Remove the photoresist layer method | |
| US20080261397A1 (en) | Method for Manufacturing Semiconductor Device | |
| CN105895649B (en) | A method of reducing CIS device noises by changing SAB film quality | |
| CN101740498B (en) | Semiconductor device with contact etching stop layer and forming method thereof | |
| KR20060037822A (en) | Apparatus for high density plasma chemical vapor deposition and method for fabricating semiconductor device using the same | |
| JPH0917867A (en) | Method of forming contact part in semiconductor device | |
| JP5565314B2 (en) | Semiconductor device manufacturing method and manufacturing apparatus thereof | |
| CN101645409A (en) | Bonding pad forming method | |
| CN107919267B (en) | Semiconductor device and manufacturing method thereof | |
| JP2005183919A (en) | Method of manufacturing semiconductor device | |
| JP5699803B2 (en) | Manufacturing method of semiconductor device | |
| KR20020002732A (en) | Method for forming an insulation layer of a semiconductor device | |
| KR20050115508A (en) | Method of forming a damascene pattern |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20131219 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20131219 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |