CN101145897A - A method and system for reducing transmission clock line based on communication hardware platform - Google Patents
A method and system for reducing transmission clock line based on communication hardware platform Download PDFInfo
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- CN101145897A CN101145897A CNA2007101240750A CN200710124075A CN101145897A CN 101145897 A CN101145897 A CN 101145897A CN A2007101240750 A CNA2007101240750 A CN A2007101240750A CN 200710124075 A CN200710124075 A CN 200710124075A CN 101145897 A CN101145897 A CN 101145897A
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Abstract
The invention discloses a method for reducing a clock-transmission line based on a communication hardware platform. The method includes the following steps: A. a sending end of a system clock modulates the system clock signals of various types into the serial data signals in an encoding way, and transmits the serial data signals via the clock bus to a receiving end of the system clock on each interface unit board; B. the receiving end of the system clock decodes the serial data signals and recovers the system clock signals. The invention transmits a plurality of clock signals only by using a few lines, meeting the system demand for the adaptability and enhancing the reliability of the system.
Description
Technical field
The present invention relates to computer realm, be specifically related to transmission and the method for reseptance and the system thereof of clock signal in the compunication hardware platform.
Background technology
Clock signal of system in the communication hardware platform generally has: 8K frame signal, 16.384M clock signal; Sometimes increase according to service needed: PP2S synchronizing signal, cycle 1.25ms clock signal, 19.44M clock signal etc.The method of traditional system clock transmission clock is to adopt independently that holding wire transmits each road clock signal, and along with development of technology, the integrated level and the reliability requirement of system are more and more higher, and shortcoming is also more and more obvious:
(1) line of the inner backboard needs of system module is many, in present communication hardware platform, the backboard wiring quantity that is used for the transfer system clock signal by standard code has only three groups, and this mode can not transmit all clock signals, will have influence on the service application scope of system like this.
(2) quantity of the clock cable that needs during the transmission clock signal between system module is many.
(3), often adopt direct-current coupling or directly connection because in the clock signal that transmits, the frequency of frame signal is lower, generally should not adopt the mode of AC coupled to transmit.If adopt clock cable directly to be connected intermodule transmission clock signal, have the danger of swell damage interface chip.
(4) traditional clock transfer approach takies a clock passage owing to every kind of clock signal, and extensibility is relatively poor, the bad increase that adapts to clock signal kinds in future.
The tranmission techniques of clock in the existing systems, the data rate before having adapted to is lower, the also not too high situation of integrated level of system.But reach system in the future now, because the raising of integrated level, the line of distributing to clock signal of system can be not abundant as before, and also can increase more multi-clock signal as required, so requirement and adaptive requirement to the reliability of system are also more and more higher, thereby find out, existing systems needs a kind of new method come the transmission clock signal, requirement transmits the clock signal that multiple systems needs on limited clock line, and satisfies the reliability requirement of system.
Summary of the invention
The object of the present invention is to provide a kind of method and system thereof that reduces transmission clock line based on communication hardware platform, it is according to the transmission characteristics of present communication hardware platform clock signal, difficulty in conjunction with present available circuit technology proposes a kind of method and system new, rationally reliable system clock transmission, satisfies system reliability and adaptive requirement.
The present invention adopts following technical method to realize.
Method of the present invention is carried out according to following steps:
A, system clock transmitting terminal adopt the mode of coding that the sorts of systems clock signal is modulated into serial data signal, and this serial data signal is delivered to system clock receiving terminal on each interface unit plate by clock bus;
B, described system clock receiving terminal are by decoding to described serial data signal, and reduction sorts of systems clock signal.
Wherein, described coded system adopts the coded system of 4B/5B.
Wherein, among the described step B, the clock signal on the described system clock receiving terminal elder generation recovered clock bus utilizes this clock signal to read described serial data signal on this clock bus again.
Wherein, in the described steps A, described system clock transmitting terminal sends to described system clock receiving terminal by a clock bus with described serial data signal, and sends to described system clock receiving terminal by the clock signal that another clock bus will be used to read serial data signal.
Wherein, among the described step B, the described clock signal that the utilization of described system clock receiving terminal receives is used to read serial data signal reads the described serial data signal on the clock bus.
Adopt in the system for carrying out said process, described system comprises: system clock plate and at least two interface unit plates that carry out business data processing of being used to produce the sorts of systems clock signal, link to each other by clock bus between system clock plate and the interface unit plate, the system clock transmitting terminal of described system clock plate comprises the data tranmitting data register; System clock transmitting terminal on the described system clock plate also comprises: all kinds of clock signal coding circuits, be used for the sorts of systems clock signal that described system clock plate produces is encoded, and obtain code signal; And a data bit shift circuit, be used for beat according to described data tranmitting data register, described code signal is converted to serial data outputs on the clock bus;
System clock receiving terminal on the described interface unit plate comprises: a data receiver circuit is used to read serial data on the described clock bus; One decode clock restore circuit is used for described serial data is decoded, and is reduced to the sorts of systems clock signal, and clock provides circuit, is used to described data receiver circuit and decoding clock recovery circuitry that the work clock signal is provided.
Wherein, described system adopts a clock bus to transmit to contain the serial data of sorts of systems clock signal, and it is clock recovery circuitry that described clock provides circuit, is used to recover a clock signal on the described clock bus as described work clock signal.
Wherein, described system adopts two clock bus, and wherein, first clock bus is used to transmit the serial data that described data bit shift circuit is exported; The second clock bus is used to transmit described data tranmitting data register.
Wherein, it is the clock receiving circuit that described clock provides circuit, is used to receive the clock signal on the described second clock bus, and with the work clock signal of this clock signal as described data receiver circuit and described decode clock restore circuit.
Wherein, the coded system of described all kinds of clock signal coding circuits adopts the coded system of 4B/5B.
Compare with existing clock load mode, have following advantage:
First point, the present invention transmit multiple clock signal with line seldom, have satisfied system for adaptive demand.Second point, the present invention just can adopt the mode of AC coupled to transmit these clock signals owing to the data-signal that low-frequency clock signal is modulated into higher rate, use existing isolation AC coupled technology, can improve the reliability of system.Thirdly, the present invention adopts different coded systems can transmit different clock signals, can transmit the clock sync signal of multiple lower frequency on line, extensibility is better.
Description of drawings
Fig. 1 is an intelligent hardware platform system dorsulum clock bus schematic diagram in the prior art;
Fig. 2 needs the clock load mode schematic diagram of recovered clock circuit for receiving terminal of the present invention;
Fig. 3 is the not clock load mode schematic diagram of recovered clock signal of receiving terminal of the present invention;
Fig. 4 is transmission, reception and the encoding and decoding principle schematic of clock signal of the present invention.
Embodiment
Below will describe each preferred embodiment of the present invention in detail.
In the present invention, mainly be to adopt the mode of coding that the frame signal of low frequency or synchronizing signal are modulated into the data-signal of higher rate, thereby utilize a spot of data/address bus just can transmit the sorts of systems clock signal, and be suitable for the AC coupled transmission.About the frame signal of low frequency or the coding of synchronizing clock signals a variety of selection modes are arranged,, require to adopt the less coded system of DC component to be fit to AC coupled, for example coded system of 4B/5B if clock signal adopts the AC coupled load mode.
The present invention can carry out according to following two steps according to above-mentioned thought:
A, system clock transmitting terminal adopt the mode of coding that the sorts of systems clock signal is modulated into serial data signal, and this serial data signal is delivered to system clock receiving terminal on each interface unit plate by clock bus;
B, described system clock receiving terminal are by decoding to described serial data signal, and reduction sorts of systems clock signal.
According to above-mentioned steps, the working method of above-mentioned receiving terminal can be divided into dual mode:
(1) receiving terminal needs the mode of recovered clock circuit: the clock signal on the said system clock receiving terminal elder generation recovered clock bus, utilize this clock signal to read described serial data signal on this bus again.Recover the frame signal or the synchronizing signal of lower frequency by data decode, principle as shown in Figure 2.The advantage of this mode is exactly that all clock signals all transmit on a circuit, distribution.
(2) said system clock transmitting terminal need be delivered to described system clock receiving terminal with described serial data signal by a clock bus, and delivers to described system clock receiving terminal by the clock signal that another clock bus will be used to read serial data signal.At this moment, the described clock signal that the direct utilization of system clock receiving terminal receives reads the described serial data signal on the clock bus, is restored the frame signal or the synchronizing signal of lower frequency then by the decode clock restore circuit, and principle as shown in Figure 3.The advantage of this mode is exactly that circuit is simple, more easily realize, and cost is low.
The improvement of adopting said method that existing system has been done below with reference to description of drawings the present invention.
As shown in Figure 1, in the system communication hardware platform commonly used at present, system mainly comprises system clock plate 100 and at least two the interface unit plates 120 that carry out business data processing that are used to produce the sorts of systems clock signal, links to each other by clock bus between system clock plate 100 and the interface unit plate 120; Usually system can be equipped with three data/address buss, be System Backplane clock bus CLK1, System Backplane clock bus CLK2, the System Backplane clock bus CLK3 among Fig. 1, wherein CLK3 has arranged to receive as clock board the passage of the clock signal of other veneers, the system clock plate can only be on CLK1 and CLK2 each veneer needs in the dissemination system clock signal.When concrete enforcement is of the present invention, because there are above-mentioned two kinds of working methods in the system clock receiving terminal on the interface unit plate 120, so also there are following two kinds in particular circuit configurations:
(1) corresponding with above-mentioned first kind of mode, as shown in Figure 2, the system clock transmitting terminal of the present invention on system clock plate 100 increased all kinds of clock signal coding circuits 101 and a data bit shift circuit 102; Wherein, all kinds of clock signal coding circuits 101 sorts of systems clock signal that is used for system clock plate 100 is produced (CLOCK1, CLOCK2, CLOCK3 ..., CLOCKn) encode, obtain code signal; Data bit shift circuit 102 is used for the beat according to data tranmitting data register 103 (this clock signal can be held a concurrent post by arbitrary clock of system clock transmitting terminal), described code signal is converted to serial data outputs on the clock bus, this moment, system can adopt a clock bus to transmit the serial data that contains the sorts of systems clock signal; Because above-mentioned design, the system clock receiving terminal on the described interface unit plate 120 need comprise: a data receiver circuit 121, and it is used to read serial data on the described clock bus; An and decode clock restore circuit 122, it is used for described serial data is decoded, and be reduced to the sorts of systems clock signal (CLOCK1, CLOCK2, CLOCK3 ..., CLOCKn), also need simultaneously to comprise: a clock restore circuit 120 provides circuit as clock, it is used to recover the clock signal on the described clock bus, and this clock signal provides the work clock signal for data receiver circuit 121 and described decode clock restore circuit 122.
(2) corresponding with the above-mentioned second way, as shown in Figure 3, the system clock transmitting terminal of the present invention on system clock plate 100 increased all kinds of clock signal coding circuits 101 and a data bit shift circuit 102, wherein, the sorts of systems clock signal that all kinds of clock signal coding circuits 101 are used for system clock plate 100 is produced (CLOCK1, CLOCK2, CLOCK3 ..., CLOCKn) encode, obtain code signal; Data bit shift circuit 102 is used for the beat according to data tranmitting data register 103, described code signal is converted to serial data to output on the clock bus, during this kind situation, system can adopt two clock bus: first clock bus is used to transmit the serial data that described data bit shift circuit 102 is exported; The second clock bus is used to transmit described data tranmitting data register.Based on above-mentioned design, the system clock receiving terminal on the described interface unit plate 120 need comprise: a data receiver circuit 121, and it is used to read serial data on the described clock bus; An and decode clock restore circuit 122, it is used for described serial data is decoded, and be reduced to the sorts of systems clock signal (CLOCK1, CLOCK2, CLOCK3 ..., CLOCKn), also need simultaneously to comprise: a clock receiving circuit 124 provides circuit as clock, it is used to receive the clock signal on the described second clock bus, and this clock signal provides the work clock signal for described data receiver circuit 121 and described decode clock restore circuit 122.The coded system of above-mentioned all kinds of clock signal coding circuits 101 also can adopt the coded system of 4B/5B, how to design and can decide according to coded system as for its internal circuit, belongs to prior art, does not explain at this.Above-mentioned data receiver circuit 121 can adopt shift register to realize.
Below referring to Fig. 4, illustrate that the present invention adopts system shown in Figure 3 to following clock signal: the principle that 8K frame signal, 16.384M clock signal, PP2S synchronizing signal, cycle 1.25ms clock signal transmit.System of the present invention adopts the CLK2 passage to transmit the 16.384M clock signal, and it is as data tranmitting data register 103, for other structure members provide the work clock signal.CLK1 is as a data coding pass, the 8K frame signal except that the 16.384M clock signal, PP2S synchronizing signal, cycle 1.25ms clock signal that system needs have been modulated, because clock signal adopts AC coupled, and need the clock of coding to have only 3 kinds, the present invention can adopt the coded system of the 4B/5B that easily realizes.The characteristics of this 4 tunnel clock signal are: 8K frame signal and 16.384M clock signal are synchronous, and PP2S synchronizing signal and cycle 1.25ms clock signal are synchronous.According to these characteristics, the present invention realizes that the 8K frame signal adopts solid size, priority encoding and decoding.PP2S synchronizing signal and cycle 1.25ms clock signal adopt three sign indicating numbers to link up by the order of determining synchronously and encode, reason is that they may be overlapping by the 8K frame signal, the coding of part can be covered by the coding of 8K frame signal, so the sign indicating number position that coding adopts will be grown.
Simultaneously directly use serial data on the 16.384M clock signal receive clock bus at the system clock receiving terminal, and decode according to the coded system that scheme defines and to recover other clock signals, the 16.384M clock signal can directly be distributed to system and uses simultaneously.The trailing edge that is referenced as owing to the system requirements clock, not too restriction of pulsewidth to clock, so the system clock transmitting terminal all sends bell idles in other parts of CLK1 passage, bell idles also be from 16 sign indicating numbers of 4B/5B, choose definite, as shown in Figure 4, A district expression 8K frame signal coding, here Bian Ma priority is the highest, can cover the coding of other clock signal; The coding of B district expression PP2s synchronizing signal, owing to may be covered by 8K frame signal coding, so code length will be noted situation about covering than the length of 8K frame signal coding during decoding; The coding of the 1.25ms of C district indication cycle clock signal, this signal in system with the PP2s synchronizing signal be along the alignment, so the coverage condition except noting being encoded during this signal decoding by the 8K frame signal, be also noted that the volume with the PP2s synchronizing signal is " or " logical relation; D district expression bell idles, the coding of other parts of encoding except A, B, C in the data.In the system of the present invention, the clock signal distribution between each circuit module adopts cable to connect, and AC coupled had so both reduced number of cable, had improved the reliability of system again.
In sum, in present intelligent hardware platform system, employing the inventive method usefulness clock distribution channel for distribution system has seldom realized the transmission to the multipath clock signal, thereby has satisfied the demand of system.
Be understandable that above-mentioned explanation is comparatively concrete, can not therefore think the restriction to scope of patent protection of the present invention, scope of patent protection of the present invention should be as the criterion with claims.
Claims (10)
1. one kind is reduced the method for transmission clock line based on communication hardware platform, it is characterized in that described method is carried out according to following steps:
A, system clock transmitting terminal adopt the mode of coding that the sorts of systems clock signal is modulated into serial data signal, and this serial data signal is delivered to system clock receiving terminal on each interface unit plate by clock bus;
B, described system clock receiving terminal are by decoding to described serial data signal, and reduction sorts of systems clock signal.
2. method according to claim 1 is characterized in that, described coded system adopts the coded system of 4B/5B.
3. method according to claim 1 is characterized in that, among the described step B, the clock signal on the described system clock receiving terminal elder generation recovered clock bus utilizes this clock signal to read described serial data signal on this clock bus again.
4. method according to claim 1, it is characterized in that, in the described steps A, described system clock transmitting terminal sends to described system clock receiving terminal by a clock bus with described serial data signal, and sends to described system clock receiving terminal by the clock signal that another clock bus will be used to read serial data signal.
5. method according to claim 4 is characterized in that, among the described step B, the described clock signal that is used to read serial data signal that the utilization of described system clock receiving terminal receives reads the described serial data signal on the clock bus.
6. system that reduces transmission clock line based on communication hardware platform, described system comprises: system clock plate and at least two interface unit plates that carry out business data processing of being used to produce the sorts of systems clock signal, link to each other by clock bus between system clock plate and the interface unit plate, the system clock transmitting terminal of described system clock plate comprises the data tranmitting data register;
It is characterized in that the system clock transmitting terminal on the described system clock plate also comprises:
One all kinds of clock signal coding circuits are used for the sorts of systems clock signal that described system clock plate produces is encoded, and obtain code signal; And
One data bit shift circuit is used for the beat according to described data tranmitting data register, described code signal is converted to serial data outputs on the clock bus;
System clock receiving terminal on the described interface unit plate comprises:
One data receiver circuit is used to read serial data on the described clock bus;
One decode clock restore circuit is used for described serial data is decoded, and is reduced to the sorts of systems clock signal; And
Clock provides circuit, is used to described data receiver circuit and decoding clock recovery circuitry that the work clock signal is provided.
7. system according to claim 6, it is characterized in that, described system adopts a clock bus to transmit the serial data that contains the sorts of systems clock signal, and, it is clock recovery circuitry that described clock provides circuit, is used to recover a clock signal on the described clock bus as described work clock signal.
8. system according to claim 6 is characterized in that, described system adopts two clock bus, and wherein, first clock bus is used to transmit the serial data that described data bit shift circuit is exported; The second clock bus is used to transmit described data tranmitting data register.
9. system according to claim 8, it is characterized in that, it is the clock receiving circuit that described clock provides circuit, is used to receive the clock signal on the described second clock bus, and with the work clock signal of this clock signal as described data receiver circuit and described decode clock restore circuit.
10. system according to claim 6 is characterized in that, the coded system of described all kinds of clock signal coding circuits adopts the coded system of 4B/5B.
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| CN2007101240750A CN101145897B (en) | 2007-10-19 | 2007-10-19 | A method and system for reducing transmission clock line based on communication hardware platform |
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| CN2007101240750A CN101145897B (en) | 2007-10-19 | 2007-10-19 | A method and system for reducing transmission clock line based on communication hardware platform |
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| CN101145897B CN101145897B (en) | 2010-12-29 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109547310A (en) * | 2018-11-05 | 2019-03-29 | 中国航空工业集团公司西安飞机设计研究所 | A kind of modular bus data method of reseptance |
| CN114124283A (en) * | 2021-12-01 | 2022-03-01 | 岱昆半导体(上海)有限公司 | Single-wire communication method based on frequency coding |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9230505B2 (en) * | 2013-02-25 | 2016-01-05 | Lattice Semiconductor Corporation | Apparatus, system and method for providing clock and data signaling |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1204906A (en) * | 1997-05-09 | 1999-01-13 | 阿尔卡塔尔-阿尔斯托姆通用电气公司 | Apparatus for reducing jitter in asynchronous apparatus |
| US6748027B1 (en) * | 2000-08-10 | 2004-06-08 | Intel Corporation | CMI signal timing recovery |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109547310A (en) * | 2018-11-05 | 2019-03-29 | 中国航空工业集团公司西安飞机设计研究所 | A kind of modular bus data method of reseptance |
| CN109547310B (en) * | 2018-11-05 | 2021-06-01 | 中国航空工业集团公司西安飞机设计研究所 | Modular bus data receiving method |
| CN114124283A (en) * | 2021-12-01 | 2022-03-01 | 岱昆半导体(上海)有限公司 | Single-wire communication method based on frequency coding |
| CN114124283B (en) * | 2021-12-01 | 2023-11-03 | 岱昆半导体(上海)有限公司 | Single-wire communication method based on frequency coding |
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