CN101145876A - Time slot configuration method and time slot configuration device - Google Patents
Time slot configuration method and time slot configuration device Download PDFInfo
- Publication number
- CN101145876A CN101145876A CNA2007101300338A CN200710130033A CN101145876A CN 101145876 A CN101145876 A CN 101145876A CN A2007101300338 A CNA2007101300338 A CN A2007101300338A CN 200710130033 A CN200710130033 A CN 200710130033A CN 101145876 A CN101145876 A CN 101145876A
- Authority
- CN
- China
- Prior art keywords
- time slot
- preliminary treatment
- buffer memory
- time
- logic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Time-Division Multiplex Systems (AREA)
Abstract
The invention provides a timeslot configuration method and a device, wherein the method includes that a timeslot preprocessing buffer is set; one or more logical timeslot number is distributed according to the minimal cross particle size; after a timeslot preprocessing command is received, the timeslot preprocessing is performed, and the result from the timeslot preprocessing is stored in the timeslot preprocessing buffer; and after a timeslot configuration command is received, according to the sent-down logical timeslot number and the cross rank, the register address and the register value that are needed to be set are taken out from the timeslot preprocessing buffer and the register value is written into the register address. Therefore, with the invention, the efficiency of timeslot configuration can be obviously improved, and for highly integrated miniature equipment, the effect is particularly significant.
Description
Technical field
The present invention relates to the optical transmission field, more specifically, relate to a kind of time-slot configuring method and time slot configuration device.
Background technology
Described a kind of technology that is used to reduce business switching time in No. 200610149674.3 patent, the shortcoming of this technology is the calculating of configuration register and read-write operation are not proposed the method optimized.
Along with the development of Science and Technology, SDH equipment is more and more come into the terminal use, and people have proposed new requirement to its aspect such as volume, cost, reliability.Volume is little, light weight, price is low, business interface is abundant, adaptive capacity to environment is strong integrated miniaturization SDH equipment are arisen at the historic moment in this case.
Because the height of compact apparatus is integrated, be divided into the time slot configuration of several veneers originally, also be integrated in now on the veneer and realized.And compact apparatus has been mentioned certain height to cost, and the cost of CPU is also included the category of consideration naturally in.Based on top these two factors, time slot processing institute's time spent has just increased.Like this in business configuration with when switching, business is joined logical and to recover the needed time also elongated.
And for communication equipment, the consequence that present communication disruption causes also becomes more and more serious.The survivability of communication network has become crucial design to be considered, also becomes the important focus of the competition between market access environment lower network network operator or the service supplier.
Thereby, be badly in need of a kind of scheme and improve time slot configuration efficient.
Summary of the invention
In view of the problems of the prior art, the invention provides a kind of time-slot configuring method and time slot configuration device, be used to improve time slot configuration efficient.
The invention provides a kind of time-slot configuring method, it can may further comprise the steps: time slot preliminary treatment buffer memory is set; Distribute one or more logic timeslot numbers according to minimum cross granularity; After receiving time slot preliminary treatment order, carry out the time slot preliminary treatment, and the preliminary treatment result is stored in the time slot preliminary treatment buffer memory; And after receiving the time slot configuration order, according to the logic timeslot number that issues and the rank of intersecting, from time slot preliminary treatment buffer memory, take out register address and the register value that needs setting, and register value is write register address.
Wherein, above-mentioned time slot preliminary treatment comprises: the corresponding relation of logic time slot and physical slot by time is kept in the preliminary treatment buffer memory; And, calculate the register address and the register value of the required setting of different intersection rank respectively, and be stored in respectively in the time slot preliminary treatment buffer memory corresponding to each logic timeslot number.
According to the present invention, register address and register value are that index stores is in time slot preliminary treatment buffer memory with the logic timeslot number.Cross granularity is space division cross granularity or time-division cross granularity.
The present invention also provides a kind of time slot configuration device, and it can comprise: buffer memory is provided with the unit, is used to be provided with time slot preliminary treatment buffer memory; Allocation units are used for distributing one or more logic timeslot numbers according to minimum cross granularity; The time slot pretreatment unit is used for carrying out the time slot preliminary treatment after receiving time slot preliminary treatment order, and the preliminary treatment result is stored in the time slot preliminary treatment buffer memory; And dispensing unit, be used for after receiving the time slot configuration order, according to the logic timeslot number that issues and the rank of intersecting, from time slot preliminary treatment buffer memory, take out register address and the register value that needs setting, and register value is write register address.
Wherein, above-mentioned time slot pretreatment unit comprises: preserve module, be used for the corresponding relation of logic time slot and physical slot by time is kept at the preliminary treatment buffer memory; And computing module, be used for corresponding to each logic timeslot number, calculate the register address and the register value of the required setting of different intersection rank respectively, and be stored in respectively in the time slot preliminary treatment buffer memory.
Register address and register value are that index stores is in time slot preliminary treatment buffer memory with the logic timeslot number.Cross granularity is space division cross granularity or time-division cross granularity.
Thereby, adopting the present invention, the efficient of time slot configuration can obviously improve.Particularly at the compact apparatus of high integration, effect is particularly evident.
Other features and advantages of the present invention will be set forth in the following description, and, partly from specification, become apparent, perhaps understand by implementing the present invention.Purpose of the present invention and other advantages can realize and obtain by specifically noted structure in the specification of being write, claims and accompanying drawing.
Description of drawings
Accompanying drawing is used to provide further understanding of the present invention, and constitutes the part of specification, is used from explanation the present invention with embodiments of the invention one, is not construed as limiting the invention.In the accompanying drawings:
Fig. 1 is the flow chart according to time-slot configuring method of the present invention;
Fig. 2 is the flow chart according to the software processes of the embodiment of the invention;
The schematic diagram of the time slot configuration structure among Fig. 3 the present invention; And
Fig. 4 is the block diagram according to time slot configuration device of the present invention.
Embodiment
Below in conjunction with accompanying drawing the preferred embodiments of the present invention are described, should be appreciated that preferred embodiment described herein only is used for description and interpretation the present invention, and be not used in qualification the present invention.
Fig. 1 is the flow chart according to time-slot configuring method of the present invention.As shown in Figure 1, this time-slot configuring method may further comprise the steps:
S102 is provided with time slot preliminary treatment buffer memory;
S104 distributes one or more logic timeslot numbers according to minimum cross granularity;
S106 after receiving time slot preliminary treatment order, carries out the time slot preliminary treatment, and the preliminary treatment result is stored in the time slot preliminary treatment buffer memory; And
S108, receive the time slot configuration order after, according to the logic timeslot number that issues and the rank of intersecting, taking out from time slot preliminary treatment buffer memory needs the register address and the register value that are provided with, and register value is write register address.
Wherein, above-mentioned time slot preliminary treatment comprises: the corresponding relation of logic time slot and physical slot by time is kept in the preliminary treatment buffer memory; And, calculate the register address and the register value of the required setting of different intersection rank respectively, and be stored in respectively in the time slot preliminary treatment buffer memory corresponding to each logic timeslot number.
Register address and register value are that index stores is in time slot preliminary treatment buffer memory with the logic timeslot number.Cross granularity is space division cross granularity or time-division cross granularity.
Fig. 2 is the flow chart according to the software processes of the embodiment of the invention, and the schematic diagram of the time slot configuration structure among Fig. 3 the present invention.Describe the detailed process of time slot processing method of the present invention in detail below with reference to Fig. 2 and Fig. 3.
As shown in Figure 3, comprised A, B, C, the operation of four modules of D in the cross time-slot configuration.Dispose a time slot and will operate the register of these four modules simultaneously.
As shown in Figure 2, specifically may further comprise the steps:
S202 opens up time slot preliminary treatment buffer memory;
S204, TU11 comes the assignment logic timeslot number according to minimum intersection particle;
S206, receive time slot preliminary treatment name, the corresponding relation of logic time slot and physical slot by time is saved in the preliminary treatment buffer memory. each logic timeslot number is calculated different intersection rank (AU4, AU3, TU3 respectively, TU12, TU11 etc.) A, B, C, all register addresss and the register value of the required setting of D module, being saved in the logic timeslot number is in the preliminary treatment buffer memory of index;
S208, whether the preliminary treatment time slot sets up.If then carried out for the 5th step, otherwise carried out for the 3rd step;
S210, the receiving slot configuration order. according to the logic timeslot number that issues and the rank of intersecting, from time slot preliminary treatment buffer memory, take out A, B, C, all register addresss of the required setting of D module and register value also are provided with respectively; And
S212, time slot configuration finishes, and returns S210.
Fig. 4 is the block diagram according to time slot configuration device 400 of the present invention.As shown in Figure 4, this time slot configuration device comprises: buffer memory is provided with unit 402, is used to be provided with time slot preliminary treatment buffer memory; Allocation units 404 are used for distributing one or more logic timeslot numbers according to minimum cross granularity; Time slot pretreatment unit 406 is used for carrying out the time slot preliminary treatment after receiving time slot preliminary treatment order, and the preliminary treatment result is stored in the time slot preliminary treatment buffer memory; And dispensing unit 408, be used for after receiving the time slot configuration order, according to the logic timeslot number that issues and the rank of intersecting, from time slot preliminary treatment buffer memory, take out register address and the register value that needs setting, and register value is write register address.
Wherein, above-mentioned time slot pretreatment unit 406 comprises: preserve module, be used for the corresponding relation of logic time slot and physical slot by time is kept at the preliminary treatment buffer memory; And computing module, be used for corresponding to each logic timeslot number, calculate the register address and the register value of the required setting of different intersection rank respectively, and be stored in respectively in the time slot preliminary treatment buffer memory.
Register address and register value are that index stores is in time slot preliminary treatment buffer memory with the logic timeslot number.Cross granularity is space division cross granularity or time-division cross granularity.
In sum, by the present invention, can obviously improve the efficient of time slot configuration, especially in highly integrated mini-plant, effect is especially obvious.
Be the preferred embodiments of the present invention only below, be not limited to the present invention, for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1. a time-slot configuring method is characterized in that, may further comprise the steps:
Time slot preliminary treatment buffer memory is set;
Distribute one or more logic timeslot numbers according to minimum cross granularity;
After receiving time slot preliminary treatment order, carry out the time slot preliminary treatment, and the preliminary treatment result is stored in the described time slot preliminary treatment buffer memory; And
After receiving the time slot configuration order, according to the logic timeslot number that issues and the rank of intersecting, from described time slot preliminary treatment buffer memory, take out register address and the register value that needs setting, and described register value is write described register address.
2. time-slot configuring method according to claim 1 is characterized in that, described time slot preliminary treatment comprises:
The corresponding relation of logic time slot and physical slot by time is kept in the described preliminary treatment buffer memory; And
Corresponding to each described logic timeslot number, calculate the described register address and the described register value of the required setting of different intersection rank respectively, and be stored in respectively in the described time slot preliminary treatment buffer memory.
3. time-slot configuring method according to claim 2 is characterized in that, described register address and described register value are that index stores is in described time slot preliminary treatment buffer memory with described logic timeslot number.
4. according to each described time-slot configuring method in the claim 1 to 3, it is characterized in that described cross granularity is space division cross granularity or time-division cross granularity.
5. a time slot configuration device is characterized in that, comprising:
Buffer memory is provided with the unit, is used to be provided with time slot preliminary treatment buffer memory;
Allocation units are used for distributing one or more logic timeslot numbers according to minimum cross granularity;
The time slot pretreatment unit is used for carrying out the time slot preliminary treatment after receiving time slot preliminary treatment order, and the preliminary treatment result is stored in the described time slot preliminary treatment buffer memory; And
Dispensing unit, be used for after receiving the time slot configuration order, according to the logic timeslot number that issues and the rank of intersecting, from described time slot preliminary treatment buffer memory, take out register address and the register value that needs setting, and described register value is write described register address.
6. time slot configuration device according to claim 5 is characterized in that, described time slot pretreatment unit comprises:
Preserve module, be used for the corresponding relation of logic time slot and physical slot by time is kept at described preliminary treatment buffer memory; And
Computing module is used for corresponding to each described logic timeslot number, calculates the described register address and the described register value of the required setting of different intersection rank respectively, and is stored in respectively in the described time slot preliminary treatment buffer memory.
7. time slot configuration device according to claim 6 is characterized in that, described register address and described register value are that index stores is in described time slot preliminary treatment buffer memory with described logic timeslot number.
8. according to each described time slot configuration device in the claim 5 to 7, it is characterized in that described cross granularity is space division cross granularity or time-division cross granularity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101300338A CN101145876B (en) | 2007-07-25 | 2007-07-25 | Time slot configuration method and time slot configuration device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101300338A CN101145876B (en) | 2007-07-25 | 2007-07-25 | Time slot configuration method and time slot configuration device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101145876A true CN101145876A (en) | 2008-03-19 |
| CN101145876B CN101145876B (en) | 2011-05-25 |
Family
ID=39208194
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007101300338A Expired - Fee Related CN101145876B (en) | 2007-07-25 | 2007-07-25 | Time slot configuration method and time slot configuration device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101145876B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010142169A1 (en) * | 2009-06-09 | 2010-12-16 | 中兴通讯股份有限公司 | Method and apparatus for fast passing through services for synchronous digital hierarchy device |
| CN106487711A (en) * | 2016-10-13 | 2017-03-08 | 福建星海通信科技有限公司 | A kind of method of caching dynamically distributes and system |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1112782C (en) * | 2000-02-01 | 2003-06-25 | 深圳市中兴通讯股份有限公司 | Very-large-scale cross connector in synchronous digital transmission device |
| CN1317842C (en) * | 2003-07-17 | 2007-05-23 | 深圳市中兴通讯股份有限公司 | Super large-scale cross connection device and method used for synchronous digital transmission system |
-
2007
- 2007-07-25 CN CN2007101300338A patent/CN101145876B/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010142169A1 (en) * | 2009-06-09 | 2010-12-16 | 中兴通讯股份有限公司 | Method and apparatus for fast passing through services for synchronous digital hierarchy device |
| CN101577602B (en) * | 2009-06-09 | 2013-02-27 | 中兴通讯股份有限公司 | Method and device of fast SDH device punch- through service |
| US8798079B2 (en) | 2009-06-09 | 2014-08-05 | Zte Corporation | Method and apparatus for fast passing through services for synchronous digital hierarchy device |
| CN106487711A (en) * | 2016-10-13 | 2017-03-08 | 福建星海通信科技有限公司 | A kind of method of caching dynamically distributes and system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101145876B (en) | 2011-05-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102377682B (en) | Queue management method and device based on variable-length packets stored in fixed-size location | |
| CN101848135B (en) | Management method and management device for statistical data of chip | |
| WO2005026876A3 (en) | Shared usage telecommunications billing system and method | |
| EP3166269B1 (en) | Queue management method and apparatus | |
| US20130023207A1 (en) | Wireless Communication User System | |
| CN105260128A (en) | Method for writing data in storage device and storage device | |
| CN101527932A (en) | Method for performing buffer status reporting and communication apparatus thereof | |
| TW200708950A (en) | Memory management method and system | |
| CN109324874A (en) | A kind of virutal machine memory snapshot imports the method, system and device of block device | |
| CN101145876B (en) | Time slot configuration method and time slot configuration device | |
| CN102821045B (en) | Method and device for copying multicast message | |
| CN102508786B (en) | Chip design method for optimizing space utilization rate and chip thereof | |
| CN1561492A (en) | Bus system and bus interface for connection to a bus | |
| CN109040868B (en) | Method and system for ONU (optical network unit) end uplink framing in XGSPON (XGSPON) | |
| CN101594201B (en) | Method for integrally filtering error data in linked queue management structure | |
| CN101650690B (en) | Application method of large-capacity memory card as well as mobile terminal | |
| CN101789840B (en) | Pan-T crossing device and pan-T crossing method | |
| CN104956633A (en) | Optical line terminal, distribution point unit, system and data stream scheduling method | |
| CN102148757B (en) | A kind of multiple nucleus system message distributing method and device | |
| CN109376131A (en) | A kind of log distributed deployment store method, apparatus and system | |
| CN101668234A (en) | Data packet sending method and module | |
| CN105450488B (en) | A kind of data processing method and relevant apparatus | |
| CN101202601B (en) | Method for recovering virtual cascades | |
| CN102497652A (en) | Load balancing method and device for large-flow data of code division multiple access (CDMA) R-P interface | |
| CN208174726U (en) | Data transmission device and intelligent interactive panel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20151118 Address after: 430223 East Lake Wuhan New Technology Development Zone Hua Hua Road, Optics Valley Industrial Park, ZTE building, building No. 3, building Patentee after: WUHAN ZHONGXING SOFTWARE CO., LTD. Address before: 518057 Nanshan District science and Technology Industrial Park, Guangdong high tech Industrial Park, ZTE building Patentee before: ZTE Corporation |
|
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110525 Termination date: 20190725 |