CN101140596A - On-site programmable gate array research table verification method - Google Patents
On-site programmable gate array research table verification method Download PDFInfo
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- CN101140596A CN101140596A CNA200710050260XA CN200710050260A CN101140596A CN 101140596 A CN101140596 A CN 101140596A CN A200710050260X A CNA200710050260X A CN A200710050260XA CN 200710050260 A CN200710050260 A CN 200710050260A CN 101140596 A CN101140596 A CN 101140596A
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Abstract
A search table verification method for in-situ programmable gate arrays, relates to an integrated circuit technology and comprises the following steps: 1) Utilize a software to pre-configure target LUT test vectors and corresponding correct results before storage; 2) The software party automatically creates corresponding configuration files according to LUT test vectors, and transmits the configuration file into FPGA for configuration; the hardware party closes LUT in the test according to the configuration file, but only remains a test target LUT; 3) The software party apply an LUT test vector to FPGA at the hardware party; then, return the results to the software party; the software party performs analysis and comparison for the results; 4) Return to Step 1) to continue testing the next LUT, until all LUTs are test; 5) Create test reports according to all test results. The invention guarantees input and output logic relations one-to-one correlated, and ensures kernel modules inside FPGA working normally. Moreover, speed can be increased. Meanwhile, the invention can considerably increase test efficiency.
Description
Technical field
The present invention relates to integrated circuit technique, particularly the field programmable gate array verification technology.
Background technology
Look-up table (Look-Up-Table) abbreviates LUT as, and LUT is exactly a RAM in essence.Present LUT that use 4 inputs among the FPGA so each LUT can regard a RAM of 16 * 1 that 4 bit address lines are arranged as more.When the user by schematic diagram or HDL language description after logical circuit, PLD/FPGA develops software and understands all possible result of automatic calculation logic circuit, and the result write RAM in advance, like this, signal of every input carries out logical operation and just equals to import an address and table look-up, find out the content of address correspondence, output gets final product then.
Look-up table is a core logic among the FPGA, and actual checking should guarantee that all LUT can both operate as normal in the chip.Can know from this, general only input added limited excitation vector method and can not travel through, output error may occur detecting all results in the LUT.
Summary of the invention
Technical matters to be solved by this invention is, a kind of look-up table (LUT) verification method of field programmable gate array is provided, can be fully, the LUT to FPGA does checking comprehensively efficiently.
The technical scheme that the present invention solve the technical problem employing is that the look-up table of field programmable gate array (LUT) verification method may further comprise the steps:
1) with software goal-selling LUT test vector and corresponding correct result, and storage;
2) software section automatically generates corresponding configuration file according to the LUT test vector, and transmits configuration file and to FPGA it is disposed, and the hardware root is closed the LUT of non-this test according to configuration file, only keeps test target LUT;
3) software section applies the LUT test vector to hardware side FPGA, then the result is turned back to software side, software side's analyses and comparison result,
4) return step 1) and continue the next LUT of test, up to the test of finishing whole LUT;
5) generate test report according to each time test result.
Software side only sets up with hardware side by pci bus and communicates by letter.Described LUT test vector is single LUT test vector.Promptly only to the tested effective test vector of single LUT.
The invention has the beneficial effects as follows, the consideration that the present invention is comprehensive input various situations and verifying one by one, so just can verify LUT reliably, guaranteed input and output logical relation correspondence one by one, guarantee that the nucleus module of FPGA inside is working properly.The present invention has simultaneously abandoned the pattern of traditional " layout line+data line ", adopts pci bus transmission of configuration information and excitation vector, and speed is improved.The present invention simultaneously can finish the test to all wire laying channels automatically, and does not need user intervention, has improved testing efficiency greatly.
The present invention is further illustrated below in conjunction with the drawings and specific embodiments.
Description of drawings
Fig. 1 is an one-piece construction synoptic diagram of the present invention.DUT is user FPGA to be tested.
F1 is the data transmission and the control module of hardware side.
Fig. 2 is a pci bus application synoptic diagram in the present invention.
Embodiment
Referring to Fig. 1.
On-site programmable gate array research table verification method of the present invention may further comprise the steps:
1) with software goal-selling LUT test vector and corresponding correct result, and storage;
2) software section automatically generates corresponding configuration file according to the LUT test vector, and transmits configuration file and to FPGA it is disposed, and the hardware root is closed the LUT of non-this test according to configuration file, only keeps test target LUT;
3) software section applies the LUT test vector to hardware side FPGA, then the result is turned back to software side, and the software root is according to default correct interpretation of result comparison;
4) return step 1) and continue the next LUT of test, up to the test of finishing whole LUT;
5) generate test report according to each time test result.
Software side only sets up with hardware side by pci bus and communicates by letter.
LUT test vector of the present invention is single LUT test vector, promptly only to the effective test vector of single LUT.
Embodiment:
LUT forms the function generator of CLB, and the LUT for four inputs can control 24 addresses, forms 216 kinds of logical functions; In 4000 series, F and G function LUT can also constitute the RAM of 32 * 1 and 16 * 1 dual-ports, and the two kinds of trigger modes in enable level/edge.For the functional test of SRAM, can adopt the resolution chart (TestPattern) of conventional SRAM, but prerequisite is to finish the fault detect of LUT.
LUT is made up of CLB input circuit, address decoding (Address Decoder) and storage unit (Memory Cell), the fault model of CLB input circuit and memory cell failure performance is stack-at-0 and stack-at-1 fault, and the address decoding fault shows as abuse, can't visit and the multiple-unit visit.
LUT is configured to 4 input XOR and XNOR, enter programmable links after four the pin inputs of input end by fpga chip, link LUT as address wire then, write all possible logical consequence among the LUT in advance, export then to corresponding data by address search, combinational logic has just been realized like this.Output and the fault detect that can finish LUT as shown in table 1 of input corresponding relation.Begin to carry out by turn the read/write operation of 1,0 signal from lowest order during the pattern ram test, finish, guarantee the correctness of each function to most significant digit.
Table 1:XOR truth table
| XOR output | Input A | Input B | Input C | Input D |
| ?0 | ?0 | ?0 | ?0 | ?0 |
| ?1 | ?0 | ?0 | ?0 | ?1 |
| ?1 | ?0 | ?0 | ?1 | ?0 |
| ?0 | ?0 | ?0 | ?1 | ?1 |
| ?1 | ?0 | ?1 | ?0 | ?0 |
| ?0 | ?0 | ?1 | ?0 | ?1 |
| ?0 | ?0 | ?1 | ?1 | ?0 |
| ?1 | ?0 | ?1 | ?1 | ?1 |
| ?1 | ?1 | ?0 | ?0 | ?0 |
| ?0 | ?1 | ?0 | ?0 | ?1 |
| ?0 | ?1 | ?0 | ?1 | ?0 |
| ?1 | ?1 | ?0 | ?1 | ?1 |
| ?0 | ?1 | ?1 | ?0 | ?0 |
| ?1 | ?1 | ?1 | ?0 | ?1 |
| ?1 | ?1 | ?1 | ?1 | ?0 |
| ?0 | ?1 | ?1 | ?1 | ?1 |
The hardware components that present embodiment adopts is the FPGA hardware test platform, belongs to prior art.Present embodiment adopts the pci bus communication technology to establish a communications link between software section and FPGA hardware test platform, is used to transmit configuration file and test vector, and this is an innovative point of the present invention.
On 1,000,000 gate leve development boards, by pci bus FPGA2 is carried out download configuration, both can save JTAG and download line, also can improve the speed of download configuration, can also be implemented in systems programming (ISP) in addition.
As shown in Figure 2:
FPGA supports that ppu is configured (being commonly referred to as passive configuration mode) to it, and in pci card, the back is configured it by outside EEROM because FPGA1 powers on, and after the configuration successful, FPGA1 can serve as ppu FPGA2 is configured.Concrete operating process is: after the user selects the configuration file of FPGA2 by the configuration software on the computing machine, configuration software sends configuration order to FPGA2 to FPGA1, the configuration steering logic of FPGA1 inside can require FPGA2 is sent the configuration commencing signal according to the sequential under the FPGA passive configuration mode, if there be not wrong the generation, FPGA2 can send the indicator signal that is ready to dispose to FPGA1, FPGA1 promptly notifies software can begin to have sent configuration data after receiving this signal, the value that software reads configuration file is that unit sends to FPGA1 by pci bus with 32bit, FPGA1 requires to produce the proper configuration clock according to the configuration sequential after receiving configuration data, and will send to FPGA2 after the configuration data serial conversion, so repeatedly, till configuration data all sends, FPGA2 receives that the sram cell to its inside is configured after the series arrangement data, after all sram cell configurations finish, FPGA2 sends configuration to FPGA1 and finishes signal, so far, finished whole layoutprocedure.
FPGA configuration mode based on pci bus possesses multiple advantage than the JTAG configuration mode based on the parallel port: at first, it does not need JTAG specific download line, and this has not only saved system cost but also make system operation easier; Secondly, its configuration speed is faster than parallel port configuration mode, still can not improve about 30 times through the situation speed of optimizing, and this is because the data rate of PCI is far longer than the transmission speed of parallel port; At last, based on the FPGA configuration mode of pci bus, can conveniently realize the ISP function, that is: at system programmable, the configuration file by software Dynamic Selection FPGA in system's operational process is configured FPGA, thereby realizes reconfigurable computing function.
FPGA configuration mode based on pci bus requires have a chips to serve as the Configuration Control Unit of the FPGA that is configured on the development board, because the logic of FPGA1 inside is fixed on the SoC development board, so can serve as the Configuration Control Unit of FPGA2 by FPGA1, therefore do not need to add MCU or CPLD, for realizing this function, FPGA1 only need use several configuration pin relevant with FPGA2 (the Cyclone series of altera corp only needs 5 pins), FPGA1 realizes the resource also considerably less (only needing 110LEs in Altera CycloneFPGA) that Configuration Control Unit consumes, and realizes on the SoC verification platform that as seen the FPGA configuration based on pci bus is very economical.
Claims (3)
1. on-site programmable gate array research table verification method is characterized in that, may further comprise the steps:
1) with software goal-selling LUT test vector and corresponding correct result, and storage;
2) software section automatically generates corresponding configuration file according to the LUT test vector, and transmits configuration file and to FPGA it is disposed, and the hardware root is closed the LUT of non-this test according to configuration file, only keeps test target LUT;
3) software section applies the LUT test vector to hardware side FPGA, then the result is turned back to software side, software side's analyses and comparison result,
4) return step 1) and continue the next LUT of test, up to the test of finishing whole LUT;
5) generate test report according to each time test result.
2. on-site programmable gate array research table verification method as claimed in claim 1 is characterized in that, software side only sets up with hardware side by pci bus and communicates by letter.
3. on-site programmable gate array research table verification method as claimed in claim 1 is characterized in that, described LUT test vector is single LUT test vector.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103294837A (en) * | 2012-02-23 | 2013-09-11 | 安凯(广州)微电子技术有限公司 | Method and system for verifying and debugging integrated circuit |
| CN109444630A (en) * | 2018-11-05 | 2019-03-08 | 西安智多晶微电子有限公司 | FPGA routing cell tests structure and method |
| CN112287632A (en) * | 2020-10-26 | 2021-01-29 | 成都华微电子科技有限公司 | Method for prejudging wiring of integrated circuit |
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2007
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103294837A (en) * | 2012-02-23 | 2013-09-11 | 安凯(广州)微电子技术有限公司 | Method and system for verifying and debugging integrated circuit |
| CN103294837B (en) * | 2012-02-23 | 2016-05-11 | 安凯(广州)微电子技术有限公司 | A kind of verifying and debugging method and system of integrated circuit |
| CN109444630A (en) * | 2018-11-05 | 2019-03-08 | 西安智多晶微电子有限公司 | FPGA routing cell tests structure and method |
| CN109444630B (en) * | 2018-11-05 | 2020-12-01 | 西安智多晶微电子有限公司 | FPGA wiring unit test structure and method |
| CN112287632A (en) * | 2020-10-26 | 2021-01-29 | 成都华微电子科技有限公司 | Method for prejudging wiring of integrated circuit |
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