CN101136334A - Method for manufacturing polycrystalline silicon emitter interface layer - Google Patents
Method for manufacturing polycrystalline silicon emitter interface layer Download PDFInfo
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- CN101136334A CN101136334A CNA2006100305310A CN200610030531A CN101136334A CN 101136334 A CN101136334 A CN 101136334A CN A2006100305310 A CNA2006100305310 A CN A2006100305310A CN 200610030531 A CN200610030531 A CN 200610030531A CN 101136334 A CN101136334 A CN 101136334A
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- polycrystalline silicon
- interface layer
- layer
- silicon emitter
- emitter interface
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Abstract
This invention discloses a method for preparing an interface layer of a polysilicon emitter, which first of all cleans the surface of the silicon chip with a HF-Last wet method to eliminate a natural oxidation layer on the surface of the chip completely, then putting the chip into an UV03 process device to form an interface oxidation layer in a period of time under a certain temperature to process an interface layer of polysilicon emitter of Bipolar or BiCMOS, in which, the temperature is better at 100-300deg.C, the time is 1-10min. and thickness of the oxidation layer of the interface layer is 5-15.
Description
Technical field
The present invention relates to semiconductor fabrication process, relate in particular to a kind of method of making polycrystalline silicon emitter interface layer
Background technology
When making the polysilicon emitter of Bipolar or BiCMOS, need usually between emitter-polysilicon and base, to form the extremely thin interface oxide layer of one deck, so that the increase at double of the current gain of device, can be referring to Fig. 1.Generate interface oxide layer at present and mainly contain following several method:
1, places for a long time at ambient temperature, form natural oxide film.This method time loss is longer, and the oxide-film that generates in natural atmosphere, wherein contains impurity such as more carbon, and not fine and close.
2, use RCA wet method solution that the surface is handled, form oxide layer on the surface.The oxide layer that this method surface forms is not very fine and close, and homogeneity is bad in the silicon chip.
3, utilization rapid thermal treatment (RTP) device carries out oxidation to the surface.This method cost height, and RTP is not easy temperature control at low temperatures.
4, use DRY O
2(plasma surface oxidation processes).This method has the possibility of introducing PLASMA DAMAGE (plasma damage).
5, WET O
3(wet method ozone treatment).The oxide layer that this method surface forms is not very fine and close, and homogeneity is bad in the silicon chip.
Therefore, how to provide a kind of not high to temperature requirement, the processing time is not long, and the polycrystalline silicon emitter interface layer that forms is membranous, and process is still very necessary preferably with the thickness homogeneity.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of method of making polycrystalline silicon emitter interface layer, can solve under low low temperature, forms polycrystalline silicon emitter interface layer fast, and membranous better with the thickness homogeneity.
For solving the problems of the technologies described above, a kind of method of making polycrystalline silicon emitter interface layer of the present invention is at first carried out the HF-Last wet method to silicon chip surface and is cleaned processing, to remove the natural oxidizing layer of silicon chip surface fully; Then silicon chip is put into UV O
3(ultraviolet and ozone) processing unit, at uniform temperature and the interface oxide layer that forms in the time, make the polycrystalline silicon emitter interface layer of Bipolar (bipolar transistor) or BiCMOS (bipolarcomplementary metal-oxide semiconductor bipolar complimentary metal oxide transistor npn npn).Temperature is preferably 100-300 degree centigrade in the above-mentioned technology, and the time is 1-10 minute, and the interface oxidation layer thickness is the 5-15 dust.
The inventive method processing step is very simple, control temperature easily when implementing, and the interface oxidation film of generation is rapid and quality is better, can make the current gain increase at double of device.
Description of drawings
Fig. 1 is a polysilicon emitter interface oxide layer schematic diagram;
Fig. 2 is the UV O that the inventive method is used
3The processing unit schematic diagram;
Fig. 3 is the process flow diagram of the inventive method.
Embodiment
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments.
The inventive method is used UV O
3Make the polycrystalline silicon emitter interface layer of Bipolar or BiCMOS, the UV O of its use
3Processing unit can be referring to Fig. 2.Before making polycrystalline silicon emitter interface layer, need (a kind of last hydrofluoric acid treatment that is in the present invention through HF-Last, rather than the method for washing) wet treatment, the natural oxidizing layer that guarantees the surface are removed fully and to be subjected to hydrogen passivation autoxidation layer growth very slow on the surface; The silicon chip that will need then to handle is put into UV O
3In the processing unit.Tell about the present invention according to a specific embodiment below.Concrete flow chart can be referring to Fig. 3.
Embodiment one:
In this embodiment, at first silicon chip surface is cleaned through the HF-Last wet method and handled, guarantee that the natural oxidizing layer on surface is removed fully, then silicon chip is inserted UV O as shown in Figure 2 by the inventive method
3In the processing unit schematic diagram; Oxygen is introduced UV O as shown in Figure 2
3Processing unit, this UV O
3The ozone generator of processing unit is handled oxygen and is produced ozone, and the mercury lamp of processing unit heats; Temperature is controlled in the processing unit in this embodiment: 150-250 degree centigrade of processing time is 8 minutes; Make the relatively better interface of homogeneous quality of Bipolar polysilicon emitter interface oxide layer by this example, the oxidated layer thickness that generates in this example is 10 dusts.With the polycrystalline silicon emitter interface layer that also can make BiCMOS with quadrat method, and effect is better.
According to embodiment, concrete technological parameter preferably is controlled at following scope in the inventive method, that is: temperature is 100-300 degree centigrade; Processing time is 1 minute-10 minutes; The oxidated layer thickness that generates is the 5-15 dust.
In sum, the present invention proposes a kind of use UV 0
3Device is made the method for polycrystalline silicon emitter interface layer, this method is simple, control easily, the extremely thin interface oxide layer of one deck can formed between emitter-polysilicon and base rapidly under the lower temperature, and the interface oxidation film quality homogeneous that generates has very high value in real technology.
Claims (4)
1. a method of making polycrystalline silicon emitter interface layer is characterized in that, comprising:
Step 1, silicon chip surface is carried out the HF-Last wet treatment, to remove the natural oxidizing layer of silicon chip surface;
Step 2, described silicon chip is put into UV O
3Processing unit at uniform temperature and the interface oxide layer that forms in the time, is made the polycrystalline silicon emitter interface layer of Bipolar or BiCMOS, this UV O
3Processing unit comprises ozone generator and heater.
2. the method for making polycrystalline silicon emitter interface layer according to claim 1 is characterized in that, described temperature is 100-300 degree centigrade, and temperature is controlled by heater, and described heater is a mercury lamp.
3. the method for making polycrystalline silicon emitter interface layer according to claim 1 is characterized in that, the described time is 1-10 minute.
4. the method for making polycrystalline silicon emitter interface layer according to claim 1 is characterized in that, described interface oxidation layer thickness is the 5-15 dust.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006100305310A CN101136334A (en) | 2006-08-29 | 2006-08-29 | Method for manufacturing polycrystalline silicon emitter interface layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006100305310A CN101136334A (en) | 2006-08-29 | 2006-08-29 | Method for manufacturing polycrystalline silicon emitter interface layer |
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| Publication Number | Publication Date |
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| CN101136334A true CN101136334A (en) | 2008-03-05 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2006100305310A Pending CN101136334A (en) | 2006-08-29 | 2006-08-29 | Method for manufacturing polycrystalline silicon emitter interface layer |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102205942A (en) * | 2011-05-13 | 2011-10-05 | 上海集成电路研发中心有限公司 | Manufacturing method of sacrifice layer of MEMS (Micro-electromechanical System) |
| WO2016101361A1 (en) * | 2014-12-24 | 2016-06-30 | 深圳市华星光电技术有限公司 | Method for forming oxide layer on amorphous silicon surface |
| CN110335896A (en) * | 2019-05-09 | 2019-10-15 | 中国电子科技集团公司第二十四研究所 | A kind of production method of the polysilicon emitter structure of adjustable current gain |
-
2006
- 2006-08-29 CN CNA2006100305310A patent/CN101136334A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102205942A (en) * | 2011-05-13 | 2011-10-05 | 上海集成电路研发中心有限公司 | Manufacturing method of sacrifice layer of MEMS (Micro-electromechanical System) |
| CN102205942B (en) * | 2011-05-13 | 2015-11-04 | 上海集成电路研发中心有限公司 | MEMS sacrificial layer structure making process |
| WO2016101361A1 (en) * | 2014-12-24 | 2016-06-30 | 深圳市华星光电技术有限公司 | Method for forming oxide layer on amorphous silicon surface |
| CN110335896A (en) * | 2019-05-09 | 2019-10-15 | 中国电子科技集团公司第二十四研究所 | A kind of production method of the polysilicon emitter structure of adjustable current gain |
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Open date: 20080305 |