CN101128884A - One time programmable latch and method - Google Patents
One time programmable latch and method Download PDFInfo
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- CN101128884A CN101128884A CNA2005800320808A CN200580032080A CN101128884A CN 101128884 A CN101128884 A CN 101128884A CN A2005800320808 A CNA2005800320808 A CN A2005800320808A CN 200580032080 A CN200580032080 A CN 200580032080A CN 101128884 A CN101128884 A CN 101128884A
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Abstract
A one-time programmable (OTP) latch circuit can include a single OTP device capable of storing a logic value in a nonvolatile fashion, or only two OTP devices in the event redundancy is desired. A latch section can latch a data value based on a comparison between a current drawn according to the one OTP device, and a reference current generated without and OTP device. An OTP device can include a gate oxide antifuse (GOAF) device.
Description
Technical field
The present invention is in general relevant with latch circuit, and more particularly, the present invention with can be relevant with the latch circuit of non-volatile storage element coupling operation.
Background technology
In general electronic system can comprise data storage capability.For example, similarly be the bistable circuit of trigger, can in one of described two binary logic numerical value, keep a data value according to one of described trigger is imported.It is general that employed can to keep the bistable circuit that a logic value is written into or write once more up to another numerical value be a latch.
Latch can adopt multiple different form.For example, a latch can comprise cross-linked inverted rectifier, and it can latch a data value on the complementary data node, up to writing a new data value again.This latch is usually as static random stored memory (SRAM) unit.The latch of one static random stored memory form can store the true and complementary logic numerical value that is sent to described latch form, and just as an example, it is a data bus.This storage data value can be read when an addressing storage element is obtained (for example, reading) data at a performance element.
Unlike internal storage location, it may need to be updated periodically (in other words, dynamic random stored memory (DRAM) unit), the latch of a static random stored memory form can keep stored data and need not upgrade, till removing the time of electric power from described latch.Yet, even in many application, all want a kind of effect that also can carry out the data value reservation in the electric power that lacking.As an example, in some system, ROM (read-only memory) (ROM) storing media can be used for the software in the storage application, and it does not change immediately or does not need as a start driver.More particularly, ROM (read-only memory) is used as the part of a basic input/output (BIOS) sign indicating number usually, and can use in question blank and feature generator.
In case after being programmed, the mode how a ROM (read-only memory) keeps a programming state then can change according to employed ROM (read-only memory) form.In general, ROM (read-only memory) can be used a kind of non-volatile storage element.As known, a non-volatile storage element still can kept a stored logic value after described circuit removes electric power.By contrast, a volatibility storage unit will be lost a numerical value storage at once after removing electric power.
Latch circuit generally then is understood that a kind of volatile circuits.On the other hand, shielded read-only memory or field-programmable read-only storage (PROM) are a kind of forms of Nonvolatile memory.The form of other Nonvolatile memory comprises electronic type programmable read only memory (EPROM) and electronic type EPROM (EEPROM).
In general, the main difference between field-programmable read-only storage and the electronic type programmable read only memory (or electronic type EPROM), be described the former in general can only be programmed once, and after can't be eliminated.The described latter can be by applying ultraviolet light or electrical erasure is removed." flash memory (Flash) " storer is a kind of form of electronic type EPROM, its can be non-volatile at needs with the application of demagnetization in use.
Electronic sub-system can comprise volatibility and Nonvolatile memory usually.In general, a volatile ram is to be positioned among the integrated circuit, its be separated by with the integrated circuit that comprises a Nonvolatile memory and away from.Yet, may exist volatibility and non-volatile storage element both to be included in situation among the described identical integrated circuit.In this case, it is in general different fully with the target data that is used for described volatibility storage unit to be used for the target data of volatibility storage unit.For example, described different pieces of information set can be respectively applied for different application.
For described identical data value, then want to reach a kind of storage device with volatibility and nonvolatile features.For example, if data when electric power exists by temporary transient preservation, a storage device can use a latch, wherein can write data and after read.Yet,, can utilize described data value is stored in mode among the non-volatile storage element, and after removing electric power, still possess described data if when described storage data has enough importance.The basic function of a kind of demand storage device like this is just as latch, but also comprises the non-volatile storage element that is used for latch data, and therefore can be used as be not a latch be exactly non-volatile storage element special-purpose traditional storage device improvement.A kind of circuit like this can be considered to be a kind of " able to programme " latch circuit.
In order to obtain the preferable understanding of disclosed embodiment different viewpoints of the present invention, at first will narrate the example of two kinds of conventional programmable latch.
In Figure 11, set the schematic diagram of one first conventional programmable latch, and marked with general reference number 1100.One programmable latch circuit 1100 can comprise a volatile latch section 1102, a read/write multiplexer fragment 1104 and a nonvolatile storage fragment 1106.One volatile latch 1102 can store a value data responding a write operation, and output data is to respond a read operation.One multiplexer fragment 1104 can make among data are loaded on volatile section 1102 from a nonvolatile storage (reading) fragment, and the data of storage (writing) in volatile section 1102 are programmed among the nonvolatile storage fragment 1106.
In the special example of Figure 11, nonvolatile storage fragment 1106 can be used the non-volatile storage element of silica nitrogen-oxygen-silicon (SONOS) form.Silicon oxide nitride oxide silicon (SONOS) form non-volatile storage element can be programmed to inverse state (for example, when applying a specific grid voltage, having conduction or non-conduction condition).In a load operation, the described node of described latch can be by equilibrium.The silicon oxide nitride oxide silicon device of described opposite programming can with described latch node after equilibrium state discharges, latch node is caused different current potentials.Therefore, a data value of being set up by described silicon oxide nitride oxide silicon storage unit just can be latched device among latch section 1102.
In this mode, a programmable latch can comprise the non-volatile storage element of most storage data values, and its storage can be latching to the value data among the volatile latch circuit.
In Figure 12, set the schematic diagram of one second conventional programmable latch, and marked with general reference number 1200.One programmable latch circuit 1200 can comprise a volatile latch section 1202, a multiplexer fragment 1204 and a nonvolatile storage fragment 1206.Unlike the configuration of Figure 11, second conventional programmable latch 1200 can be " disposable " (OTP) able to programme.That is to say that described programmable latch 1200 can use non-volatile storage element, it is merely able to by single programming (otp device).In the very special example of Figure 12, a nonvolatile storage fragment 1206 can comprise goaf (GOAF) device 1208.Especially, goaf device 1208 can be the part of a kind of three transistors (3T GOAF) unit 1210 (also being referred to as the internal storage location into " two-transistor Unit one (2T-1C) ").
A shortcoming of the above conventional arrangement is a needed area in realizing sort circuit the time.Especially when setting up complementary value, need to use two non-volatile apparatus, and in general described non-volatile apparatus all is large-scale plant at volatile latch node place.Especially, in the device of case of sonos type, because need a big relatively program current (for example, 1 micromicroampere (mA)), thereby plant bulk that will be big relatively is to be supplied to this electric current in described silicon oxide nitride oxide silicon device.In the situation of goaf device, a goaf cell may occupy 30% to 40% of described programmable latch circuit.
Above-described shortcoming may become deterioration because need redundancy in described programmable device in some applications.Especially when realizing fully redundance, must comprise four non-volatile elements, this just further increases size of described programmable latch.
In above-described viewpoint, it need reach a kind of one time programmable latch circuit, but its to have compared to the above traditional settling mode be little size.
Summary of the invention
The present invention can comprise a programmable latch circuit, it comprises and is merely able to the current source of being programmed and installing, provide a current reference value and do not comprise the One Time Programmable device with the One Time Programmable (OTP) that stores a logic value by single, and a storage circuit that stores a predetermined logic numerical value, described predetermined logic numerical value then is based on responds electric current that described One Time Programmable device drawn and the comparison between the described reference current.
The present invention also can comprise a programmable latch, and it has a latch circuit, a current source circuit and an One Time Programmable device.Described latch circuit has the cross-couplings back end that stores a logic value.One current source circuit then is coupled with one first back end, and can supply one first electric current to, first back end to respond a load signal.One current source circuit is not to control according to any non-volatile memory device.One Time Programmable device projected current not basically in one first state, and in described second state, draw a leakage current.In addition, described One Time Programmable device can be coupled with one second back end, to respond a load signal.
The present invention also can comprise the method for a programmable latched.Described method comprises a state of setting up an One Time Programmable device, so that a program current numerical value of representing a predetermined logic numerical value to be provided.Described method can further provide a reference current that does not produce from the One Time Programmable device, and latchs the data value based on difference between described program current and described reference current.
Description of drawings
Fig. 1 is the block icon of one first embodiment One Time Programmable (OTP) latch circuit according to the present invention.
Fig. 2 is the schematic diagram of the one second embodiment one time programmable latch circuit according to the present invention.
Fig. 3 A to Fig. 3 F is the current source circuit schematic diagram that can be contained in the embodiment of the invention.Fig. 3 G is for showing the sequential chart that is used for Fig. 3 A to Fig. 3 F circuit signal example start-up time.
Fig. 4 is for showing the sequential chart that is used for Fig. 2 circuit one data write operation.
Fig. 5 is for describing the schematic diagram that is used for Fig. 2 circuit one programming operation.
Fig. 6 is for describing the schematic diagram that is used for Fig. 2 circuit one data loading operations.
Fig. 7 shows the sequential chart that is used for the load operation of Fig. 2 circuit data in addition.
Fig. 8 A is the schematic diagram of one or three transistors (3T) goaf (GOAF) circuit, and it can be used for embodiments of the invention.Fig. 8 B is the side section configuration/processing icon of a goaf device.Fig. 8 C is that representative is used for a goaf device one first stratum's structure of models icon.
Fig. 9 is the top configure icons according to four the three transistor gate oxide anti-fuse circuits of an embodiment.
Figure 10 is the method flow diagram according to another embodiment of invention.
Figure 11 is the schematic diagram of a conventional programmable latch circuit, and it uses the storage unit of silicon oxide nitride oxide silicon (SONOS) form.
Figure 12 is the schematic diagram of an otp latch circuit, and it uses most goaf device.
Embodiment
Different embodiments of the invention instruct a kind of programmable latch circuit and method.An employed programmable element in comprising redundant embodiment, or in not comprising redundant situation, have only two programmable elements, can reach less circuit size.
With reference now to Fig. 1,, the programmable latch circuit of set basis one first embodiment in a block diagram, and marked with general reference number 100.Described programmable latch circuit can be a kind of One Time Programmable (OTP) latch circuit, and can comprise a latch section 102, a current source circuit 104 and One Time Programmable circuit 106.One latch circuit 102 can be a volatibility storage circuit, and it can latch a value data DATA.For example, a latch circuit 102 can provide complementary data value DATA and DATAB on complementary data node ND0 and ND1.
One current source circuit 104 can provide a reference current IREF to latch circuit 102.In one embodiment, the size of a reference current IREF can be greater than the electric current of being drawn by One Time Programmable circuit 106 when storing a state, but less than the electric current of being drawn by One Time Programmable circuit 106 when storage one second state.One current source circuit 104 does not use any non-volatile apparatus to produce described reference current.
One Time Programmable circuit 106 can be programmed to one of two condition at least.A kind of circuit like this can be an One Time Programmable.That is to say that in case described circuit has been programmed to a particular state, it just maintains among this state (in other words, its for can not eliminate).Preferably, One Time Programmable circuit 106 can comprise the One Time Programmable device with in order to the interlock circuit of the described One Time Programmable device of programming.And more preferably, the One Time Programmable circuit can comprise a goaf (GOAF) device, and can be enabled in a grid structure and the circuit that generally is connected the program voltage that applies between source electrode-drain electrode structure.
As already pointed out, in a state (in other words, programming), One Time Programmable circuit 106 can be drawn one first current values (for example, basically not projected current), and it is less than a reference current that is provided by current source circuit 104.In another state (in other words, programming), One Time Programmable circuit 106 can be drawn a leakage current, and it is greater than a reference current that is provided by current source circuit 104.
In this mode,, just can cause a value data to be latched in a latch circuit by the projected current difference that an otp device and current source circuit are produced.Be noted that only to comprise an One Time Programmable device, form compared to the conventional arrangement that relies on two this kind devices circuit more closely.
In Fig. 2, the one time programmable latch circuit of set basis one second embodiment, and marked with general reference number 200.One time programmable latch circuit 200 can be relevant to the consideration together of Fig. 1, and wherein on behalf of of setting general circuit in Fig. 1, Fig. 2 can realize especially.One time programmable latch circuit 200 can comprise a latch section 202, a current reference circuit 204, One Time Programmable circuit 206 and a loading/programmed circuit 218.
One latch section 202 can comprise n channel insulation gate field effect transistor (NFET (NMOS) s) N1 and N2, and they are cross-couplings between back end 208 and 210.Same, p channel insulation gate field effect transistor (PFETs) P1 and P2 also can be between back end 208 and 210 cross-couplings.Observe in another way, 202 of latch section comprise cross-couplings inverted rectifier N1/P1 and N2/P2.
One latch section 202 can further comprise " maintenance " p channel insulation gate field effect transistor P3 and P4.Keep p channel insulated gate FET P3 can have the one source pole-drain path that between a back end 208 and a high supply voltage VPWR, is coupled, keep p channel insulated gate FET P4 then to have the one source pole-drain path that between a back end 210 and a high supply voltage VPWR, is coupled.The grid of described p channel insulated gate FET P3 and P4 then receives a holding signal HOLD jointly.In addition, a latch section 202 can comprise balanced n channel insulation gate field effect transistor N3 and N4.Balanced n channel insulated gate FET N3 can have the one source pole-drain path that is coupled between a back end 210 and a low supply voltage VGND, and balanced n channel insulation gate field effect transistor N4 can have the one source pole-drain path that is coupled between a back end 208 and a low supply voltage VGND.The grid of change n channel insulation gate field effect transistor N3 such as described and N4 then receives an equalizing signal EQ jointly.
One current reference circuit 204 can be connected between a high voltage VPWR and back end 210, and can supply a reference current I
REFIn shown special example, a current reference circuit 204 can respond a signal LOAD and be activated.That is to say that when enabling signal LOAD not, current reference circuit is supply of current not basically.Yet when signal LOAD started, current reference circuit can be supplied reference current I
REFCan utilize special electric current possibility example form as a current reference circuit 204, it will more be described in detail following.
One Time Programmable circuit 206 can comprise One Time Programmable device 212, a high voltage transistor 214 and a programming transistor 216.In the special example of Fig. 2, One Time Programmable device 212 can be a goaf device.Just as what well understood, a goaf device can comprise a grid structure, and it utilizes a gate insulator (at this normally a kind of oxide) and a substrate separation.One not in the programming state, a gate insulator can be kept perfectly intact.Therefore, when applying a current potential between described grid and described substrate, a leakage current can be zero basically.By contrast, in a programming state, can see through described gate insulator and set up a short circuit.Therefore, when between described grid and described substrate, applying a current potential, just cause a leakage current.One high voltage transistor 214 can be the transistor that a kind of design is used for resisting a relative noble potential between its grid and source/drain.Just as an example, a high voltage transistor can have compared to other device of described circuit and the gate insulator of Yan Weihou.
One Time Programmable device 212 can have in order to receiving the coupled gates structure of a program voltage Vpp, and the source that is connected to high voltage transistor 214 1 drain electrodes jointly.One high voltage transistor 214 can have the one source pole-drain path of coupling between One Time Programmable device 212 and programming transistor 216 1 drain electrodes.Programming transistor 216 can have the one source pole-drain path that is coupled between a high voltage transistor 214 and a low supply voltage VGND.
One loading/programmed circuit 218 can provide between the different paths between single programmable circuit 206 and the latch section 202.In the configuration of Fig. 2, a loading/programmed circuit 218 can comprise a program enable device 220, and read One Time Programmable device 222, a dummy device 224 and a data loading device 226.In a customized configuration, one program enable device 220 can comprise a high voltage transistor, it has the one source pole-drain path that is connected between back end 208 and programming transistor 216 1 grids, and in order to receive the grid of a programming enabling signal PRGEN.One reads One Time Programmable device 222 can comprise a transistor, and it has in a low electric power supply voltage VGND and the one source pole-drain path that is connected between program enable device 220 1 drains, and can receive a signal RDOTP at its grid place.One dummy device 224 can be to be connected to transistorized one " diode ", and described transistor then is coupled between a node 210 and a low electric power supply VGND.One data loading device 226 can be a transistor, and it has the one source pole-drain path that connects between high voltage transistor 214 back end 208, and in order to receive the drain electrode of a load signal LOAD.
Still with reference to figure 2, the configuration of Fig. 2 shows a circuit, wherein can see through back end 208 and 210 both, data are written to a latch, and read from a latch.In view of the above, described one time programmable latch circuit 200 comprises one first read-out amplifier 230 that is coupled to back end 208, and one second read-out amplifier 232 that is coupled to back end 210.Read-out amplifier (208 and 210) can respond respectively and read signal READ1 and READ2 starts.Be noted that READ1 and READ2 can be identical signals in the situation that needs different pieces of information to read, or in the situation that needs " signal terminating " read, be different signals.
Utilize a similar form, write data and/or reading of data is provided in order to receive, the described embodiment of Fig. 2 comprise with the coupling of one first bit line 236 one first by device 234, and with 240 couplings of one second bit line one second by device 238.In this mode, can utilize the mode that starts by device 234 and 238, a value data is write to a latch circuit 202, or read from a latch circuit 202.In the situation of a write operation, can between bit line 236 and 240, drive a different voltage.In the situation of a read operation, a difference voltage that is produced between bit line 236 and 240 can be exaggerated.
Certainly, in alternate embodiment, for this data of latch section 202 write with read operation also can be " unilateral termination ".In addition, if data from bit lines of read- out amplifier 230 and 232 couplings or both bit lines when reading, reading access can be " dual interface ".
As already pointed out, a current reference circuit similarly is a current reference circuit 204 shown in Fig. 2, can have multiple form.Some of planting current reference circuit like this may realize then being presented among Fig. 3 A to Fig. 3 E with schematic diagram.These circuit are just represented possible current reference circuit example, and it should not be considered to be used for limiting the present invention.
Each of current reference circuit described in Fig. 3 A to Fig. 3 F can comprise a current source transistor P1 and a data load transistor N1.In Fig. 3 A, a current source transistor P1 can have the grid that is connected to a low supply voltage VGND, and therefore can operate in the mode of utilizing strong reversing.One data load transistor N1 can receive an effectively high LOAD signal.Art technology person can see clearly that transistor P1, N1 or both can be adjusted size and/or be doped in the described circuit of Fig. 3 A, to reach a kind of reference current numerical value of wanting.
Fig. 3 B shows that current source transistor P1 forms the configuration of current mirror P1/P2 part.One data load transistor N1 can be arranged in a pin of described current mirror.In the selection, be to be not enough to produce one require in the situation of current values in the self-bias of described p channel transistor P1/P2, a current providing circuit 420 can be situated in another pin of described current mirror.
Fig. 3 C shows that current source transistor P1 forms another configuration of current mirror P1/P2 part.One data load transistor N1 can be situated in the pin of described current mirror, and by described reference current that described another pin provided.In the selection, in the situation of the self-bias deficiency of described current mirror, a current providing circuit 422 can be connected in series with data load transistor N1.
Fig. 3 D shows a kind of configuration, and it can comprise the identical primary element as Fig. 3 B.Yet described circuit 406 can comprise one second data load transistor N2 in addition at another pin of described first current mirror that load transistor is arranged in, one pin.Second load transistor can receive one second load signal LOAD2.This data that are configured in are not loaded, and two pin of described current mirror P1/P2 can provide a kind of favourable low standby current when all being closed.
Fig. 3 E shows a kind of configuration, and it can comprise the identical primary element as Fig. 3 A.Yet current source transistor P1 can receive a voltage bias VB IAS, with control when the log-on data load transistor N1, the electric current total amount that is provided.
Fig. 3 F shows a kind of configuration, and it can comprise the identical primary element as Fig. 3 A.Yet, can use a resistor R 1 to replace described current source transistor P1.
At last, in other embodiments, a reference circuit can be a digital programmable.For example, can use a current source digital revolving die to intend converter (DAC) to produce a reference current.This configuration can form the overall output of improvement, is being increased the change of One Time Programmable leakage current and other change from handling to handle.The current digital revolving die is intended converter (DAC) form and method also is that the special smart person in this area is known.
Fig. 3 G shows the sequential chart that is used for signal LOAD and LOAD2 (only showing at Fig. 4 D).As shown, transistor N1 can be activated at first, then is transistor N2.Certainly, just represent an example duration of shown signal specific, it can change according to specific implementation.
Embodiment example in Fig. 2 and Fig. 3 is described in detail, and to referring now to Fig. 4 to Fig. 7, describes the different operating of one time programmable latch circuit 200 described in Fig. 2.
Fig. 4 is for showing the sequential chart of one time programmable latch circuit 200 1 data write operation.Fig. 4 comprises the waveform that a complementation writes value data DATA/DATAB, it may reside in paratope line, one HOLD signal is then in order to the control latch operation, one read/write signal RW can start the device that passes through with the bit line coupling, one equalizing signal EQ can be with the node equilibrium of a latch, and a LATCH DATA signal is then represented a latch data numerical value.
At the time t0 place, can exist one to write value data at described bit line.Probably at identical time place, a HOLD signal can fully be driven (be height) in this example, makes the holding device P3/P4 anergy among the latch section 202, to allow changing a latch state simply.One RW signal can be incomplete (being low in this example), and it can be kept by installing 234 and 238 and be in closed condition, and latch section 202 is isolated with said write data DATA/DATAB.One equalizing signal EQ also can be incomplete, has different current potentials to keep latch node.Latch data LATCH DATA can be maintained a previous numerical value of setting up.
Probably at time t1 place, an equalizing signal EQ can become complete state (being height in this example).Therefore, just can start equalizing apparatus N3/N4, both back end (208/210) that drive latch section 202 are low, cause LATCH DATA not have the data of foundation (back end the both be released).At place of identical time, holding device P3/P4 keeps and closes, and make the latch ability anergy of latch section 202, and signal RW keeps not exclusively, and continuation is with latch section 202 and write data isolation.
Before time t2, an equalizing signal EQ can get back to partial state, and back end (208 and 210) is isolated from each other.
At general time t2 place, a RW signal can be activated (in this example for high), start by device 234 and 238, and feasible complementation writes data DATA/DATAB and locates driving at back end (208 and 210).This can be so that latch circuit 202 receives the said write value data.
Afterwards, signal HOLD can get back to an active state, starts holding device P3/P4, and therefore makes latch section 202 latch said write data.
Be noted that in write operation other unlike signal of Fig. 2 comprises that a high voltage bias signal HVB, reads One Time Programmable element signal RDOTP, a programming enabling signal PRGEN can be maintained low.At the same time, a program voltage Vpp can be in high-voltage state, but less than a program voltage (for example, a high supply voltage VPWR).
In this mode, data can be write to an otp latch circuit 200.
With reference now to Fig. 5,, the same circuits of its displayed map 2 has employed signal levels in a demonstration programming operation.One programming operation can be according to a state of the data setting One Time Programmable device 212 of institute's latch among latch section 202.More particularly, store in the situation of a numerical value (node 208 is that height, node 210 are for low) in a latch section 202, one insulator (oxide) of goaf device 212 is broken, produce a resistive short of passing goaf device 212 by this.Store in the situation of a complementary value (node 210 is that height, node 208 are for low) in a latch section 202, one goaf device 212 can be maintained not programming state, therefore, one insulator (oxide) of goaf device 212 can be kept complete, and projected current not basically.
In the shown programming operation example, it supposes that a latch section 202 can store a value data in Fig. 5, and makes goaf device 212 be programmed (node 208 for high, node 210 for low).
With reference to figure 5, in latch section 202, a HOLD signal can act on, and startup is lived again.Equating signal EQ can be incomplete.In addition, the RW signal can be incomplete, and bit line (236 and 240) and latch section 202 are isolated.
In One Time Programmable circuit 206, a goaf device 212 can receive a pulse program voltage Vpp at its grid place.In shown described particular example, its assumed goaf device 212 has the oxide thickness of about 20 dusts, and a pulse voltage Vpp is approximately 6.5 volts.One high voltage transistor 214 can receive an effective high voltage signal HVB.A signal like this can allow the source of goaf device 212 to be drawn toward a lower voltage in the situation of programming.At the same time, such device can be isolated latch section 202 with described relative high programming voltage Vpp.In shown described particular example, the HVB signal can drive and be general 3.25 volts.
Among loading/programmed circuit 218, one program enable device 220 can receive high voltage programming enabling signal PRGEN, and therefore a value data that stores in the latch section 202 is connected to a grid of programmer 216 among the One Time Programmable circuit 206.In this mode, if node 208 is high, programmer 216 can enable a programming path to VGND.In shown described specific operation, high voltage programming enabling signal PRGEN can be approximately 3.25 volts.At the same time, one reads the RDOTP signal that One Time Programmable device 222 may be received in an incomplete stratum place, and can be closed.In addition, a LOAD signal can be incomplete, and closes charger 226 and current reference circuit 204.
Under this situation, a goaf otp device 212 can be programmed setting up a program current, as with as shown in the arrow 500.In this mode, one time programmable latch circuit 200 can be programmed once, to remember a particular data value.
With reference now to Fig. 6,, the same circuits of its displayed map 2 has employed signal levels in a load operation.One load operation can be set the state of latch section according to a state of One Time Programmable device 212.More particularly, be programmed at One Time Programmable device 212 in the situation of (in other words, drawing an electric current), a latch section can be set to and store a numerical value (node 208 is low for high, node 210).Opposite, not being programmed at One Time Programmable device 212 in the situation of (in other words, not drawing an electric current basically), a latch section can be set to and store an opposite numerical value (node 208 is height for low, node 210).
In follow-up narration, will suppose that otp device 212 is for being programmed state.Among One Time Programmable circuit 206, a goaf device 212 can receive a high voltage at its grid place.In shown described particular example, a high voltage can be to have about 1.8 volts high power supply voltage.One high voltage transistor 214 also can receive and be approximately 1.8 volts similar high power supply voltage.Therefore, can start by the current path of goaf device 212 with high voltage transistor 214.
Among loading/programmed circuit 218, a program enable device 220 can receive one incomplete (low) programming enabling signal PRGEN.One LOAD news can be height, and a current path of 208 is provided from One Time Programmable circuit 206 to node, and from reference current circuit 204 to node another current path of 210.As what will be recalled, when One Time Programmable device 212 for what be programmed, one of node 208 leaks (in other words, charging), and electric current can be greater than a reference current of node 210.When One Time Programmable device 212 is programming, one of node 208 leaks (in other words, charging) that electric current can be less than a reference current of node 210.Therefore, according to a programming state of One Time Programmable device 212, the current potential between node 208 and 210 can be different, and are carried out at last and latch.
Among latch section 202, can start equalizing device N3/N4 at first, and make holding device P3/P4 anergy.In case between node 208 and 210, develop the voltage that an enough difference, just can make equalizing device N3/N4 anergy, and start holding device P3/P4, therefore according to a status latch one value data of described One Time Programmable device 212.
In Fig. 7, show a clock signal example that is used for this load operation.
Fig. 7 shows that equalizing signal EQ, holding signal HOLD and One Time Programmable read the sequential chart of signal RDOTP.At whenabouts t0 place, signal EQ can be height, starts equalizing device N3/N4, and synchronous signal HOLD can be height, closes holding device P3/P4.This can cause latch section 202 nodes 208 and 210 to be discharged to ground connection situation (VGND).
At whenabouts t1 place, it is one low-level that signal EQ can get back to, and causes back end 208 and 210 to be isolated from each other.At this moment, node 208 and 210 can be driven to different current potentials according to a programming state of One Time Programmable device 212.In addition, signal RDOTP can become effectively, and makes a program path anergy of One Time Programmable circuit 206.Be noted that a signal LOAD also starts after signal RDOTP becomes effectively.
At whenabouts t2 place, it is one low-level that signal HOLD can get back to, and starts holding device P3/P4 and therefore start the described latch function of latch section 202.Therefore the data that show described otp device 212 just can be latched.
In this mode, one time programmable latch circuit 200 can be programmed.The One Time Programmable device 212 that has been programmed, its leakage paths are then shown with arrow 600.
With reference now to Fig. 8 A to Fig. 8 C,, will be described in more detail for one or three transistors (3T) goaf (GOAF) circuit.Sort circuit can connect above embodiment to be considered together, and wherein, sort circuit can be as the One Time Programmable circuit.Fig. 8 A shows the schematic diagram of one or three transistor gate oxide anti-fuse circuits 800.Shown specific three transistor gate oxide anti-fuse circuits 800 can comprise a goaf device 802, a high voltage n channel insulated gate FET 804 and a low-voltage n channel insulated gate FET 806.One goaf device 802 can have the grid structure with a programming node 808 couplings, and the source that is connected to a high voltage n channel insulated gate FET 804 drains jointly.One high voltage n channel insulated gate FET 804 can be a kind of high voltage device, compared to most other transistor, can resist a higher voltage difference between its grid and drain/source.One high voltage n channel insulated gate FET 804 can have the source electrode that is connected to a low-voltage n channel insulated gate FET 806 drain electrodes.Low-voltage n channel insulated gate FET 806 can have the one source pole that is connected to a low supply voltage VGND.
The grid (grid structure) that Fig. 8 A is presented at described different device locates to receive a very special example of high voltage levels.Therefore, a programming node 808 can receive a high signal to 6.5 volts.One grid of high voltage n channel insulated gate FET 804 can receive a high signal to 3.25 volts.At last, a grid of low-voltage n channel insulated gate FET 806 can receive a high signal to 1.8 volts.
Fig. 8 B shows the side section icon according to an embodiment one goaf device.One goaf device 810 can have the identical general structure that is had with a n channel insulation gate field effect transistor, comprise a gate insulator 812 that is formed on the p doped substrate 814, and all over gate insulator (for example, oxide) 812 on a formed grid structure 816.In addition, in substrate 814, can form a N doped source 818 and a N doped-drain 820.N doped source 818 can be connected to each other prevailingly with drain electrode 820.
As what well understood, when between a grid structure 816 and source/drain 818/820, applying a high voltage, because cause one gate insulator 812 of charge-trapping and infiltration may collapse at a tender spots place.Current density at the collapse point place may cause localized hyperthermia, a silicon fine rule (showing with 822) of its may connect a grid structure 812 and substrate 814.The generation of this fine rule (for example 822) may form the structure of a kind diode, and its effect similarly is the transistor with saturated drain electrode.
Fig. 8 C shows that one is programmed a representative model of goaf device.Therefore, a goaf device model 830 can comprise a resistance R
SHORTWith a diode.
With reference now to Fig. 9,, sets the sample design of three transistor gate oxide anti-fuse circuits in top view icon mode.Fig. 9 can consider that it represents a kind of possible design configurations with above embodiment, and can use with above which couple.
Four three transistor gate oxide anti-fuse circuit 902-0 to 902-3 are described in design 900, and it is about total 904 mirror-image arrangement of Vpp contact.Each goaf circuit (902-0 to 902-3) can comprise a goaf device 906, high voltage transistor 908 and low-voltag transistor 910 (only show and be used for goaf circuit 902-3).The shade structure can be to spread all over the formed polysilicon gate layer more than of active area, and described active area is then separated from one another with isolator 912.
According to the good known technology that gets, device 906 can utilize many silicon gates to form with transistor 908 and 910, and with a gate oxide and a substrate separation.Device 906 and 908 can be a high voltage device, and has thicker gate oxide and/or mix especially.
Scrutablely be that in a kind of traditional approach that similarly is Figure 12, a design 900 only providing two otp latch circuit to be used, or can only be used by an otp latch circuit when using redundancy when not using redundancy.Under significantly contrasting, when in according to the one time programmable latch circuit of the above embodiment, using one to design 900, this design can provide four otp latch circuit to use when not using redundancy, or provides two otp latch circuit to use when using redundancy.
In this mode, described various embodiment can provide a large amount of minimizings of circuit size for similarly being for traditional solution among Figure 12.
With reference now to Figure 10,, with the method for narration a kind of programming/operation one time programmable latch circuit.The embodiment of Figure 10 can consider with above embodiment, and wherein this method can be done by sort circuit institute is real.
Figure 10 shows the flow process diagram of a method 1000, and it comprises and utilizes the One Time Programmable device to produce a data current I
DATA(step 1002).Described method further comprises does not utilize the One Time Programmable device to produce a reference current I
REF(step 1004).At described data current I
DATAGreater than described reference current I
REFSituation in ("Yes" at 1006 places), just can latch a value data DATA (step 1008).At described data current I
DATAAnd be not more than described reference current I
REFSituation in ("No" at 1006 places), can latch a complementary data value DATAB (step 1010).
In view of the above, described different embodiment can propose a kind of improvement for traditional settling mode, in traditional approach, is merely able to a kind of non-volatile form, uses the One Time Programmable device to store a logical data (being two by contrast).In addition, in the situation of needs redundancy, only need to increase an extra One Time Programmable device (needing to increase by two this devices by contrast).
Another advantage is for improving whole programming output.In a traditional solution that similarly is Figure 12, can load a value data from the One Time Programmable device according to the leakage current in one of two One Time Programmable devices.That is to say, for all sort circuits, the One Time Programmable device of must programming at least.By contrast, the above embodiment only programmes a device according to the described logical data that is stored.
And in addition, the present invention also provides a kind of favourable degree adjusted, to carry out more efficient load operation.More particularly, after programming, can adjust a reference current according to an expection or actual goaf resistance numerical value.This can form comparatively fast and/or more reliable load operation.
Passable solving be, described embodiment of the present invention can carry out lacking under the element that do not specify or the step.That is to say that an inventive features of the present invention can be omitted an element or step.
In addition, for purpose clearly, the many quilts of one time programmable latch circuit and method of operating are extensively known and details not related to the present invention, also omit from above narration.
What should know from experience is, spreading all over employed reference term in this concrete specification, similarly is that " embodiment " or " embodiment " are meaning specific feature, structure or a characteristic and be and the description that embodiment connects that is comprised at least one embodiment of the present invention.Therefore, be stressed that employed reference term " embodiment " or " embodiment " or " alternate embodiment " do not need forever with reference to identical embodiment in this concrete specification mass part.In addition, described special characteristic, structure or characteristic can be by suitable couplings in one or more embodiment of the present invention.
Same, though set and narrated many different viewpoints of described specific embodiment, do not deviating under the present invention's spirit and the viewpoint at this, can carry out belonging to different changes, displacement more and replacing to the present invention.
Claims (20)
1. programmable latch circuit comprises:
An One Time Programmable (OTP) device, it is merely able to be programmed to store a logic value by single;
One current source, it provides a current reference value, and described current reference value is not that state according to any One Time Programmable device produces; And
One storage circuit, it stores a predetermined logic numerical value, and described predetermined logic numerical value then is based on the electric current responding described One Time Programmable device and draw and the comparison between the described reference current and decides.
2. programmable latch circuit as claimed in claim 1, wherein:
Described One Time Programmable device comprises a goaf device.
3. programmable latch circuit as claimed in claim 1, wherein:
Described storage circuit comprises
One latch circuit, it stores described predetermined logic numerical value and comprises at least two latch node that store complementary logic numerical value,
One sensor amplifier, itself and at least one described latch node are coupled, and amplify the described logic value on the described latch node, and
One by device, and it is coupled with at least one described latch node, and provides one to write the path of data to described latch circuit.
4. programmable latch circuit as claimed in claim 1, wherein:
Described current source is to be selected from the group that is made up of following element:
One transistor is right, and it comprises a first transistor and a transistor seconds of polyphone, described the first transistor and power supply coupling, and described transistor seconds is started by a load signal, and it is in starting when described One Time Programmable device loads a value data,
One transistor is right, it comprises a first transistor and a transistor seconds of polyphone, described the first transistor and bias voltage coupling, the level of described bias voltage between supply voltage, described transistor seconds is started by a load signal, it is in starting when described One Time Programmable device loads a value data
One current mirror, it has the load transistor with one of them polyphone of two current mirror pin, and described load transistor is started by a load signal, and it is in starting when described One Time Programmable device loads a value data,
One current mirror, it has the load transistor of all contacting with two current mirror pin, and described load transistor is started by a load signal, and it is in starting when described One Time Programmable device loads a value data, and
One resistor, itself and a load transistor are connected in series, and described load transistor is started by a load signal, and it starts in from described One Time Programmable device control loaded one value data the time.
5. programmable latch circuit as claimed in claim 1 also comprises:
A described current source and a storage circuit, it comprises insulated gate FET; And
An One Time Programmable circuit, it comprises described One Time Programmable device and at least one high voltage transistor, and described high voltage transistor comprises a gate insulator, and its described transistor than described current source and storage circuit more can be resisted the high voltage collapse.
6. programmable latch circuit as claimed in claim 5, wherein:
Described storage circuit comprises a latch circuit, and it stores described predetermined logic numerical value and comprises at least two latch node that store complementary logic numerical value,
Described One Time Programmable circuit, it comprises described One Time Programmable device, described high voltage transistor and a programming transistor, one source pole-the drain path of described high voltage transistor is coupled between described One Time Programmable device and one of them the described latch node, and the one source pole-drain path of described programming transistor then is coupled between a described high voltage transistor and the low supply voltage.
7. programmable latch circuit as claimed in claim 1 also comprises:
One redundant One Time Programmable (R-OTP) device, it is merely able to be programmed to store a logic value by single, described redundant One Time Programmable device and described One Time Programmable device are arranged in parallel, and when described One Time Programmable device did not lose efficacy, described redundant One Time Programmable device was not programmed with the state with described One Time Programmable device and matches.
8. one time programmable latch comprises:
One latch circuit, it has the cross-linked back end that stores a logic value;
One current source circuit, itself and one first back end are coupled, and described current source circuit responds a load signal and supplies one first electric current to one first back end, and described first current values is not to control according to any non-volatile memory device; And
An One Time Programmable device, its projected current not basically in one first state, and in one second state, draw a leakage current, wherein said One Time Programmable device responds described load signal and is coupled to one second back end.
9. one time programmable latch as claimed in claim 8, wherein:
Described latch circuit comprises
A pair of latch transistor, it is cross-couplings between described back end, and
A pair of maintenance transistor, one first keeps transistor to have the one source pole-drain path that is coupled between one first back end and one first supply voltage, one second keeps transistor to have the one source pole-drain path that is coupled between one second back end and described first supply voltage, and described first and second keeps transistorized grid coupled in common to receive a holding signal.
10. one time programmable latch as claimed in claim 9, wherein:
Described latch circuit also comprises
A pair of balanced transistor-resistor logic, one first balanced transistor-resistor logic has the one source pole-drain path that is coupled between described first back end and the second source voltage, one second balanced transistor-resistor logic has the one source pole-drain path that is coupled between described second back end and the described second source voltage, and transistorized grid coupled in common such as described first and second gradeization is to receive an equalizing signal.
11. one time programmable latch as claimed in claim 8 also comprises:
One high voltage transistor, it has the one source pole-drain path that is coupled between described One Time Programmable device and described second back end.
12. one time programmable latch as claimed in claim 11 also comprises:
One programming transistor, it has the one source pole-drain path that is coupled between described high voltage transistor and the second source voltage, and gate coupled is to one of them of described back end.
13. one time programmable latch as claimed in claim 12 also comprises:
One programming starts transistor, and it has the one source pole-drain path between the grid that is coupled in described programming transistor and the described back end.
14. one time programmable latch as claimed in claim 8 also comprises:
An One Time Programmable load transistor, it has the one source pole-drain path that is coupled between described One Time Programmable device and described second back end;
One current source load transistor, it has the one source pole-drain path that is coupled between described current source circuit and described first back end; Wherein
The grid coupled in common of described One Time Programmable load transistor and described current source load transistor is to receive a load signal.
15. a programmable latched method, it may further comprise the steps:
Set up a state of One Time Programmable device, so that a program current numerical value of representing a predetermined logic numerical value to be provided;
One reference current is provided, and it is not to be produced by the One Time Programmable device; And
Latch a value data according to the difference between described program current and the described reference current.
16. programmable latched method as claimed in claim 15, wherein:
The described state of setting up described One Time Programmable device comprises,
Store a logic value, in the insulator of the goaf device of drawing a leakage current, set up a short circuit, and
Store another logic value, it does not change the gate insulator of described goaf device, and does not come projected current with described goaf device basically.
17. programmable latch method as claimed in claim 16, wherein:
Described reference current is lower than described leakage current.
18. programmable latch method as claimed in claim 15, wherein:
Provide described reference current to comprise to apply and be biased in a current supply transistor.
19. programmable latch method as claimed in claim 15 also comprises:
When the programming described One Time Programmable device a state time,
One value data is written to a latch, and
When described latch stores one particular data value, start a read/program potential of described One Time Programmable device.
20. programmable latch method as claimed in claim 15, wherein:
Provide described reference current to comprise and produce described reference current from a digital numerical value.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US61317904P | 2004-09-24 | 2004-09-24 | |
| US60/613,179 | 2004-09-24 | ||
| US11/234,429 | 2005-09-23 |
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| Publication Number | Publication Date |
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| CN101128884A true CN101128884A (en) | 2008-02-20 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2005800320808A Pending CN101128884A (en) | 2004-09-24 | 2005-09-23 | One time programmable latch and method |
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| CN (1) | CN101128884A (en) |
| TW (1) | TW200627448A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102074269A (en) * | 2009-11-24 | 2011-05-25 | 华东光电集成器件研究所 | Programmable information storage circuit |
| CN106469565A (en) * | 2015-08-18 | 2017-03-01 | 力旺电子股份有限公司 | Digital generator, disposable programmable memory block and digital production method |
| CN108335712A (en) * | 2017-01-17 | 2018-07-27 | 恩智浦美国有限公司 | Volatile latch circuit with the backup of anti-interference Nonvolatile latch |
-
2005
- 2005-09-22 TW TW094132921A patent/TW200627448A/en unknown
- 2005-09-23 CN CNA2005800320808A patent/CN101128884A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102074269A (en) * | 2009-11-24 | 2011-05-25 | 华东光电集成器件研究所 | Programmable information storage circuit |
| CN106469565A (en) * | 2015-08-18 | 2017-03-01 | 力旺电子股份有限公司 | Digital generator, disposable programmable memory block and digital production method |
| US10181357B2 (en) | 2015-08-18 | 2019-01-15 | Ememory Technology Inc. | Code generating apparatus and one time programming block |
| CN106469565B (en) * | 2015-08-18 | 2019-07-05 | 力旺电子股份有限公司 | Digital generation device, disposable programmable memory block and digital production method |
| CN108335712A (en) * | 2017-01-17 | 2018-07-27 | 恩智浦美国有限公司 | Volatile latch circuit with the backup of anti-interference Nonvolatile latch |
| CN108335712B (en) * | 2017-01-17 | 2023-06-27 | 恩智浦美国有限公司 | Volatile latch circuit with tamper-resistant nonvolatile latch backup |
Also Published As
| Publication number | Publication date |
|---|---|
| TW200627448A (en) | 2006-08-01 |
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