CN101110390A - Wafer cutting method - Google Patents
Wafer cutting method Download PDFInfo
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- CN101110390A CN101110390A CNA2006100994224A CN200610099422A CN101110390A CN 101110390 A CN101110390 A CN 101110390A CN A2006100994224 A CNA2006100994224 A CN A2006100994224A CN 200610099422 A CN200610099422 A CN 200610099422A CN 101110390 A CN101110390 A CN 101110390A
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Abstract
A wafer cutting method firstly provides a wafer. The wafer is provided with a plurality of positive module array units and a first contrapuntal mark. And then, the wafer is connected with a transparent substrate. The transparent substrate is provided with an edge zone, which is convex out of the wafer. A second contrapuntal mark is formed on the edge zone. Besides, the transparent substrate is cut with the first contrapuntal mark as a reference mark and the wafer is cut with the second contrapuntal mark as a reference mark.
Description
Technical field
The invention relates to a kind of wafer (Wafer) cutting method, and particularly relevant for a kind of method for cutting wafer with pinpoint accuracy.
Background technology
Along with modern video signal development of technology, optical projection apparatus has been widely used in occasions such as family's theater, mini-session report and operating room's discussion.Optical projection apparatus mainly comprises light source, optical valve in reflection type (light valve) and projection lens.Light source is in order to light beam to be provided, and optical valve in reflection type is in order to transforming the light beam into image, and projection lens be in order to image projecting on screen.
At present the kind of optical valve in reflection type mainly contain monocrystalline silicon LCD panel (Liquid Crystal onSilicon, LCOS) and digital micro-mirror device (Digital Micro-mirror Device, DMD) two classes.Because making the part processing procedure of monocrystalline silicon LCD panel can be finished by ripe Silicon Wafer (Wafer) manufacture of semiconductor of tradition, therefore compared to digital micro-mirror device, the processing procedure of monocrystalline silicon LCD panel is simple and easy, and yield is higher, so it has preferable competitive advantage.
Fig. 1 is the generalized section of known a kind of monocrystalline silicon LCD panel.Please refer to Fig. 1, known monocrystalline silicon LCD panel 100 comprises a plurality of groups of substrates of thin-film transistor 110, one conducting glass substrate 120, a liquid crystal layer 130 and a frame glue 140, wherein plurality of groups of substrates of thin-film transistor 110 is to be binded by frame glue 140 with conducting glass substrate 120, and liquid crystal layer 130 is to be disposed between plurality of groups of substrates of thin-film transistor 110 and the conducting glass substrate 120.In addition, the configuration that can misplace usually of plurality of groups of substrates of thin-film transistor 110 and conducting glass substrate 120 is to make things convenient for follow-up line connection process.
Accept above-mentioned, plurality of groups of substrates of thin-film transistor 110 has a plurality of thin-film transistors 112 of array configuration and the pixel electrode 114 (only showing a group in the diagram) that electrically connects with thin-film transistor 112, and the conducting glass substrate 120 of subtend has a transparency conducting layer 122.By the electric field strength between thin-film transistor 112 modulation pixel electrodes 114 and the transparency conducting layer 122, the sensing that can change liquid crystal molecule 132 in the liquid crystal layer 130 is to adjust the light reflected intensity.
Below, with the manufacturing process of narration monocrystalline silicon LCD panel 100.At first, shown in Fig. 2 A, provide a wafer 11, wafer 11 has a plurality of thin-film transistor array location 11a, and each thin-film transistor array location 11a all has as shown in Figure 1 a plurality of thin-film transistors 112 and pixel electrode 114.In addition, wafer 11 has the cross contraposition mark 11b that can supply contraposition to cut.
Continue, shown in Fig. 2 B, provide a conducting glass substrate 12.Then, shown in Fig. 2 C, conducting glass substrate 12 is fitted on the wafer 11, and the local cross section after fitting is shown in Fig. 2 D, wherein wafer 11 is to be binded by aforesaid frame glue 140 with conducting glass substrate 12.Afterwards, will in conjunction with after wafer 11 carry out the singulation processing procedure with conducting glass substrate 12 and can form a plurality of monocrystalline silicon LCD panels 100 as shown in Figure 1.Below, segmentation is narrated the detailed step of this singulation processing procedure.
At first, know the cross contraposition mark 11b that sees on the wafer 11 owing to seeing through conducting glass substrate 12, therefore can be with cross contraposition mark 11b as the reference mark, conducting glass substrate 12 is cut and form many line of cut L1 laterally and longitudinally with cutter.Look on after the cutting and local cross section shown in Fig. 2 E and 2F, wherein line of cut L1 defines the regional extent of each thin-film transistor array location 11a.
Yet, because wafer 11 is lighttight, thus can't be directly with cross contraposition mark 11b as the reference mark and therefore cutting crystal wafer 11 must make the contraposition mark in addition.Refer again to Fig. 2 E, the mode of making the contraposition mark at present be directly cut split wafer 11 and conducting glass substrate 12 edge to form two contraposition limit B.Then, with wafer 11 after the combination and conducting glass substrate 12 turn-overs, and be reference marker with this two contraposition limit B, wafer 11 is cut and form many line of cut L2 laterally and longitudinally with cutter.Look on after the cutting and local cross section shown in Fig. 2 G and 2H, wherein line of cut L2 and line of cut L1 have dislocation slightly.
These thin-film transistor array locations 11a is separated at last and form a plurality of monomers, and liquid crystal molecule poured into to seal behind these monomers promptly finish making monocrystalline silicon LCD panel 100 as shown in Figure 1 in the mode of board sliver.
In the process of above-mentioned cutting, the accuracy of cutting is the accuracy that depends on the contraposition mark.Fig. 3 is the local enlarged diagram of Fig. 2 E, please refer to Fig. 2 E and Fig. 3, owing to contraposition limit B directly cuts the edge of splitting wafer 11 and conducting glass substrate 12 by cutter to form, this can make contraposition limit B be smooth straight line, but is irregular curve.To detect contraposition limit B and it during as the reference mark, promptly can be caused bit errors P because of irregular contraposition limit B when the image sensor of board, make the accuracy of cutting crystal wafer 11 descend and cause line of cut L2 skew.
In addition, when directly cut with cutter split wafer 11 and conducting glass substrate 12 the edge with the process of making contraposition limit B in, can the accelerated wear test cutter and shorten useful life of cutter, cause cost of manufacture to improve.In addition, irregular contraposition limit B often can't be with the automatic contraposition of automatic alignment system, and needs carry out contraposition with manual type, makes production efficiency to promote.
Summary of the invention
The purpose of this invention is to provide a kind of method for cutting wafer, to promote sharpnes of cuts.
Another object of the present invention provides a kind of method for cutting wafer, to solve the problem of sharpnes of cuts deficiency.
For achieving the above object, method for cutting wafer provided by the invention comprises:
One wafer is provided, and this wafer has a plurality of driving component array locations and one first contraposition mark;
Engage a transparency carrier on this wafer, wherein this transparency carrier has zone, an edge, and this fringe region is to protrude from outside this wafer;
Form one second contraposition mark on this fringe region;
, as the reference mark this transparency carrier is cut with this first contraposition mark; And
, as the reference mark this wafer is cut with this second contraposition mark.
Described method for cutting wafer, the method that wherein forms this second contraposition mark comprises the laser burning.
Described method for cutting wafer, the method that wherein forms this second contraposition mark comprises etching.
Described method for cutting wafer, wherein this driving component array location is a thin-film transistor array location.
Described method for cutting wafer, wherein this transparency carrier is a conducting glass substrate, and this conducting glass substrate comprises a glass substrate and a transparency conducting layer, and wherein this transparency conducting layer is to be disposed on this glass substrate, and between this glass substrate and this wafer.
Described method for cutting wafer, the method for wherein cutting this wafer comprises machine cuts or laser cutting.
Described method for cutting wafer, the method for wherein cutting this transparency carrier comprises machine cuts or laser cutting.
The present invention also provides a kind of method for cutting wafer, comprising:
One wafer is provided, and this wafer has a plurality of driving component array locations and a contraposition mark;
, the edge of this wafer cut split as the reference mark with this contraposition mark to form one first contraposition limit and one second contraposition limit;
Processing procedure is polished on this first contraposition limit and this second contraposition limit;
Engage a transparency carrier on this wafer;
, as the reference mark this transparency carrier is cut with this contraposition mark; And
, as the reference mark this wafer is cut with this first contraposition limit and this second contraposition limit.
Described method for cutting wafer, the method for wherein polishing this first contraposition limit and this second contraposition limit comprises grinding and polishing.
Described method for cutting wafer, wherein the direction on this first contraposition limit is vertical with the direction on this second contraposition limit.
Described method for cutting wafer, wherein this driving component array location is a thin-film transistor array location.
Described method for cutting wafer, wherein this transparency carrier is a conducting glass substrate, and this conducting glass substrate comprises a glass substrate and a transparency conducting layer, and wherein this transparency conducting layer is to be disposed on this glass substrate, and between this glass substrate and this wafer.
Described method for cutting wafer, the method for wherein cutting this wafer comprises machine cuts or laser cutting.
Described method for cutting wafer, the method for cutting this transparency carrier comprises machine cuts or laser cutting.
In other words, a kind of method for cutting wafer of the present invention at first provide a wafer, and wafer has a plurality of driving component array locations and one first contraposition mark.Afterwards, engage a transparency carrier on wafer, and transparency carrier has zone, an edge, and fringe region protrudes from outside the wafer.Then, form one second contraposition mark on fringe region.Come again, as the reference mark, transparency carrier cut with the first contraposition mark, and then with the second contraposition mark as the reference mark, wafer is cut.
In one embodiment of this invention, the method for the above-mentioned formation second contraposition mark comprises laser burning or etching.
For reaching above-mentioned or other purpose, the present invention proposes a kind of method for cutting wafer in addition, and a wafer at first is provided, and this wafer has a plurality of driving component array locations and a contraposition mark.Afterwards,, the edge of wafer cut split as the reference mark with the contraposition mark to form one first contraposition limit and one second contraposition limit.Then, the first contraposition limit and the second contraposition limit polished processing procedure after, engage a transparency carrier on wafer.Come again, as the reference mark, transparency carrier cut with the contraposition mark, and then with the first contraposition limit and the second contraposition limit as the reference mark, wafer is cut.
In one embodiment of this invention, the method on the above-mentioned polishing first contraposition limit and the second contraposition limit comprises grinding and polishing.
In one embodiment of this invention, the direction on the first above-mentioned contraposition limit is vertical with the direction on the second contraposition limit.
In one embodiment of this invention, above-mentioned driving component array location is a thin-film transistor array location.
In one embodiment of this invention, above-mentioned transparency carrier is a conducting glass substrate, and conducting glass substrate comprises a glass substrate and a transparency conducting layer, and wherein transparency conducting layer is to be disposed on the glass substrate, and between glass substrate and wafer.
In one embodiment of this invention, the method for above-mentioned cutting crystal wafer comprises machine cuts or laser cutting.
In one embodiment of this invention, the method for above-mentioned cutting transparency carrier comprises machine cuts or laser cutting.
In sum, in method for cutting wafer of the present invention,, therefore can promote the accuracy of cutting crystal wafer because the second contraposition mark or the first contraposition limit and the second contraposition limit all have preferable contraposition accuracy.
Description of drawings
Fig. 1 is the generalized section of known a kind of monocrystalline silicon LCD panel.
Fig. 2 A～2H is the process schematic diagram of the monocrystalline silicon LCD panel of construction drawing 1.
Fig. 3 is the local enlarged diagram of Fig. 2 E.
Fig. 4 A～Fig. 4 F is the schematic diagram according to the method for cutting wafer of first embodiment of the invention.
Fig. 4 G is the profile of transparency carrier behind the joint of Fig. 4 F and the wafer monomer after through the sliver processing procedure.
Fig. 5 A～Fig. 5 F is the schematic diagram according to the method for cutting wafer of second embodiment of the invention.
Embodiment
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
First embodiment
Fig. 4 A～Fig. 4 F is the schematic diagram according to the method for cutting wafer of first embodiment of the invention.Please refer to Fig. 4 A and Fig. 4 B, a wafer 21 and a transparency carrier 22 at first are provided, wherein wafer 21 has a plurality of driving component array location 21a and one first contraposition mark 21b, and transparency carrier 22 has zone, edge 22a.In this enforcement, these driving component array locations 21a arranges in the array mode, and the first contraposition mark 21b for example is a cross contraposition mark, to enable to locate the position of these driving component array locations 21a.But, the present invention does not limit form and the quantity of the first contraposition mark 21b.
Please continue the 4C with reference to figure, then transparency carrier 22 is engaged on the wafer 21, wherein the fringe region 22a of transparency carrier 22 protrudes from outside the wafer 21.In the present embodiment, the shape of transparency carrier 22 for example is square, and the area of transparency carrier 22 is the areas greater than wafer 21, and transparency carrier 22 is to cover whole wafer 21.But, spirit of the present invention is to be when joint transparency carrier 22 is on wafer 21, transparency carrier 22 has the outer fringe region 22a that protrudes from wafer 21, and the present invention is for the shape of transparency carrier 22, and any restriction is not all done in the zone that area size between transparency carrier 22 and the wafer 21 or transparency carrier 22 cover wafers 21.
Please continue 4D, follow with the first contraposition mark 21b as the reference mark, in the last one second contraposition mark 22b that forms of the fringe region 22a of transparency carrier 22, so that the second contraposition mark 22b also can locate the position of these driving component array locations 21a with reference to figure.In the present embodiment, the mode that forms the second contraposition mark 22b for example is to carry out the laser burning and form with laser machine at quarter (Laser Marker), and but, the mode that forms the second contraposition mark 22b is useful etch or other suitable manner forms also.In addition, the present invention does not also limit form and the quantity of the second contraposition mark 22b.
Although it should be noted that in abovementioned steps it is just to form the second contraposition mark 22b after being engaged in transparency carrier 22 on the wafer 21 earlier, but the present invention also can exchange the order of this two step.In detail, be after forming the second contraposition mark 22b on the transparency carrier 22, just engage transparency carrier 22 in wafer 21, wherein the zone at the second contraposition mark 22b place is to protrude outside the wafer 21.So, after determining second position of contraposition mark 22b, can utilize the second contraposition mark 22b to locate the position of these driving component array locations 21a with respect to the first contraposition mark 21b.
Please continue 4E with reference to figure, then with the first contraposition mark 21b as the reference mark, transparency carrier 22 is cut to form many line of cut L1 laterally and longitudinally, wherein line of cut L1 defines the regional extent of each driving component array location 21a.In the present embodiment, the present invention for example is to use as the cutter of resin cutter and cuts transparency carrier 22 in the mode of machine cuts, but the present invention also can adopt laser cutting or other suitable manner cutting transparency carrier 22.
Please continue 4F, with the transparency carrier 22 and wafer 21 turn-overs after engaging with reference to figure.Because transparency carrier 22 is light-permeables, can know that therefore the position that picks out the second contraposition mark 22b is for following cutter.Then with the second contraposition mark 22b as the reference mark, wafer 21 is cut to form many line of cut L2 laterally and longitudinally.Compared to known with irregular contraposition limit B (as shown in Figure 3) as with reference to mark, the second contraposition mark 22b of the present invention has higher accuracy, therefore can significantly promote the accuracy of cutting crystal wafer 21.
Accept above-mentioned, in the present embodiment, horizontal line of cut L2 for example with the position consistency of corresponding horizontal line of cut L1, and line of cut L2 has dislocation slightly with the corresponding L1 of line of cut longitudinally longitudinally.But, the present invention does not limit the relative position relation of line of cut L1 and line of cut L2, and need the arrange in pairs or groups layout designs of actual wafer 21 of the cutting position of line of cut L1 and line of cut L2.
In addition, the present invention for example is to use as the cutter of steel edge and with the mode cutting crystal wafer 21 of machine cuts, but the present invention also can adopt laser cutting or other suitable manner cutting crystal wafer 21.In addition, do not split, therefore can significantly reduce the consume of cutter and increase useful life of cutter because the present invention in the process with cutter cutting, does not all need wafer 21 or transparency carrier 22 directly cut.
Although it should be noted that in aforesaid step it is first cutting crystal wafer 21 just behind the cutting transparency carrier 22, but the present invention also can exchange the order of this two step.In addition, when cutting transparency carrier 22, the present invention also can cut the second contraposition mark 22b as the reference mark.
Fig. 4 G is the profile of transparency carrier 22 and wafer 21 behind the joint of Fig. 4 F monomer after through the sliver processing procedures.Please refer to Fig. 4 G, these driving component array locations 21a is separated promptly forming a plurality of monomers 200 in the mode of board sliver.In the present embodiment, driving component array location 21a for example is the thin-film transistor array location, and wherein each driving component array location 21a comprises a plurality of thin-film transistors 212 and the pixel electrode 214 (only showing a group in the diagram) that electrically connects with thin-film transistor 212.In addition, transparency carrier 22 for example is a conducting glass substrate, wherein transparency carrier 22 comprises a glass substrate 222 and a transparency conducting layer 224, and wherein this transparency conducting layer 224 is to be disposed on the glass substrate 222, and between glass substrate 222 and driving component array location 21a.After being poured into monomer 200, the liquid crystal molecule (not shown) seals the monocrystalline silicon LCD panel (not shown) that promptly completes.
But, method for cutting wafer of the present invention does not limit and can only be applied to make monocrystalline silicon LCD panel.For example, driving component array location 21a also can comprise a plurality of thin-film transistors and the organic electric-excitation luminescent material layer (Organic ElectroluminescentMaterial Layer) that electrically connects with thin-film transistor, so, the monomer behind the sliver is an organic electroluminescence panel.
Subsidiary one carry be, need with the manual type contraposition compared to known contraposition limit B (as shown in Figure 3), the second contraposition mark 22b of the present invention can use the automatic contraposition of automatic alignment system, so can accelerate to locate the speed of cutting crystal wafer 21, to promote whole efficiency.In addition, because the present invention significantly promotes the accuracy of cutting crystal wafer 21, so the quality of product is improved, and increases the whole yield of product.
Second embodiment
Fig. 5 A～Fig. 5 F is the schematic diagram according to the method for cutting wafer of second embodiment of the invention.The method for cutting wafer of present embodiment is similar to the method for cutting wafer shown in Fig. 2 A～2F, obscures for avoiding causing, and the member of same names can be represented with different labels in the diagram, but it still has identical function.Please refer to Fig. 5 A, a wafer 31 at first is provided, wherein wafer 31 has a plurality of driving component array location 31a and a contraposition mark 31b, and contraposition mark 31b is suitable for locating the position of these driving component array locations 31a.
Please continue 5B with reference to figure, then with the first contraposition mark 31b as the reference mark, the edge of wafer 31 cut splits to form one first contraposition limit B1 and one second contraposition limit B2.In the present embodiment, the direction of the first contraposition limit B1 can be vertically, and the direction of the second contraposition limit B2 can be laterally.After, the first contraposition limit B1 and the second contraposition limit B2 are polished processing procedure, with the leveling first contraposition limit B1 and the second contraposition limit B2, and the present invention carries out edging in the mode of grinding and polishing to the first contraposition limit B1 and the second contraposition limit B2.
Accept above-mentioned, because the present invention polishes processing procedure to the first contraposition limit B1 and the second contraposition limit B2, therefore the first contraposition limit B1 and the second contraposition limit B2 are smooth straight line, so, can have higher accuracy as the reference mark with the first contraposition limit B1 of the present invention and the second contraposition limit B2 compared to known irregular contraposition limit B (as shown in Figure 3).
Please continue with reference to figure 5C and 5D, a transparency carrier 32 then is provided, and transparency carrier 32 is engaged on the wafer 31.Please continue 5E with reference to figure, then with contraposition mark 31b as the reference mark, transparency carrier 32 is cut to form many line of cut L1 laterally and longitudinally, wherein line of cut L1 defines the regional extent of each driving component array location 31a.Subsidiary one carry be, this step of cutting can also the first contraposition limit B1 and the second contraposition limit B2 as the reference mark.
Please continue 5F, with the transparency carrier 32 and wafer 31 turn-overs after engaging with reference to figure.Because transparency carrier 32 is light-permeables, can know that therefore the position that picks out the first contraposition limit B1 and the second contraposition limit B2 is for following cutter.Then with the first contraposition limit B1 and the second contraposition limit B2 as the reference mark, wafer 31 is cut to form many line of cut L2 laterally and longitudinally.Because the first contraposition limit B1 and the second contraposition limit B2 as the reference mark have higher accuracy, therefore can significantly promote the accuracy of cutting crystal wafer 31.
In sum, method for cutting wafer of the present invention has following advantage at least:
One, owing to when cutting crystal wafer, have the higher contraposition mark of accuracy (as the second contraposition mark, the first contraposition limit or the second contraposition limit), therefore can promote the accuracy of cutting crystal wafer, and then promote product quality and yield as with reference to mark.
Two, the automatic contraposition of automatic alignment system can be used in the second contraposition mark of the present invention, the first contraposition limit or the second contraposition limit, so can increase the efficient of integral cutting, and reduces cost of labor.
Therefore three, in one embodiment, the present invention does not directly cut with cutter splits wafer, can reduce the consume of cutter and increases useful life of cutter.
Though the present invention describes as above with preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this technical staff; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the content that claim defines.
Claims (14)
1. method for cutting wafer comprises:
One wafer is provided, and this wafer has a plurality of driving component array locations and one first contraposition mark;
Engage a transparency carrier on this wafer, wherein this transparency carrier has zone, an edge, and this fringe region is to protrude from outside this wafer;
Form one second contraposition mark on this fringe region;
, as the reference mark this transparency carrier is cut with this first contraposition mark; And
, as the reference mark this wafer is cut with this second contraposition mark.
2. method for cutting wafer as claimed in claim 1, the method that wherein forms this second contraposition mark comprises the laser burning.
3. method for cutting wafer as claimed in claim 1, the method that wherein forms this second contraposition mark comprises etching.
4. method for cutting wafer as claimed in claim 1, wherein this driving component array location is a thin-film transistor array location.
5. method for cutting wafer as claimed in claim 1, wherein this transparency carrier is a conducting glass substrate, and this conducting glass substrate comprises a glass substrate and a transparency conducting layer, and wherein this transparency conducting layer is to be disposed on this glass substrate, and between this glass substrate and this wafer.
6. method for cutting wafer as claimed in claim 1, the method for wherein cutting this wafer comprises machine cuts or laser cutting.
7. method for cutting wafer as claimed in claim 1, the method for wherein cutting this transparency carrier comprises machine cuts or laser cutting.
8. method for cutting wafer comprises:
One wafer is provided, and this wafer has a plurality of driving component array locations and a contraposition mark;
, the edge of this wafer cut split as the reference mark with this contraposition mark to form one first contraposition limit and one second contraposition limit;
Processing procedure is polished on this first contraposition limit and this second contraposition limit;
Engage a transparency carrier on this wafer;
, as the reference mark this transparency carrier is cut with this contraposition mark; And
, as the reference mark this wafer is cut with this first contraposition limit and this second contraposition limit.
9. method for cutting wafer as claimed in claim 8, the method for wherein polishing this first contraposition limit and this second contraposition limit comprises grinding and polishing.
10. method for cutting wafer as claimed in claim 8, wherein the direction on this first contraposition limit is vertical with the direction on this second contraposition limit.
11. method for cutting wafer as claimed in claim 8, wherein this driving component array location is a thin-film transistor array location.
12. method for cutting wafer as claimed in claim 8, wherein this transparency carrier is a conducting glass substrate, and this conducting glass substrate comprises a glass substrate and a transparency conducting layer, and wherein this transparency conducting layer is to be disposed on this glass substrate, and between this glass substrate and this wafer.
13. method for cutting wafer as claimed in claim 8, the method for wherein cutting this wafer comprises machine cuts or laser cutting.
14. method for cutting wafer as claimed in claim 8, the method for cutting this transparency carrier comprises machine cuts or laser cutting.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2006100994224A CN100514602C (en) | 2006-07-18 | 2006-07-18 | Wafer cutting method |
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| CNB2006100994224A CN100514602C (en) | 2006-07-18 | 2006-07-18 | Wafer cutting method |
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| CN101110390A true CN101110390A (en) | 2008-01-23 |
| CN100514602C CN100514602C (en) | 2009-07-15 |
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| CNB2006100994224A Expired - Fee Related CN100514602C (en) | 2006-07-18 | 2006-07-18 | Wafer cutting method |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101834160A (en) * | 2010-04-23 | 2010-09-15 | 浙江大学 | Multi-project wafer cutting method for improving finished product rate of chips |
| CN101986427A (en) * | 2009-07-28 | 2011-03-16 | 台湾积体电路制造股份有限公司 | Semiconductor wafer having pre-aligning pattern and method for pre-aligning the same |
| CN102130050A (en) * | 2011-01-05 | 2011-07-20 | 杭州广立微电子有限公司 | Multi-project wafer cutting method supporting constraint and limitation on positions of chips |
| CN101226887B (en) * | 2008-02-15 | 2012-08-29 | 日月光半导体制造股份有限公司 | Method for cutting chip |
| CN105321864A (en) * | 2014-07-17 | 2016-02-10 | 东和株式会社 | Method and device for cutting substrate |
| CN105974627A (en) * | 2016-05-11 | 2016-09-28 | 豪威半导体（上海）有限责任公司 | LCOS display panel and manufacture method thereof |
| CN107632444A (en) * | 2017-11-02 | 2018-01-26 | 上海天马微电子有限公司 | Special-shaped display panel and its manufacture method and display device |
| CN109742065A (en) * | 2018-12-25 | 2019-05-10 | 惠科股份有限公司 | A kind of display panel and the method and display device for cutting its mother substrate |
| CN111660014A (en) * | 2020-06-09 | 2020-09-15 | 上海申和热磁电子有限公司 | Method for improving laser cutting precision of DBC substrate from back side |
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2006
- 2006-07-18 CN CNB2006100994224A patent/CN100514602C/en not_active Expired - Fee Related
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101226887B (en) * | 2008-02-15 | 2012-08-29 | 日月光半导体制造股份有限公司 | Method for cutting chip |
| CN101986427A (en) * | 2009-07-28 | 2011-03-16 | 台湾积体电路制造股份有限公司 | Semiconductor wafer having pre-aligning pattern and method for pre-aligning the same |
| CN101834160A (en) * | 2010-04-23 | 2010-09-15 | 浙江大学 | Multi-project wafer cutting method for improving finished product rate of chips |
| CN102130050A (en) * | 2011-01-05 | 2011-07-20 | 杭州广立微电子有限公司 | Multi-project wafer cutting method supporting constraint and limitation on positions of chips |
| CN102130050B (en) * | 2011-01-05 | 2012-12-19 | 杭州广立微电子有限公司 | Multi-project wafer cutting method supporting constraint and limitation on positions of chips |
| CN105321864A (en) * | 2014-07-17 | 2016-02-10 | 东和株式会社 | Method and device for cutting substrate |
| CN105321864B (en) * | 2014-07-17 | 2018-01-16 | 东和株式会社 | Substrate cut and substrate cutting method |
| CN105974627A (en) * | 2016-05-11 | 2016-09-28 | 豪威半导体（上海）有限责任公司 | LCOS display panel and manufacture method thereof |
| CN107632444A (en) * | 2017-11-02 | 2018-01-26 | 上海天马微电子有限公司 | Special-shaped display panel and its manufacture method and display device |
| CN109742065A (en) * | 2018-12-25 | 2019-05-10 | 惠科股份有限公司 | A kind of display panel and the method and display device for cutting its mother substrate |
| CN109742065B (en) * | 2018-12-25 | 2020-10-16 | 惠科股份有限公司 | Display panel, method for cutting mother substrate of display panel and display device |
| CN111660014A (en) * | 2020-06-09 | 2020-09-15 | 上海申和热磁电子有限公司 | Method for improving laser cutting precision of DBC substrate from back side |
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|---|---|
| CN100514602C (en) | 2009-07-15 |
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