CN101107778A - Device comprising a latch - Google Patents
Device comprising a latch Download PDFInfo
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- CN101107778A CN101107778A CNA2006800032237A CN200680003223A CN101107778A CN 101107778 A CN101107778 A CN 101107778A CN A2006800032237 A CNA2006800032237 A CN A2006800032237A CN 200680003223 A CN200680003223 A CN 200680003223A CN 101107778 A CN101107778 A CN 101107778A
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- latch
- transistor
- main electrode
- equipment
- tracking
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
- H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
- H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
- H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
- H03K3/288—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable using additional transistors in the input circuit
- H03K3/2885—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable using additional transistors in the input circuit the input circuit having a differential configuration
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Abstract
Devices (101-105) comprising latches (1-3) with tracking circuits (4) for, in tracking modes, tracking data signals and with deciding circuits (5) for, in deciding modes, deciding about the data signal can use their available time more efficiently by, in the tracking modes, preparing the deciding circuits (5). Thereto, the deciding circuits (5) are not to be switched between disabled/enabled situations, but are to be kept enabled. The tracking circuits (4), in the tracking modes, supply signal values derived from the data signals to the deciding circuits (5), and the deciding circuits (5), in the deciding modes, amplify the signal values. The tracking circuits (4) comprise diodes (21,22) to allow reduced voltage swings in the data signals to be sufficient for proper performances of the latch (1-3). Such reduced voltage swings allow the latches (1-3) to perform at higher speeds. The parasitic capacitors present between the cathodes of the diodes (21,22) form capacitances for storing the signal values and allow the deciding circuits (5) to be prepared.
Description
Technical field
The present invention relates to comprise the equipment of latch, and relate to latch, and relate to a kind of method.
The example of this equipment is such as modules such as divider, shift register, maker, multiplexer, demodulation multiplexer, phase-locked loop and the consumer products that comprise this module, and the example of this latch is so-called D-type latch.
Background technology
From Payam Heydari and Ravi Mohavavelu at ISCAS 03, Proceedingof the 2003 International Symposium on Cricuits and Systems (2003 international circuits and system's discussion annual report), volume 2, in May, 2003 25-28,0-7803-7761-3/03/$17.00 can know prior art equipment in the article of 2003IEEE " Design of Ultra HighSpeed CMOS CML buffers and latches (ultrahigh speed CMOS CML buffer and latch) ", this article disclosed latch in its Fig. 6 comprises input TRL tracing level (transistor MN1, MN2), be used for tracking data variation under tracing mode; And comprise latch to (transistor MN3, MN4), be used for these data of storage under latch mode.By offering differential the clock signal of (transistor MN5, MN6) is determined to follow the tracks of and latch mode.Under tracing mode, will import that TRL tracing level activates and with latch to forbidding; And under latch mode, also almost latch is right to forbid importing TRL tracing level.
This known device has drawback, and particularly, the relative poor efficiency of latch ground uses up duration.This be because latch needs are switched to state of activation from illegal state, and at this latch of illegal state to not doing anything.
Summary of the invention
An object of the present invention is to provide and comprise the equipment that uses the latch of up duration relatively efficiently.
Other purpose of the present invention provide use relatively efficiently can the time latch and method.
Equipment according to the present invention comprises latch, and this latch comprises tracking circuit, is used for tracking data signal under tracing mode; This latch comprises decision circuit, is used at decision pattern this data-signal that acts; This latch allows this decision circuit get ready under tracing mode.
By allowing this decision circuit (latch cicuit) get ready under tracing mode, this latch uses up duration more efficiently.In order to allow this decision circuit get ready, this decision circuit does not switch between illegal state and state of activation, but remains under the state of activation.
Qualification according to the embodiment of equipment of the present invention is characterised in that: tracking circuit offers decision circuit at following signal value of deriving from data-signal of tracing mode, and this decision circuit amplifies this signal value under decision pattern.Under tracing mode, this decision circuit has low relatively or is zero multiplication factor, and under decision pattern, this decision circuit has high relatively multiplication factor.
Qualification according to the embodiment of equipment of the present invention is characterised in that: tracking circuit comprises the electric capacity that is used to store this signal value.This capacitance stores signal value also is notified to decision circuit with this signal value.
Qualification according to the embodiment of equipment of the present invention is characterised in that: this decision circuit comprises the first transistor and transistor seconds, first main electrode of this first transistor and transistor seconds is connected to each other, and first and second transistorized second main electrodes separately are connected respectively to second and the first transistor control electrode separately.This structure is commonly called latch cicuit or latch is right.
Qualification according to the embodiment of equipment of the present invention is characterised in that: this tracking circuit comprises first diode and second diode, first main electrode of this first and second diode is connected to each other, first and second diodes, second main electrode separately is connected respectively to first and second transistors control electrode separately, and constitutes first and second data input pins of latch respectively.This is a kind of favourable structure, because compared with prior art, between the data input pin of latch, voltage swing is reduced to the superperformance that is enough to realize latch.This voltage swing that reduces allows this latch to carry out with higher speed.Capacitor parasitics is formed for the electric capacity of storage signal value between second main electrode of two diodes.First and second data input pins of this latch are respectively for example D+ and D-input (poised state), and receive data-signal.
Qualification according to the embodiment of equipment of the present invention is characterised in that: first and second diodes, second main electrode separately is through respectively via first and second resistance and be connected to voltage source via first and second current sources respectively.These current sources are by the electric current according to temperature auto-adjusting circuit source, thereby the performance that can compensate under higher temperature reduces.
Qualification according to the embodiment of equipment of the present invention is characterised in that: first and second transistors control electrode separately is connected respectively to third and fourth transistor control electrode separately, third and fourth transistorized first main electrode is connected to each other, and third and fourth transistor, second main electrode separately constitutes first and second data output ends of latch respectively.First and second data output ends of this latch are respectively for example Q-and Q+ output (poised state), and generate output signal.
Qualification according to the embodiment of equipment of the present invention is characterised in that: first and second transistors control electrode separately is connected respectively to the 5th and the 6th transistor control electrode separately, the the 5th and the 6th transistorized first main electrode is connected to each other, and the 5th and the 6th transistor second main electrode separately is connected to voltage source via third and fourth resistance respectively, and constitutes third and fourth data output end of this latch respectively.Third and fourth data output end of this latch is respectively for example OUT-and OUT+ output (poised state), and generates further output signal.These outputs and this data input pin are separated by and are left, thereby prevent from the parasitic capacitance of load is loaded on this latch.
Qualification according to the embodiment of equipment of the present invention is characterised in that: first and second diodes, second main electrode separately is respectively via first and second resistance and be connected to voltage source via the 5th and the 6th resistance respectively, the common point of this first and the 5th resistance has constituted the 3rd data output end of this latch, and the common point of the second and the 6th resistance has constituted the 4th data output end of this latch.The the 5th and the 6th resistance has replaced this current source, and compares with the embodiment with current source, makes between the data input pin of latch to have the voltage swing that further reduces, thereby realizes the superperformance of this latch.This voltage swing that further reduces allows this latch to carry out with higher speed.
Qualification according to the embodiment of equipment of the present invention is characterised in that: first main electrode of diode further is connected to the 7th transistorized second main electrode, the 7th transistor first main electrode ground connection, and the 7th transistorized control electrode has constituted first input end of clock of this latch, third and fourth transistorized first main electrode further is connected to the 8th transistorized second main electrode, the 8th transistorized first main electrode ground connection, and the 8th transistorized control electrode has constituted the second clock input of this latch.This first input end of clock for example is the CK+ input, and this second clock input for example is the CK-input (poised state) that is used for the receive clock signal.Cause this latch to enter tracing mode or enter decision pattern at the clock input signal of these input end of clock.
Qualification according to the embodiment of equipment of the present invention is characterised in that: first and second transistorized first main electrodes further are connected to the 9th transistorized second main electrode, the 9th transistorized first main electrode ground connection, and the 9th transistorized control electrode is connected to the second clock input of this latch.Compare with the embodiment of the first and second transistorized first main electrode ground connection, this connection allows the decision circuit timing, is favourable under this situation for this latch of use in multiplexer or maker environment.
According to the embodiment of the embodiment of latch of the present invention and the method according to this invention corresponding to embodiment according to equipment of the present invention.This does not get rid of the additional embodiments that relates to nonequilibrium condition.
The starting point of the present invention is: connect and cut off that decision circuit is cut or latch cicuit needs spended time.Basic thought of the present invention is: as under decision pattern, under tracing mode, be not decision circuit is kept forbidding but to keep activation.
The problem that the present invention solves is: provide to comprise the equipment that uses the latch of up duration relatively efficiently.It is advantageous that: can use this latch with higher speed.
Below in conjunction with embodiment these and other aspect of the present invention is described in detail.
Description of drawings
In the accompanying drawings:
Fig. 1 shows briefly according to equipment of the present invention, and this equipment comprises according to latch of the present invention.
Fig. 2 shows briefly according to equipment of the present invention, and this equipment comprises according to latch of the present invention.
Fig. 3 shows briefly according to equipment of the present invention, and this equipment comprises according to latch of the present invention.
Fig. 4 shows according to equipment of the present invention briefly with the form of divider, and this divider comprises according to two latchs of the present invention.
Fig. 5 shows according to equipment of the present invention briefly with the form of d type flip flop, and this d type flip flop comprises according to two latchs of the present invention.
Embodiment
Tracking circuit 4 comprises first diode 21 and second diode 22, first main electrode (anode) of this first and second diode 21,22 is connected to each other, and this first and second diode 21,22 second main electrode (negative electrode) separately is connected respectively to first and second transistors 11,12 control electrode separately, and constitute first and second data input pins 31,32 (D+, D-) of latch 1 respectively, be used to receive data-signal.First diode 21 and second diode 22 in fact are collector electrode and base stage transistor connected to one another.
First and second diodes 21,22, second main electrode separately also is connected to voltage source 40 via first and second current sources 25,26 respectively via first and second resistance 23,24 respectively.
First and second transistors 11,12 control electrode separately is connected respectively to third and fourth transistor 13,14 control electrode (base stage) separately, first main electrode (electrode) of third and fourth transistor 13,14 is connected to each other, third and fourth transistor 13,14, second main electrode (collector electrode) separately constitutes first and second data output ends 33,34 (Q-, Q+) of latch 1 respectively, is used to generate output signal.
First and second transistors 11,12 control electrode separately is connected respectively to the 5th and the 6th transistor 15,16 control electrode (base stage) separately, first main electrode (electrode) of the 5th and the 6th transistor 15,16 is connected to each other, the the 5th and the 6th transistor 15,16 second main electrode (collector electrode) separately is connected to power supply 40 via third and fourth resistance 27,28 respectively, and constitute third and fourth data output end 35,36 (OUT-, OUT+) of latch 1 respectively, be used to generate further output signal.
First main electrode of first and second transistors 11,12 further is connected to second main electrode (collector electrode) of the 9th transistor 19, first main electrode (emitter) ground connection of the 9th transistor 19, the control electrode of the 9th transistor 19 (base stage) is connected to the second clock input 38 of latch 2.
Replaced current source 25,26 with the 5th and the 6th resistance 29,30, the common point of the first and the 5th resistance 23,29 has constituted the 3rd data output end (OUT-) of latch 3, and the common point of the second and the 6th resistance 24,30 has constituted the 4th data output end 36 (OUT+) of latch 3.
Latch 1-3 allows this decision circuit 5 get ready under tracing mode, and is for example as follows.Tracking circuit 4 offers decision circuit 5 to the signal value of deriving from the data-signal that offers data input 31,32 under tracing mode, decision circuit 5 issues big this signal value at decision pattern.This signal value for example is a stored voltage on the electric capacity of tracking circuit 4.For example, realize this electric capacity via the capacitor parasitics between the negative electrode that appears at diode 21,22.
Therefore, by allowing decision circuit 5 get ready under tracing mode, latch 1-3 uses up duration more efficiently.In order to allow this decision circuit 5 get ready, decision circuit 5 does not switch between illegal state and state of activation, but remains in the state of activation.
The tracking circuit 4 that comprises diode 21,22 has formed favourable structure, and this is that the voltage swing between the data input pin 31,32 of latch 1-3 has been reduced to the superperformance that is enough to realize latch 1-3 because compared with prior art.This voltage swing that reduces allows to carry out latch 1-3 with higher speed.
Current source shown in Fig. 1 and 2 is by regulating the electric current of current source automatically according to temperature, the performance that can compensate under the higher temperature reduces.
As illustrated in fig. 1 and 2, output 35,36 and data input pin 31,32 are kept apart, thereby prevent from the parasitic capacitance of load is loaded on this latch 1,2.
The the 5th and the 6th resistance 29,30 shown in Figure 3 replaces the current source 25,26 of Fig. 1 and 2, compare with embodiment with current source 25,26, between the data input pin 31,32 of latch 3 voltage swing that further reduces is arranged, thereby realize the superperformance of latch 3.This voltage swing that further reduces can make latch 3 carry out with higher speed.
The clock input signal that is used to offer input end of clock 37,38 causes latch 1-3 to enter tracing mode or enters decision pattern.
Fig. 4 comprises two latch 1-3 with the equipment 104 according to the present invention shown in the form of frequency divider (two-divider or pre-divider), wherein the output of first latch is connected to the input of second latch, and the output of second latch feeds back to the input of first latch.
Fig. 5 comprises two latch 1-3 with the equipment 105 according to the present invention shown in the form of d type flip flop, and wherein the output of first latch is connected to the input of second latch, and nowadays the output of second latch does not feed back to the input of first latch.But the input of first latch forms the input of d type flip flop, and the output of second latch forms the output of d type flip flop.
Shown transistor is the NPN bipolar transistor, replacedly can use the PNP bipolar transistor, replacedly can also make field-effect transistors, for example NMOS or PMOS transistor.Do not get rid of the further embodiment that relates to nonequilibrium condition.
Should be understood that the foregoing description is used for explanation and unrestricted the present invention, and under the prerequisite of the protection range that does not break away from claims, those of ordinary skills can design multiple substituting embodiment.In the claims, any mark in the round parentheses should be interpreted as limiting this claim.Use verb " to comprise " and be out of shape not get rid of outside listed parts of claim or the step and also have other parts or step.The article of parts front " one " is not got rid of and is had a plurality of such parts.The present invention can realize by the hardware that comprises a plurality of different parts, also can realize by the computer of suitable programmed.In having enumerated the device claim of a plurality of modules, a plurality of in these modules can specific implementation be an identical hardware.Though some means is to put down in writing in mutually different dependent claims, only this fact does not represent that these means combine and do not have advantage.
Claims (13)
1. the equipment (101-105) that comprises latch (1-3), described latch (1-3) comprise tracking circuit (4) and decision circuit (5),
Described tracking circuit (4) tracking data signal under tracing mode,
Described decision circuit (5) is at the decision pattern described data-signal that acts,
Described latch (1-3) allows described decision circuit (5) get ready under tracing mode.
2. equipment as claimed in claim 1 (101-105),
Described tracking circuit (4) offers described decision circuit (5) at following signal value of deriving from described data-signal of tracing mode,
Described decision circuit (5) amplifies described signal value under decision pattern.
3. equipment as claimed in claim 2 (101-105), described tracking circuit (4) comprises the electric capacity that is used to store described signal value.
4. equipment as claimed in claim 1 (101-105), described decision circuit (5) comprises the first transistor (11) and transistor seconds (12), first main electrode of described first and second transistors (11,12) is connected to each other, and described first and second transistors (11,12) second main electrode separately is connected respectively to described second and the first transistor (11,12) control electrode separately.
5. equipment as claimed in claim 4 (101-105), described tracking circuit (4) comprises first diode (21) and second diode (22), first main electrode of described first and second diodes (21,22) is connected to each other, described first and second diodes (21,22) second main electrode separately is connected respectively to described first and second transistors (11,12) control electrode separately, and constitutes first and second data input pins (31,32) of described latch (1-3) respectively.
6. equipment as claimed in claim 5 (101-105), described first and second utmost point pipes (21,22) second main electrode separately via first and second resistance (23,24) and respectively via first and second current sources (25,26), is connected to voltage source (40) respectively.
7. equipment as claimed in claim 5 (101-105), described first and second transistors (11,12) control electrode separately is connected respectively to third and fourth transistor (13,14) control electrode separately, first main electrode of described third and fourth transistor (13,14) is connected to each other, and described third and fourth transistor (13,14) second main electrode separately constitutes first and second data output ends (33,34) of described latch (1-3) respectively.
8. equipment as claimed in claim 7 (101-105), described first and second transistors (11,12) control electrode separately is connected respectively to the 5th and the 6th transistor (15,16) control electrode separately, first main electrode of the described the 5th and the 6th transistor (15,16) is connected to each other, the the described the 5th and the 6th transistor (15,16) second main electrode separately is connected to voltage source (40) via third and fourth resistance (27,28) respectively, and constitutes third and fourth data output end (35,36) of described latch (1-3) respectively.
9. equipment as claimed in claim 7 (101-105), described first and second diodes (21,22) second main electrode separately also is connected to voltage source (40) via the 5th and the 6th resistance (29,30) respectively via first and second resistance (23,24) respectively, the common point of the described first and the 5th resistance (23,29) constitutes the 3rd data output end (35) of described latch (1-3), and the common point of the described second and the 6th resistance (24,30) constitutes the 4th data output end (36) of described latch (1-3).
10. equipment as claimed in claim 7 (101-105), described diode (21,22) first main electrode further is connected to second main electrode of the 7th transistor (17), the first main electrode ground connection of described the 7th transistor (17), the control electrode of described the 7th transistor (17) constitutes first input end of clock (37) of described latch (1-3), described third and fourth transistor (13,14) first main electrode further is connected to second main electrode of the 8th transistor (18), the first main electrode ground connection of described the 8th transistor (18), the control electrode of described the 8th transistor (18) constitute the second clock input (38) of described latch (1-3).
11. equipment as claimed in claim 10 (101-105), first main electrode of described first and second transistors (11,12) further is connected to second main electrode of the 9th transistor (19), the first main electrode ground connection of described the 9th transistor (19), the control electrode of described the 9th transistor (19) are connected to the second clock input (38) of described latch (1-3).
12. comprise the latch (1-3) of tracking circuit (4) and decision circuit (5),
Described tracking circuit (4) tracking data signal under tracing mode,
Described decision circuit (5) is at the decision pattern described data-signal that acts,
Described latch (1-3) allows described decision circuit (5) get ready under tracing mode.
13. be used for the method for latch data signal, it comprises:
Tracking step, tracking data signal under tracing mode,
Decision steps, at the decision pattern described data-signal that acts,
Preparation process allows described decision steps get ready under tracing mode.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP05100549.4 | 2005-01-28 | ||
| EP05100549 | 2005-01-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101107778A true CN101107778A (en) | 2008-01-16 |
Family
ID=36616831
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2006800032237A Pending CN101107778A (en) | 2005-01-28 | 2006-01-23 | Device comprising a latch |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP1844548A2 (en) |
| JP (1) | JP2008529391A (en) |
| CN (1) | CN101107778A (en) |
| WO (1) | WO2006079966A2 (en) |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5912661A (en) * | 1982-07-13 | 1984-01-23 | Fujitsu Ltd | Variable threshold value type differential signal receiver |
| US4622475A (en) * | 1984-03-05 | 1986-11-11 | Tektronix, Inc. | Data storage element having input and output ports isolated from regenerative circuit |
| JP2621311B2 (en) * | 1988-03-10 | 1997-06-18 | 日本電気株式会社 | Comparator with latch circuit |
| EP0417334B1 (en) * | 1989-09-11 | 1993-12-29 | Siemens Aktiengesellschaft | Latch circuit with switching hysterisis |
| JPH06101671B2 (en) * | 1989-09-27 | 1994-12-12 | 株式会社東芝 | Voltage comparison circuit |
| US5347175A (en) * | 1992-05-12 | 1994-09-13 | The United States Of America As Represented By The Secretary Of Commerce | Voltage comparator with reduced settling time |
-
2006
- 2006-01-23 EP EP06710725A patent/EP1844548A2/en not_active Withdrawn
- 2006-01-23 CN CNA2006800032237A patent/CN101107778A/en active Pending
- 2006-01-23 JP JP2007552777A patent/JP2008529391A/en not_active Withdrawn
- 2006-01-23 WO PCT/IB2006/050242 patent/WO2006079966A2/en active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| EP1844548A2 (en) | 2007-10-17 |
| JP2008529391A (en) | 2008-07-31 |
| WO2006079966A3 (en) | 2006-10-12 |
| WO2006079966A2 (en) | 2006-08-03 |
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| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
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