CN101106359A - Mutual resistance amplifier - Google Patents
Mutual resistance amplifier Download PDFInfo
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- CN101106359A CN101106359A CNA2006100616860A CN200610061686A CN101106359A CN 101106359 A CN101106359 A CN 101106359A CN A2006100616860 A CNA2006100616860 A CN A2006100616860A CN 200610061686 A CN200610061686 A CN 200610061686A CN 101106359 A CN101106359 A CN 101106359A
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Abstract
A transresistance amplifier which is used to transform current signal into voltage signal is provided. The monopole amplifying circuit comprises a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein the grids connections of the first transistor and the second transistor act as the input terminals for signals; the drains of the first two transistors are connected with each other; the source of the first transistor is earthed; the source of the second transistor is connected with the first power supply; the grid and the source of the third transistor, the source of the fourth transistor are connected with the source of the second transistor; the drains connection between the third, the fourth transistors and the second transistor act as the output terminals for signals; the grid of the fourth transistor is earthed. When the photodiode connected with the transresistance amplifier transforms optical signal into current signal and input the current signal into the transresistance amplifier, the third transistor and the fourth transistor can improve the photoelectric conversion efficiency of the photodiode by increasing the current of the first transistor. The invention has high bandwidth, high stability, and no influence of external environmental factors.
Description
Technical Field
The invention relates to the field of photoelectricity, in particular to a transimpedance amplifier.
Background
An Optical Pick-UP (OPU) of a digital video disk (DVD, VCD, etc.) is one of the major components of an Optical storage system, which requires a Photo Detector Integrated Circuit (PDIC) to integrate an Optical receiver, control and feedback circuitry on the same chip for Optical signal detection, photo-electric signal conversion and signal amplification.
Fig. 1 is a schematic diagram of a DVD photodetection integrated circuit structure in the prior art. Wherein, A, B, C, D, E and F are six photodiodes for detecting the reflected light signal of the disk and converting into weak current signal by photoelectric effect, thereby reading the information of the disk and the focusing and tracking servo control signals. Each channel connected with the six photodiodes mainly consists of a preamplification circuit and is used for amplifying weak current signals and converting current into output voltage signals. Complementary Metal-Oxide Semiconductor (CMOS) amplifiers used in photodetection integrated circuits, hereinafter referred to as CMOS amplifiers, are mainly of three types: a low impedance amplifier, a high impedance amplifier, and a trans-impedance amplifier. Low impedance amplifiers are less useful due to lower performance. High impedance amplifiers are the most sensitive of these three configurations, but require additional circuitry and limit the dynamic range and dc response of the system. Transimpedance amplifiers are most commonly used because they are simple and are designed in two stages for lower voltage bias in typical applications.
Fig. 2 is a schematic diagram of a prior art optoelectronic integrated circuit employing a CMOS transimpedance amplifier. The photodiode 2 in the optoelectronic integrated circuit 100 receives the reflected light signal of the detection disk and generates an input current I in The transimpedance amplifier 1 converts an input current into a voltage signal V out . The transimpedance amplifier 1 provides a higher bandwidth but the additional noise reduces its sensitivity. The performance of a transimpedance amplifier is measured mainly by: equivalent input current noise, frequency response characteristics, stability and the like.
Fig. 3 is a schematic circuit diagram of the CMOS transimpedance amplifier 1 in fig. 2. The CMOS transimpedance amplifier 1 comprises three-stage CMOS phase inverters composed of PMOS tubes M3, M6 and M9 and NMOS tubes M1, M2, M4, M5, M7 and M8, and a transimpedance R fb Forming a feedback loop. By NMOSThe single-stage inverter composed of the transistors M1 and M2 and the PMOS transistor M3 is illustrated. The open-loop direct-current gain of the single-stage inverter of the circuit is defined as follows:
meanwhile, the width-to-length ratio of the NMOS transistors M1 and M2 to the PMOS transistor M3 is defined as:
from FIG. 3, it can be seen that: due to mutual resistance R fb The feedback loop is formed to enable the voltage of the output node to be equal to the voltage of the input node, the MOS tube works in a saturation region, and therefore the transconductance value is as follows:
g m ＝2I d /(V gs -V T ) (3)
it was therefore concluded that:
the current of the PMOS transistor M3 flows into the NMOS transistors M1 and M2, and therefore:
by combining the above two formulas (4) and (5), the following can be obtained:
the direct current gain of the single-stage amplifier is obtained by the formula (6), and mainly depends on NMOS transistors M1 and M2 and a PMOS transistor M3, and the ratio of the width-to-length ratio of the NMOS transistor M2 is irrelevant to the width and length of other MOS transistors.
Thus, assuming the three-level CMOS inverter configuration is the same, the open loop gain of the three-level CMOS inverter is
Thus, the bandwidth of the transimpedance amplifier is:
wherein C is T Is the parallel value of the capacitance of the photodiode and the input stage parasitic capacitance of the amplifier.
However, the circuit of such a CMOS transimpedance amplifier 1 has the drawback that, given the bandwidth of the CMOS transimpedance amplifier 1, the transimpedance R is such that the maximum sensitivity is obtained fb Taking the maximum value, obtaining A from formula (7) 0 A maximum value is also taken. But gain A 0 The value of (A) is limited by a stability factor 0 The increase of (b) causes the higher order pole to move toward the origin, thereby reducing the phase margin. The bandwidth of the circuit of the CMOS transimpedance amplifier 1 is susceptible to external environmental factors such as power supply and process parametersThe number, etc. of the sample. With only one feedback resistor R in the feedback loop fb A large resonance peak may occur in the frequency response, and the circuit stability is poor when the signal frequency is high. Referring also to fig. 4, there is shown a simulation of the output frequency response and output pulse voltage of the given circuit of fig. 2. As can be seen in fig. 4: the circuit is less stable due to external factors, and thus has a large fluctuation in frequency response.
Disclosure of Invention
The invention aims to provide a high-bandwidth mutual resistance amplifier with high circuit stability.
A transresistance amplifier for converting a current signal into a voltage signal, the single-stage amplification circuit comprising: a first transistor and a second transistor, wherein the gates of the first and second transistors are connected as input terminals for inputting signals, the drains thereof are connected to each other, the source of the first transistor is grounded, the source of the second transistor is connected to a first power supply, wherein the single-stage amplification circuit further comprises: the grid electrode and the source electrode of the third transistor, the source electrode of the fourth transistor are connected with the source electrode of the second transistor, the drain electrodes of the third transistor and the fourth transistor are connected with the drain electrode of the second transistor to serve as output ends for outputting signals, the grid electrode of the fourth transistor is grounded, and when the photodiode connected with the mutual resistance amplifier converts optical signals into current signals and inputs the current signals into the mutual resistance amplifier, the third transistor and the fourth transistor can increase the photoelectric conversion efficiency of the photodiode by increasing the current of the first transistor.
The first improvement of the transimpedance amplifier of the present invention is that: the first transistor is an NMOS transistor and the second, third and fourth transistors are PMOS transistors.
A second improvement of the transimpedance amplifier of the present invention is: the transimpedance amplifier comprises a feedback network, the feedback network comprises a fifth transistor, the grid electrode of the fifth transistor is grounded, the source electrode and the drain electrode of the fifth transistor are respectively connected with the output end and the input end, and the fifth transistor can guarantee the stability of the output voltage of the transimpedance amplifier.
A third improvement of the inventive transimpedance amplifier is: the fifth transistor is a PMOS transistor.
A fourth improvement of the transimpedance amplifier of the present invention is that: the feedback network also comprises a first capacitor, two ends of the first capacitor are respectively connected with the input end and the output end of the transimpedance amplifier, and the first capacitor can flatten the frequency response of the transimpedance amplifier.
A fifth improvement of the transimpedance amplifier of the present invention is that: the feedback network also comprises a parasitic capacitance compensation module, the parasitic capacitance compensation module comprises a sixth transistor, a seventh transistor and a second capacitor, the grid electrode of the sixth transistor is connected with the input end of the transimpedance amplifier, the source electrode of the sixth transistor is connected with the output end of the transimpedance amplifier, and the drain electrode of the sixth transistor is connected with one end of the second capacitor; the grid of the seventh transistor is connected with the output end of the mutual resistance amplifier, the source electrode of the seventh transistor is grounded, the drain electrode of the seventh transistor is connected with the other end of the second capacitor, and the parasitic capacitor compensation module can enable the mutual resistance amplifier to obtain enough phase margin so as to keep the circuit stable.
A sixth improvement of the transimpedance amplifier of the present invention resides in: the sixth transistor and the seventh transistor are both PMOS transistors.
A seventh improvement of the transimpedance amplifier of the present invention is that: the two ends of the second capacitor are connected with a second voltage source.
An eighth improvement of the transimpedance amplifier of the present invention is that: the transimpedance amplifier adopts a 0.6 mu mCMOS process.
A ninth improvement of the transimpedance amplifier of the present invention is: the equivalent resistance value of the fifth transistor is 12k Ω, the first to seventh transistors are all the smallest channel lengths, and the value of the first capacitor is 1pf.
Compared with the prior art, the third transistor and the fourth transistor can increase the voltage of the input end, so that the reverse voltage between the positive electrode and the negative electrode of the photodiode connected with the transimpedance amplifier is increased, and the photoelectric conversion efficiency of the photodiode is improved. Whereas the bandwidth of the prior art circuit of fig. 3 is susceptible to power and process parameter fluctuations, the present invention eliminates these external environmental factors by adding a fourth transistor. According to the invention, by adding the second capacitor and the parasitic capacitor compensation module in the feedback loop, a flatter frequency response can be obtained, so that the stability of the circuit is improved.
Drawings
Fig. 1 is a schematic diagram of a prior art DVD photodetection integrated circuit structure.
Fig. 2 is a schematic diagram of a prior art optoelectronic integrated circuit employing a CMOS transimpedance amplifier.
Fig. 3 is a schematic circuit diagram of the CMOS transimpedance amplifier 1 in fig. 2.
Fig. 4 is a simulation schematic diagram of the output frequency response and the output pulse voltage of the given circuit of fig. 2.
FIG. 5 is a schematic diagram of a structure of an optoelectronic integrated circuit employing a CMOS transimpedance amplifier according to the present invention.
Fig. 6 is a schematic circuit diagram of the transimpedance amplifier 10 in fig. 5.
Fig. 7 is a schematic diagram of a specific structure of the parasitic capacitance compensation module 81 in fig. 6.
Fig. 8 is a schematic diagram of the output frequency response and output pulse voltage simulation of fig. 6.
Detailed Description
The invention is further described with reference to the following drawings and detailed description.
Referring to fig. 5, a schematic diagram of a structure of an optoelectronic integrated circuit using the CMOS trans-impedance amplifier of the present invention is shown. The optoelectronic integrated circuit 200 comprises a photodiode 20 and a transimpedance amplifier 10 comprising a feedback network 8, the optoelectronic integrated circuitThe diode 20 receives the reflected light signal of the detection disc and generates an input current I in The transimpedance amplifier 10 converts an input current into a voltage signal V out 。
Referring to fig. 6 and 7 together, fig. 6 is a schematic circuit diagram of the transimpedance amplifier 10 in fig. 5. Fig. 7 is a schematic diagram of a specific structure of the parasitic capacitance compensation module 81 in fig. 6. The transimpedance amplifier 10 comprises a three-stage CMOS inverter and a feedback network 8. The first stage CMOS inverter 5 comprises an NMOS transistor M11 and PMOS transistors M12, M13 and M14, wherein the source electrodes and the drain electrodes of the PMOS transistors M12, M13 and M14 are respectively connected, the corresponding source electrodes are connected with a power supply Vcc, the grid electrode of the PMOS transistor M13 is grounded, the grid electrodes of the PMOS transistor M14 and the NMOS transistor M11 are connected and used as the input current I of the input end of the transimpedance amplifier 10 pd And the drain electrode of the PMOS tube M13 is the output end of the first-stage CMOS inverter 5. Similarly, the structure of the second-stage CMOS inverter 6 is the same as that of the first-stage CMOS inverter 5, and includes an NMOS transistor M15 and PMOS transistors M16, M17, and M18, the sources and drains of the PMOS transistors M16, M17, and M18 are respectively connected, and the corresponding sources are connected to the power supply Vcc, the gate of the PMOS transistor M17 is grounded, and the gates of the PMOS transistor M18 and the NMOS transistor M15 are connected to the drain of the output PMOS transistor M13 of the first-stage CMOS inverter 5. Similarly, the structure of the third-stage CMOS inverter 7 is the same as that of the first-stage and second-stage CMOS inverters 6, and includes an NMOS transistor M19 and PMOS transistors M20, M21, and M22, the sources and drains of the PMOS transistors M20, M21, and M22 are respectively connected, and the corresponding sources are connected to the power supply Vcc, the gate of the PMOS transistor M21 is grounded, and the gates of the PMOS transistor M22 and the NMOS transistor M19 are connected to the drain of the output PMOS transistor M17 of the second-stage CMOS inverter 6. The drain of the PMOS transistor M21 is used as the output voltage Vout of the transimpedance amplifier 10. The feedback network 8 comprises a capacitor C fb PMOS transistor M fb And a parasitic capacitance compensation module 81. The PMOS transistor M fb The grid electrode of the capacitor is grounded, the drain electrode and the source electrode of the capacitor are grounded, and the capacitor C fb And the input and output terminals of the parasitic capacitance compensation module 81. The parasitic capacitance compensation module 81 includesPMOS transistors Mc1, mc2 and capacitor Cc. Of the PMOS tube Mc1The grid electrode is connected with the grid electrode of the PMOS tube M14 at the input end, the source electrode of the grid electrode is connected with the grid electrode of the PMOS tube Mc2, the drain electrode of the grid electrode is connected with one end of the capacitor Cc and is connected with the power supply I 1 And (4) connecting. The source of the PMOS tube Mc2 is grounded, and the drain is connected to the other end of the capacitor Cc and to a power supply I 1 And (4) connecting.
The photocurrent I is derived in detail below pd And an output voltage V out The relationship between:
wherein, C T Is a capacitor C of a photodiode PD And parasitic capacitance C of input stage of transimpedance amplifier in Taking into account the open loop frequency response A of the amplifier d (jω)＝A 0 /(1+(jω/ω c ) Wherein ω is c Is the cut-off frequency (-3 dB), A 0 Is the open loop intermediate frequency gain, so that:
wherein, ω is 0 And Q are defined as:
to obtain the maximum flatter response (Butterworth), Q = 1/\58286andsubstitution of the equation (10) can result in:
(11) The formula gives a larger C than necessary fb To obtain dynamic stability. To increase bandwidth, a slightly lower C may be selected fb The value, chosen for the phase margin of 45 °, (8) can also be written as:
If it is not\58388and =135 DEG can meet the requirement of 45 DEG of phase margin, and the circuit is stable. When \58388; =135 °:
when the temperature is higher than the set temperature
When the method is used:
q =4 \58286canbe obtained from the two formulae (13) and (14), and in this case:
thus implementing a transimpedance amplifier, C fb The values should be between the given equations (11) and (15).
Compared with the prior art, the compensation capacitor of the invention is realized by the PMOS tubes Mc1 and Mc2, and an effective negative impedance is generated, and the value of the negative impedance is half of that of the input capacitor. By introducing a compensation capacitor, the bandwidth of the circuit can be increased. The PMOS transistors M12, M13, M16, M17, M20, and M21 may increase the voltage of the input node of the photodiode 20 connected to the transimpedance amplifier 10, thereby increasing the reverse voltage applied between the positive and negative electrodes of the photodiode 20 and increasing the photoelectric conversion efficiency of the photodiode, which is achieved by increasing the current flowing through the NMOS transistors M11, M15, and M19.
Meanwhile, the NMOS transistors M13, M17, and M21 can eliminate the influence of external environmental factors such as power supply and process parameter fluctuation, and the specific implementation manner is: the gates of PMOS transistors M13, M17, and M21 are grounded, so V SG ＝V S ＝V cc The PMOS transistors M13, M17 and M21 operate in the linear region. If the power supply voltage is reduced, then V SG Decrease, decrease in current flowing through each of M13, M17 and M21 tubes, and voltage V SD Decreases so that the output voltage increases, and the increased input voltage decreases again due to the presence of the feedback network 8Consequently, the output voltage is stabilized.
Adding a capacitor C to the feedback network 8 fb And the parasitic capacitance compensation module 81 can generate a zero point to obtain a sufficient phase margin, so that the stability of the entire circuit can be maintained.
Referring to fig. 8, a simulation diagram of the output frequency response and the output pulse voltage in fig. 6 is shown. The invention adopts a 0.6 mu mCMOS process, and the given conditions are as follows: all MOS transistors have the minimum channel length, the junction capacitance of the photodiode 20 is 1pf, and the PMOS transistor M fb Has an equivalent resistance value of 12k omega and a load capacitance C fb Has a value of 1pf. Therefore, the present invention has the greatest advantage that a high bandwidth can be obtained while a minimum chip area can be achieved. As can be seen from the figure, the circuit of the invention has flat frequency response and higher stability.
The circuit of the invention has other design schemes, because the input microampere current signal is required to be converted into a voltage signal of hundreds of millivolts, the resistance value of the feedback resistor needs hundreds of K ohms, and if polysilicon or a diffusion resistor is adopted, the generated phase shift is large. An effective method is to adopt an MOS tube working in a linear region, so that various options are available, not only PMOS tubes Mc1 and Mc2 can be adopted, but also the Mc1 and Mc2 can be NMOS tubes or the PMOS tubes and the NMOS tubes are connected in parallel, although the NMOS tubes and the PMOS tubes have the same unit junction capacitance, the NMOS tubes have poor large signal characteristics, and large input current signals can increase the resistance value, so that the NMOS tubes are easy to enter a saturation region; this effect can be eliminated by connecting NMOS and PMOS transistors in parallel, but the parasitic capacitance is doubled, thereby increasing the delay. Therefore, the use of PMOS tubes Mc1, mc2 is the most preferred embodiment.
The transimpedance amplifier 200 of the present invention may employ not only a three-stage MOS transistor inverter but also a single-stage or multi-stage CMOS transistor inverter.
The transimpedance amplifier of the present invention can be applied not only to an optical head of a digital video disk player (DVD, VCD, etc.), but also to other communication systems, such as medical instruments or scientific instruments.
The transimpedance amplifier provided by the present invention is described in detail above, and the principle and the implementation of the present invention are explained in the present document by applying specific examples, and the description of the above embodiments is only used to assist in understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed, and in conclusion, the content of the present specification should not be construed as a limitation of the present invention.
Claims (10)
1. A transresistance amplifier for converting a current signal into a voltage signal, the single-stage amplification circuit comprising: the first transistor and the second transistor, the grid of the first transistor, the second transistor is connected as the input end and used for inputting the signal, its drain-source resistance is connected each other, the source of the first transistor is grounded, the source of the second transistor is connected with first power, characterized by that: the single-stage amplification circuit further includes: the grid electrode and the source electrode of the third transistor and the source electrode of the fourth transistor are connected with the source electrode of the second transistor, the drain electrodes of the third transistor and the fourth transistor are connected with the drain electrode of the second transistor to serve as output ends for outputting signals, the grid electrode of the fourth transistor is grounded, and when the photodiode connected with the transimpedance amplifier converts an optical signal into a current signal and inputs the current signal into the transimpedance amplifier, the third transistor and the fourth transistor can increase the photoelectric conversion efficiency of the photodiode by increasing the current of the first transistor.
2. The transimpedance amplifier according to claim 1, characterized in that: the first transistor is an NMOS transistor and the second, third and fourth transistors are PMOS transistors.
3. The transimpedance amplifier of claim 1, wherein: the transimpedance amplifier comprises a feedback network, the feedback network comprises a fifth transistor, the grid electrode of the fifth transistor is grounded, the source electrode and the drain electrode of the fifth transistor are respectively connected with the output end and the input end, and the fifth transistor can guarantee the stability of the output voltage of the transimpedance amplifier.
4. A transimpedance amplifier according to claim 3, characterized in that: the fifth transistor is a PMOS transistor.
5. The transimpedance amplifier according to claim 4, characterized in that: the feedback network further comprises a first capacitor, two ends of the first capacitor are respectively connected with the input end and the output end of the transimpedance amplifier, and the first capacitor can flatten the frequency response of the transimpedance amplifier.
6. A transimpedance amplifier according to claim 3, 4 or 5, characterized in that: the feedback network also comprises a parasitic capacitance compensation module, wherein the parasitic capacitance compensation module comprises a sixth transistor, a seventh transistor and a second capacitor, the grid electrode of the sixth transistor is connected with the input end of the transimpedance amplifier, the source electrode of the sixth transistor is connected with the output end of the transimpedance amplifier, and the drain electrode of the sixth transistor is connected with one end of the second capacitor; the grid of the seventh transistor is connected with the output end of the mutual resistance amplifier, the source electrode of the seventh transistor is grounded, the drain electrode of the seventh transistor is connected with the other end of the second capacitor, and the parasitic capacitance compensation module can enable the mutual resistance amplifier to obtain enough phase margin so as to keep the circuit stable.
7. The transimpedance amplifier according to claim 6, characterized in that: the sixth transistor and the seventh transistor are both PMOS transistors.
8. The transimpedance amplifier of claim 6, wherein: the two ends of the second capacitor are connected with a second voltage source.
9. A transimpedance amplifier according to claim 1 or 8, characterized in that: the transimpedance amplifier adopts 0.6 mu mCMOS technology.
10. The transimpedance amplifier according to claim 5, characterized in that: the equivalent resistance value of the fifth transistor is 12k Ω, the first to seventh transistors are all the smallest channel lengths, and the value of the first capacitance is 1pf.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100616860A CN100559705C (en) | 2006-07-12 | 2006-07-12 | Transreactance amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100616860A CN100559705C (en) | 2006-07-12 | 2006-07-12 | Transreactance amplifier |
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| Publication Number | Publication Date |
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| CN101106359A true CN101106359A (en) | 2008-01-16 |
| CN100559705C CN100559705C (en) | 2009-11-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2006100616860A Expired - Fee Related CN100559705C (en) | 2006-07-12 | 2006-07-12 | Transreactance amplifier |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| DE3685006D1 (en) * | 1985-12-16 | 1992-05-27 | Siemens Ag | OPTICAL RECEIVER. |
| US5488321A (en) * | 1993-04-07 | 1996-01-30 | Rambus, Inc. | Static high speed comparator |
| CN1143427C (en) * | 1999-09-02 | 2004-03-24 | 深圳赛意法微电子有限公司 | Mutual impedance amplifier |
| US6812795B2 (en) * | 2003-02-11 | 2004-11-02 | O2Micro International Limited | Transimpedance amplifier with feedback resistive network |
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