CN101090094A - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
- Publication number
- CN101090094A CN101090094A CNA2006101564577A CN200610156457A CN101090094A CN 101090094 A CN101090094 A CN 101090094A CN A2006101564577 A CNA2006101564577 A CN A2006101564577A CN 200610156457 A CN200610156457 A CN 200610156457A CN 101090094 A CN101090094 A CN 101090094A
- Authority
- CN
- China
- Prior art keywords
- temperature
- substrate
- chamber
- area
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 6
- 238000000034 method Methods 0.000 claims abstract description 43
- 230000008569 process Effects 0.000 claims abstract description 29
- 238000000137 annealing Methods 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000002019 doping agent Substances 0.000 claims description 11
- 230000004913 activation Effects 0.000 claims description 6
- 238000002347 injection Methods 0.000 claims description 5
- 239000007924 injection Substances 0.000 claims description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 4
- 229910052739 hydrogen Inorganic materials 0.000 claims description 4
- 239000001257 hydrogen Substances 0.000 claims description 4
- 239000008246 gaseous mixture Substances 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- 238000007669 thermal treatment Methods 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 abstract description 5
- 239000012535 impurity Substances 0.000 abstract description 3
- 230000000694 effects Effects 0.000 description 11
- 238000009792 diffusion process Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000005465 channeling Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- WQGWDDDVZFFDIG-UHFFFAOYSA-N pyrogallol Chemical compound OC1=CC=CC(O)=C1O WQGWDDDVZFFDIG-UHFFFAOYSA-N 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A method of manufacturing a semiconductor device includes the step of performing an ion implantation process for implanting an impurity ion into a semiconductor substrate, and performing annealing in a state where temperature of respective portions of an annealing chamber are set differently in order to activate the impurity ion.
Description
Technical field
The present invention relates to semiconductor device, more specifically relate to the method for the manufacturing semiconductor device that reduces the threshold voltage difference that is formed on each element on the same wafer.
Background technology
Along with device dwindles, the integrated level of knot increases gradually.Because heat history (thermal budget) forms transient enhanced diffusion (TED) knot, (RTP) carries out follow-up high-temperature annealing process by rapid thermal treatment in order to stop.
In high-temperature annealing process, can stop because the undesired diffusion of the more deep knot that TED causes still can not prevent because the pattern effect that the increase of pattern number causes.In high temperature RTP, control temperature by the temperature of using places, measurement specified point position such as pyrometer (pyro), thermocouple.The pattern effect is to be caused by the reflectivity change in the wafer, and this temperature that causes entire wafer is along with changing from moving of high pattern density zone to pattern-free zone.
Along with the variation that electronic product is produced, wafer size increases gradually.The element characteristic that is formed on the wafer increases with the possibility that the area increase changes.In addition, the property difference between wafer middle section and the fringe region causes threshold voltage difference, makes yields descend.
Fig. 1 is the figure that each the transistorized threshold voltage variation that is formed on the single wafer is shown.
As seen from Figure 1, because pattern effect and other process, be formed on and have 100mV or bigger threshold voltage difference between each transistor in the single wafer.Particularly, the transistor that as seen is formed in the wafer middle section has lower threshold voltage than the transistor that is formed in other zone.
One of reason that is formed on the threshold voltage difference between each element on the same wafer is because the interface diffusion difference that temperature gradient causes in the annealing process.For example, after injection is used to form the ion in source/drain interface, carry out annealing process with diffusion source electrode/drain electrode junction region.This process is extremely important, and this is because it makes the interface diffusion so that electron stream is steady by annealing.
As mentioned above, the diffusing step in interface has a direct impact threshold voltage level.Particularly, diffusing step is very different with annealing temperature.Yet, when use has the wafer of roomy area, by annealing device formation temperature gradient.Thereby, between each element on the same wafer, produce threshold voltage difference.
Summary of the invention
One embodiment of the invention relate to the method for making semiconductor device, and it can improve the transistorized threshold voltage distribution that is formed on the single wafer by the annealing process that the temperature difference of implementing annealing chamber inner diverse location place is set.
In one embodiment, a kind of method of making semiconductor device may further comprise the steps: implement foreign ion is injected the ion implantation process of Semiconductor substrate and implements annealing with the activated impurity ion under the state that annealing chamber's each several part temperature difference is set.
Description of drawings
Fig. 1 is the figure that is illustrated in the transistorized threshold voltage variation on the single wafer diverse location.
Fig. 2 is the figure that the pattern effect of type of furnace RTP and lamp type RTP is shown.
Fig. 3 A is the figure that temperature gradient in the type of furnace RTP equipment is shown.
Fig. 3 B is the figure that is illustrated in chip temperature gradient in the type of furnace RTP process.
Fig. 4 A-4C is the sectional view that the method for making semiconductor device according to an embodiment of the invention is shown.
Embodiment
Below with reference to description of drawings according to specific embodiments of the present invention.
Fig. 2 is the figure that the pattern effect of type of furnace RTP and lamp type RTP is shown, and it is illustrated in the temperature T front wafer surface and the back side measured and based on the deviation between the mean temperature Tavg of type.
As shown in Figure 2, when using lamp type RTP, temperature deviation T-Tavg alters a great deal with chip design, has 80 ℃ temperature difference between wafer edge region and middle section.
On the contrary, littler from the temperature deviation of chip design when using type of furnace RTP than lamp type RTP, and the temperature difference between Waffer edge and the middle section is less than 20 ℃.
In the present invention, adopt type of furnace RTP to inject the annealing process of the ion of source electrode and drain junction, thereby reduce because the transistor characteristic difference that the pattern effect causes as activation.Attention can implement the lamp type or line style RTP substitutes type of furnace RTP.
(temperature gradient different state under) implements annealing under the state that top, top corner and the side-walls temperature difference of when annealing annealing chamber are set.
Fig. 3 A is the figure that temperature gradient in the type of furnace RTP equipment is shown.Fig. 3 B is the figure that is illustrated in chip temperature gradient in the type of furnace RTP process.In Fig. 3 A, Reference numeral 300 refers to be provided at the wherein chamber in the space of implementing process process, and 310 refer to the brilliant boat of load wafer on it.
With reference to figure 3A and 3B, in type of furnace RTP equipment, difference is set top, top corner and the side-walls temperature of chamber 300 to change the temperature on the wafer.
Thereby, if implement to have the annealing process of the type of furnace RTP of temperature gradient as the ion of activation injection source electrode and drain junction, the transistorized source electrode and the drain junction that then are formed on the wafer middle section spread manyly than the transistor that is formed on Waffer edge in knot.As a result, the transistorized conducting electric current in the wafer middle section increases and the threshold voltage rising.
Because rise than transistorized threshold voltage in the lower relatively middle section of transistorized threshold voltage in the wafer edge region, therefore can reduce the threshold voltage deviation on the entire wafer.
Temperature gradient is not limited to the temperature based on chamber region that the present invention proposes, and can also implement according to the process steps difference.For example, the temperature at top, chamber can be set to such an extent that be lower than the temperature of corner, chamber top, and the temperature of corner, top, chamber can be set to such an extent that be lower than the temperature of chamber sidewall.In other words, but the temperature difference of annealing chamber top, top corner and sidewall set.
Fig. 4 A-4C is the sectional view that the method for making semiconductor device according to an embodiment of the invention is shown.
With reference to figure 4A, n type dopant injects Semiconductor substrate 40 to form n trap (not shown).In order to control threshold voltage, inject the ion of control threshold voltage.N type dopant can comprise phosphorus (P) ion, can adopt the ion of 200-1000KeV to inject energy and 10
12-10
14Ion/cm
2Ion implantation dosage.The ion that is used to control threshold voltage can adopt p type dopant, can adopt the ion of 5-100keV inject can and 10
11-10
14Ion/cm
2Ion implantation dosage.In order to prevent the channeling effect of dopant, tilt to inject threshold voltage control ion.
Sequential aggradation gate oxide level 41 and polysilicon layer.Make polysilicon layer and gate oxide level 41 patternings, on the specific region, form grid 43.Grid 43 has the structure that gate oxide level 41 and gate electrode 42 pile up.
Form insulating barrier (for example hot temperature oxide (HTO) layer) on the whole surface of grid 43 comprising.Form separator 44 in grid 43 both sides by implementing code-pattern etching (blanket etch).The HTO layer can form under 1-3 backing pressure power, 650-800 ℃ temperature by LPCVD.
With reference to figure 4B, utilize gate electrode 42 and inject the foreign ion that is used to form source electrode and drain junction as the separator 43 of mask.Foreign ion can comprise BF
2Or B and BF
2Gaseous mixture.
When using BF
2The time, use the ion of 1-30KeV to inject energy and 10
14-5 * 10
15Ion/cm
2Ion implantation dosage.When using B and BF
2Hybrid ionic the time, use the ion of 1-30KeV inject can and 10
14-3 * 10
15Ion/cm
2Dosage inject BF
2Use the ion of 1-20KeV to inject energy and 10
14-3 * 10
15Ion/cm
2Dosage inject B.
BF
2Have high atomic weight, therefore effectively form shallow junction.BF
2Effectively stop the defective that produces owing to the inertia dopant with the hybrid ionic of B.
With reference to figure 4C, use type of furnace RTP to spread the foreign ion of injection with temperature gradient, form source electrode and drain junction 45 thus.In order to remove the inertia dopant to greatest extent, use to have the type of furnace RTP of hydrogen atmosphere, and, nitrogen is mixed with hydrogen in order to promote this process.
If use type of furnace RTP as mentioned above, then can reduce the pattern effect, and can improve because the transistor characteristic difference due to the pattern effect.
Simultaneously, if inject p type dopant as the threshold voltage ion, the transistorized threshold voltage that then is formed in the wafer middle section is low, is formed on the transistorized threshold voltage height in the wafer edge region.In type of furnace RTP, the temperature gradient of middle section is higher than the temperature gradient in the wafer edge region, therefore can improve the transistorized low threshold voltage that is positioned at middle section.
In addition, the present invention can be applicable to source/drain junctions and forms technology annealing process in addition.As a result, improve the uniformity of the transistor threshold voltage of whole single wafer.Therefore, can stablize the manufacturing semiconductor device.
As mentioned above, the present invention has the one or more of following a plurality of advantages.
Use type of furnace RTP to inject the annealing process of source electrode and drain junction intermediate ion as activation.Therefore, the pattern effect is minimized, and can improve because the transistor characteristic deviation that the pattern effect causes.
Enforcement has the annealing of temperature gradient.Therefore, the threshold voltage variation of wafer edge region and wafer middle section can be improved, and uniform threshold voltage can be obtained.
The inhomogeneity increase of single wafer that becomes serious along with the wafer size increase can solve by simple adjustment method for annealing.
Can because significantly changing the short-channel effect of transistor characteristic, follow-up pyroprocess stably make device by active process.
Above-mentioned embodiment of the present invention is exemplary, and various replacement scheme can obtain and drop in the spirit and scope of appended claims with change according to this specification.
Claims (12)
1. method of making semiconductor device comprises:
Dopant is injected Semiconductor substrate, and described substrate has first area and second area; With
Activate the dopant that injects substrate by making first and second zones stand different activation energy.
2. the method for claim 1 also comprises:
The substrate that will have an injection dopant wherein is provided on the processing region of hot equipment to carry out activation step, and described hot equipment provides first and second zones with different temperatures.
3. the method for claim 1 also comprises:
The substrate that will have an injection dopant wherein is provided at hot equipment carrying out activation step,
Wherein said hot equipment is included in the chamber that wherein provides substrate, and described chamber has temperature gradient so that substrate first area with first temperature and the substrate second area with second temperature to be provided.
4. the method for claim 3, wherein the first area of substrate is provided at the adjacent substrate center, and the second area of substrate is provided at adjacent substrate edge.
5. the method for claim 3, wherein hot equipment is type of furnace equipment.
6. the method for claim 5, wherein:
The top, chamber is set at first room temperature, the chamber sidewall is set at second room temperature.
7. the method for claim 6, wherein first room temperature is set at and is higher than second room temperature.
8. the method for claim 2, wherein first temperature is set at and is higher than second temperature, and second temperature is set at and is lower than the 3rd temperature.
9. the process of claim 1 wherein that in annealing process annealing chamber has a kind of in the type of furnace, lamp type and the line style.
10. the process of claim 1 wherein and implement annealing process by rapid thermal treatment (RTP).
11. the process of claim 1 wherein and under hydrogen atmosphere, implement annealing process.
12. the process of claim 1 wherein and under the gaseous mixture atmosphere of hydrogen and nitrogen, implement annealing process.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR20060054420 | 2006-06-16 | ||
| KR1020060054420 | 2006-06-16 | ||
| KR1020060096002 | 2006-09-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101090094A true CN101090094A (en) | 2007-12-19 |
| CN100570858C CN100570858C (en) | 2009-12-16 |
Family
ID=38943353
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006101564577A Expired - Fee Related CN100570858C (en) | 2006-06-16 | 2006-12-31 | Make the method for semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| KR (1) | KR100870324B1 (en) |
| CN (1) | CN100570858C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201517133A (en) * | 2013-10-07 | 2015-05-01 | Applied Materials Inc | Enabling high activation of dopants in indium-aluminum-gallium-nitride material system using hot implantation and nanosecond annealing |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0178489B1 (en) * | 1995-12-15 | 1999-04-15 | 양승택 | Method for dopant activation in the fabrication of semiconductor devices |
| KR20000055729A (en) * | 1999-02-09 | 2000-09-15 | 윤종용 | Semiconductor fabricating apparatus having heater for heating chamber |
| US6828204B2 (en) * | 2002-10-16 | 2004-12-07 | Varian Semiconductor Equipment Associates, Inc. | Method and system for compensating for anneal non-uniformities |
| KR101017042B1 (en) * | 2003-08-30 | 2011-02-23 | 매그나칩 반도체 유한회사 | Method of forming a transistor in a semiconductor device |
| KR20050059825A (en) * | 2003-12-15 | 2005-06-21 | 매그나칩 반도체 유한회사 | Method for fabricating semiconductor device |
| JP2006229040A (en) * | 2005-02-18 | 2006-08-31 | Matsushita Electric Ind Co Ltd | Method and apparatus for heat treatment |
-
2006
- 2006-09-29 KR KR1020060096002A patent/KR100870324B1/en not_active IP Right Cessation
- 2006-12-31 CN CNB2006101564577A patent/CN100570858C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| KR100870324B1 (en) | 2008-11-25 |
| CN100570858C (en) | 2009-12-16 |
| KR20070120010A (en) | 2007-12-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20230360915A1 (en) | Semiconductor device and manufacturing method thereof | |
| US8343862B2 (en) | Semiconductor device with a field stop zone and process of producing the same | |
| CN102737967B (en) | Semiconductor device and substrate with chalcogen doped region | |
| CN101385130B (en) | Semiconductor device and manufacturing method thereof | |
| CN100524654C (en) | Drain/source extension structure of a field effect transistor including doped high-k sidewall spacers | |
| CN107710417B (en) | Method for manufacturing semiconductor device | |
| US20140374882A1 (en) | Semiconductor Device with Recombination Centers and Method of Manufacturing | |
| JP2001127292A5 (en) | ||
| CN102054876A (en) | Fast recovery diode | |
| JP2021531665A (en) | Insulated gate power semiconductor devices, and methods for manufacturing such devices. | |
| CN101847579B (en) | For the method manufacturing power semiconductor | |
| CN103560086B (en) | The preparation method of the super-junction semiconductor device of avalanche capacity can be improved | |
| CN101281870A (en) | Method for manufacturing semiconductor device | |
| CN101026091A (en) | Semiconductor device including impurity doped region and its forming method | |
| KR100679206B1 (en) | Method for manufacturing a semiconductor device having polysilicon plugs | |
| CN100570858C (en) | Make the method for semiconductor device | |
| CN103594516A (en) | Semiconductor device and method of making the same | |
| CN104716039B (en) | Improve the back process preparation method of IGBT performances | |
| CN104992966B (en) | A kind of preparation method of the low bipolar high frequency power transistor chip of heat budget | |
| KR20160086368A (en) | Semiconductor device manufacturing method | |
| CN102044436B (en) | Method for preparing semiconductor device | |
| CN106469646A (en) | A kind of silicon carbide device forms highly doped manufacture method with ion implanting | |
| CN112885716A (en) | Method for forming semiconductor structure | |
| CN105225957A (en) | Slot type power device manufacture method and slot type power device | |
| JP7400834B2 (en) | Semiconductor device and semiconductor device manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20091216 Termination date: 20131231 |