CN101086965A - Method for reducing large patter sinking in chemical and mechanical grinding of metal and multi-crystal silicon - Google Patents
Method for reducing large patter sinking in chemical and mechanical grinding of metal and multi-crystal silicon Download PDFInfo
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- CN101086965A CN101086965A CN 200610027371 CN200610027371A CN101086965A CN 101086965 A CN101086965 A CN 101086965A CN 200610027371 CN200610027371 CN 200610027371 CN 200610027371 A CN200610027371 A CN 200610027371A CN 101086965 A CN101086965 A CN 101086965A
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Abstract
The invention provides a method of decreasing big pattern hollow during metal and polysilicon chemical and mechanical rubbing, it mainly uses photoetching and etching technique, combining decorated chemical and mechanical rubbing method, avoids big pattern hollow when metal and polysilicon is rubbed. The method not only can make performance of source area of wafer perfect, but also problem of hollow of big pattern area can be decreased greatly, besides, the method fits for increasing equality of wafer.
Description
Technical field
The present invention relates to the cmp processing procedure in the semiconductor fabrication process, be specifically related to a kind of method that reduces pattern depression in the chemical mechanical planarization process.
Background technology
In the process for fabrication of semiconductor device, be extensive use of cmp (CMP, ChemicalMechanical polishing) system and carry out smooth processing.Lapping device generally comprises grinding table (being covered with grinding pad on it) and grinding head (semiconductor wafer that the grinding of needing is arranged on it).Semiconductor wafer is fixed on the grinding head, the semiconductor wafer of grinding pad in the face of polishing, and when grinding semiconductor chip, grinding pad has in the presence of the lapping liquid of polishing particles, with certain pressure contact and grinding semiconductor chip, makes its surface be tending towards smooth.
The cmp processing procedure can relate to the grinding of metal and polysilicon usually, because the feature of CMP processing procedure consumptive material, the consumptive material of CMP processing procedure comprises: grinding pad, and lapping liquid etc., the characteristic of these consumptive materials makes cmp can cause big pattern depression (dishing).Even in design rule, avoid described big pattern occurring, also can cause huge yield loss as far as possible.Development along with ic manufacturing technology, to the increase in demand of big pattern, pattern dimension even surpass 10000 μ m * 10000 μ m sometimes, and because the existence of the problems referred to above, depression greater than 2000 will appear in these big area of the pattern, and this can cause component failure.
Fig. 1 a and Fig. 1 b have shown the wafer vertical section contrast schematic diagram of metal pattern close quarters before and after cmp, numeral 1 expression material SiO among the figure
2, 2 expression material of tungsten.Through cmp, the tungsten that the upper strata covers is milled to SiO
2Layer exposes, and forms tungsten and SiO
2The pattern that intermeshes, but there is depression to a certain degree the central area.
With respect to the pattern close quarters, can there be big area of the pattern in its periphery usually, and the difference behind the cmp is more obvious, and Fig. 2 a and Fig. 2 b have shown the wafer vertical section contrast schematic diagram of big area of the pattern before and after cmp, numeral 1 expression SiO among the figure
2, 2 expression tungsten.Can see that because tungsten is the monoblock pattern, its depression situation of grinding back is more serious than Fig. 1 a and Fig. 1 b demonstration.
Fig. 3 a and Fig. 3 b have shown in the polysilicon grinding processing procedure, the wafer vertical section contrast schematic diagram of the active area that pattern is intensive (cell area) before and after cmp, numeral 1 expression SiO among the figure
2, 3 expression silicon substrates, 4 expression polysilicons.Through cmp, the polysilicon on upper strata and SiO
2The pattern that formation intermeshes, depression to a certain degree appears in abrasive areas.
The active area intensive with respect to pattern, its neighboring area are the big area of the pattern of polysilicon, and Fig. 4 a and Fig. 4 b have shown the wafer vertical section contrast schematic diagram of the big area of the pattern of polysilicon before and after cmp, numeral 1 expression SiO among the figure
2, 3 expression silicon substrates, 4 expression polysilicons.Because polished polysilicon is the monoblock pattern, its depression situation is more serious than Fig. 3.
The problem of above-mentioned big area of the pattern serious depression behind cmp is inevitable owing to the characteristic of grinding processing procedure itself, and along with ic manufacturing technology constantly develops, this problem more and more looms large, and therefore is necessary to find effective solution.
Summary of the invention
In order to reduce the big area of the pattern depression that in the CMP of metal and polysilicon processing procedure, occurs, reduce the risk that integrated circuit (IC)-components lost efficacy, finally promote the product yield and propose the present invention.
The objective of the invention is to; a kind of method that reduces big area of the pattern depression is provided; when metal or polysilicon are carried out cmp; protection with photoresist has the neighboring area of big pattern; make not behind the etched certain thickness of being protected by photoresist of part the cmp of modification property again with the mode of eat-backing, last grinding result can reduce the degree of big pattern depression greatly.
Technical scheme provided by the invention, be to be integrated in the ripe semiconductor fabrication process, various photoetching the preceding, deposition forms technologies such as device pattern feature or removal photoresist and all adopts prior art, before using the present invention, should finish the metal level that needs grinding, for example tungsten (W), the perhaps deposition of polysilicon layer.
Concrete technical scheme of the present invention comprises the following steps:
1) apply photoresist on the wafer that needs grind, exposure imaging makes big area of the pattern be covered by photoresist, exposes the intensive active region of all the other patterns;
2) (etch back) eat-back in the zone of exposing, stay about 200 ～700 by the grinding-material layer;
3) peel off residual photoresist with the remove photoresist mode of (ashing) or Wet-type etching (wet etch) of high temperature sintering,, can make wafer enter successive process after the end wafer modification property cmp (touch up CMP).
In the present invention, the means of lithographic process and follow-up removal photoresist all can be with reference to the prior art of maturation, wherein the coating thickness of photoresist is on step 2) in the material thickness that needs to eat-back decide, the thickness of photoresist should guarantee after eat-backing, the big area of the pattern of periphery still has photoresist residual, makes big area of the pattern not etched.
Above-mentioned steps 2) in, described eat-backing adopted the dryness etching, specifically for metal etch, and tungsten (W) for example, the etching gas of employing is sulphur hexafluoride (SF
6); For the polysilicon etching, used etching gas is chlorine (Cl
2) or hydrogen bromide (HBr).
Described modification cmp (touch up CMP), come down to a kind of chemical and mechanical grinding method of optimization, the low grinding head pressure of control in implementation process, low grinding table and grinding head rotating speed can reach better lapped face planarization effect.
Contrasting flow chart shown in Figure 5 can clearer understanding above-mentioned steps, after preposition step, the light shield that forms open active area carries out exposure imaging, big area of the pattern is covered by photoresist, expose the intensive active region of all the other patterns, then open active area filler is eat-back (etch back), stay about 200 ～700 by the grinding-material layer, remove photoresist, can enter successive process behind the modified property cmp.
The invention has the advantages that, by above-mentioned method, can obviously reduce the degree that big area of the pattern caves in behind CMP, for example size surpasses the big pattern of 10000 μ m * 10000 μ m, by the inventive method carry out its depression behind the cmp from original greater than 2000 to less than 500 .This method both can make the intensive active area of the pattern of a wafer functional, and the depression problem of the big area of the pattern of periphery is reduced, and this in addition method also helps promoting the uniformity of wafer.Following table 1 is for handling the back uniformity tables of data that grab sample measures to wafer according to the inventive method, can see no matter be center wafer or fringe region, the film thickness difference of active area after grinding that big area of the pattern of periphery and pattern are intensive is all very little, is respectively 249 and 291 .
Table 1
| Inspection item | Center () | Edge () | Difference () | |||
| Near active area | Away from active area | Near active area | Away from active area | The center | The edge | |
| Neighboring area polysilicon thickness | 2450 | 2201 | 2239 | 2530 | 249 | 291 |
For be more readily understood purpose of the present invention, feature with and advantage, below conjunction with figs. and embodiment are described in detail the present invention.
Description of drawings
The accompanying drawing that comprises among the application is a component part of specification, and accompanying drawing and specification and claims one are used from explanation flesh and blood of the present invention, are used for understanding better the present invention.
Fig. 1 a and Fig. 1 b have shown the wafer vertical section contrast schematic diagram of metal pattern close quarters before and after cmp in the prior art;
Fig. 2 a and Fig. 2 b have shown the wafer vertical section contrast schematic diagram of big area of the pattern before and after cmp in the prior art;
Fig. 3 a and Fig. 3 b have shown in the polysilicon grinding processing procedure of prior art, the wafer vertical section contrast schematic diagram of the active area that pattern is intensive (cell area) before and after cmp;
Fig. 4 a and Fig. 4 b have shown the wafer vertical section contrast schematic diagram of the big area of the pattern of polysilicon before and after cmp in the prior art;
Fig. 5 is the flow chart of method provided by the present invention;
Fig. 6 a represent Application Example 1 method is provided before, the wafer active area, promptly pattern is than the vertical section schematic diagram of zonule;
Fig. 6 b is by before Application Example 1 provided method, the vertical section schematic diagram of the big area of the pattern of wafer perimeter;
After being respectively the etchback step of embodiment 1 method that provides shown in Fig. 7 a and Fig. 7 b, the wafer vertical section schematic diagram of active area and neighboring area;
Wafer vertical section schematic diagram according to active area and neighboring area after the modification cmp step of embodiment 1 method that provides is provided shown in Fig. 8 a and Fig. 8 b;
Fig. 9 a is depicted as the wafer vertical section schematic diagram after the preposition step among the embodiment 2;
Fig. 9 b is depicted as among the embodiment 2 the wafer vertical section schematic diagram behind the big area of the pattern on the covering protection wafer with photoresist;
Wafer vertical section schematic diagram after Fig. 9 c is depicted as among the embodiment 2 wafer eat-back;
Fig. 9 d is depicted as among the embodiment 2 the wafer vertical section schematic diagram behind the wafer modification property cmp.
Embodiment
In order to understand technology of the present invention better, be described further below in conjunction with specific embodiments of the invention, but it does not limit the present invention.
Use method of the present invention to reduce the sinking degree of tungsten behind CMP of deposition
At first normally form raceway groove according to prior art, deposition is filled steps such as raceway groove, obtains structure shown in Fig. 6 a and Fig. 6 b, and wherein Fig. 6 a represents the wafer active area, be the vertical section schematic diagram of pattern than the zonule, Fig. 6 b is the vertical section schematic diagram of the big area of the pattern of wafer perimeter.Follow these steps to subsequently handle:
1) on wafer, applies photoresist, define active area and neighboring area, expose the intensive active region of pattern behind the exposure imaging, and the neighboring area is covered by photoresist still;
2) active area that exposes is eat-back (etch back), stay about 200 ～700 tungsten layers, used engraving method is a plasma etching, and etching reaction gas is sulphur hexafluoride (SF
6).The neighboring area is owing to protected by photoresist, and tungsten layer does not have etched.The wafer vertical section schematic diagram of active area and neighboring area is respectively shown in Fig. 7 a and Fig. 7 b;
3) peel off residual photoresist with the remove photoresist mode of (ashing) or Wet-type etching (wet etch) of high temperature sintering, to wafer modification property (touch up) cmp, control low grinding head pressure, low grinding table and grinding head rotating speed are to form SiO
2With tungsten at a pattern that copline is interlaced;
The coating thickness of photoresist is on step 2 in the step 1)) in the material thickness that needs to eat-back decide, the thickness of photoresist should guarantee that after eat-backing the big area of the pattern of periphery still has photoresist residual, makes big area of the pattern not etched.
Modification property cmp is applicable to all work-table of chemicomechanical grinding mill, concrete controlling schemes is as follows: the rotating speed of grinding table is between 30 rpms to 70 rpms, the rotating speed of grinding head is between 30 rpms to 70 rpms, and the pressure of grinding head is that 1.0 pound per square inches are between 3.5 pound per square inches.
The wafer vertical section schematic diagram that grinds back active area and neighboring area is respectively shown in Fig. 8 a and Fig. 8 b.Can make wafer enter successive process after the end.
Use method of the present invention to reduce the sinking degree of polysilicon behind CMP of deposition
At first normally form raceway groove according to prior art, deposition is filled steps such as raceway groove, obtains the vertical section schematic diagram of wafer shown in Fig. 9 a, and the thickness of polysilicon layer 4 depositions is 1500 ～4000 .Follow these steps to subsequently handle:
1) on wafer, apply photoresist, define active area and neighboring area, expose the intensive active region of pattern behind the exposure imaging, and the big area of the pattern of periphery is still covered by photoresist layer 5, shown in Fig. 9 b;
2) active area that exposes is carried out etching, stay about 200 ～700 polysilicon layers, used engraving method is a plasma etching, and etching reaction gas is chlorine (Cl
2) or hydrogen bromide (HBr).The neighboring area is owing to protected by photoresist, and polysilicon layer does not have etched.Shown in Fig. 9 c;
3) peel off residual photoresist with the remove photoresist mode of (ashing) or Wet-type etching (wet etch) of high temperature sintering, to wafer modification property (touch up) cmp, control low grinding head pressure, low grinding table and grinding head rotating speed are to form SiO
2With polysilicon at a pattern that copline is interlaced; The wafer vertical section schematic diagram of active area and neighboring area is shown in Fig. 9 d.Can make wafer enter successive process after the end.
The coating thickness of photoresist is on step 2 in the step 1)) in the material thickness that needs to eat-back decide, the thickness of photoresist should guarantee that after eat-backing the big area of the pattern of periphery still has photoresist residual, makes big area of the pattern not etched.
Modification property cmp is applicable to all work-table of chemicomechanical grinding mill, concrete controlling schemes is as follows: the rotating speed of grinding table is between 30 rpms to 70 rpms, the rotating speed of grinding head is between 30 rpms to 70 rpms, and the pressure of grinding head is that 1.0 pound per square inches are between 3.5 pound per square inches.
Claims (3)
1, a kind of method that reduces big pattern depression in metal and multi crystal silicon chemical mechanical milling is characterized in that comprising the following steps:
1) apply photoresist on the wafer that needs grind, exposure imaging makes big area of the pattern be covered by photoresist, exposes all the other zones;
2) zone of exposing is eat-back, stay 200 ～700 by the grinding-material layer;
3), make wafer enter successive process after the end to wafer modification property cmp.
2, the method for claim 1, wherein step 2) in etching method be the dryness etching, for metal etch, used etching gas is sulphur hexafluoride (SF
6); For the polysilicon etching, used etching gas is chlorine (Cl
2) or hydrogen bromide (HBr).
3, the method for claim 1, wherein the condition of modification property cmp is controlled to be in the step 3): the rotating speed of grinding table is between 30 rpms to 70 rpms, the rotating speed of grinding head is between 30 rpms to 70 rpms, and the pressure of grinding head is that 1.0 pound per square inches are between 3.5 pound per square inches.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100273714A CN100565812C (en) | 2006-06-07 | 2006-06-07 | In metal and multi crystal silicon chemical mechanical milling, reduce the method for big pattern depression |
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|---|---|---|---|
| CNB2006100273714A CN100565812C (en) | 2006-06-07 | 2006-06-07 | In metal and multi crystal silicon chemical mechanical milling, reduce the method for big pattern depression |
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| CN101086965A true CN101086965A (en) | 2007-12-12 |
| CN100565812C CN100565812C (en) | 2009-12-02 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102768944A (en) * | 2012-07-03 | 2012-11-07 | 上海华力微电子有限公司 | Method for repairing layer-removed sample |
| CN105984833A (en) * | 2015-02-04 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| CN112198416A (en) * | 2020-09-28 | 2021-01-08 | 上海华力集成电路制造有限公司 | Layer removing method for improving chip flatness |
-
2006
- 2006-06-07 CN CNB2006100273714A patent/CN100565812C/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102768944A (en) * | 2012-07-03 | 2012-11-07 | 上海华力微电子有限公司 | Method for repairing layer-removed sample |
| CN105984833A (en) * | 2015-02-04 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| CN105984833B (en) * | 2015-02-04 | 2017-12-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof |
| CN112198416A (en) * | 2020-09-28 | 2021-01-08 | 上海华力集成电路制造有限公司 | Layer removing method for improving chip flatness |
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| CN100565812C (en) | 2009-12-02 |
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Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING Effective date: 20111201 |
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Effective date of registration: 20111201 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Co-patentee after: Semiconductor Manufacturing International (Beijing) Corporation Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation Effective date of registration: 20111201 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Co-patentee after: Semiconductor Manufacturing International (Beijing) Corporation Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |
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Granted publication date: 20091202 Termination date: 20190607 |