CN106783586B - Method for improving memory unit word line chemical mechanical polishing process window - Google Patents

Method for improving memory unit word line chemical mechanical polishing process window Download PDF

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Publication number
CN106783586B
CN106783586B CN201710079403.3A CN201710079403A CN106783586B CN 106783586 B CN106783586 B CN 106783586B CN 201710079403 A CN201710079403 A CN 201710079403A CN 106783586 B CN106783586 B CN 106783586B
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word line
chemical mechanical
mechanical polishing
floating gate
memory cell
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CN106783586A (en
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陈宏�
曹子贵
王哲献
王卉
徐涛
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region

Abstract

A method for improving a memory cell wordline cmp process window, comprising: the first step is as follows: forming a semiconductor structure having a memory cell word line; the second step is as follows: performing chemical mechanical polishing treatment on the semiconductor structure; the third step: forming a hard mask layer on the semiconductor structure; the fourth step: and etching the hard mask layer so as to form a hard mask covering object on the exposed floating gate isolation side wall. In the invention, under the condition that the floating gate isolation side wall silicon nitride is exposed by the memory unit word line chemical mechanical polishing process, the hard mask covering is formed on the exposed floating gate isolation side wall, so that the floating gate isolation side wall is prevented from being corroded by solutions such as phosphoric acid, and the memory unit word line chemical mechanical polishing process window under the condition that the word line has smaller critical dimension can be effectively improved.

Description

Method for improving memory unit word line chemical mechanical polishing process window
Technical Field
The present invention relates to the field of semiconductor manufacturing; in particular, the present invention relates to the field of memory manufacturing; more particularly, the present invention relates to a method for improving the process window of the memory cell wordline cmp.
Background
Chemical Mechanical Polishing (CMP) is widely used for surface planarization process in semiconductor manufacturing. The chemical mechanical polishing process is to place the wafer on a rotating polishing pad, apply a certain pressure, and polish the wafer with chemical polishing liquid to planarize the wafer. In the process of grinding the silicon wafer by the chemical mechanical grinding equipment, the grinding agent (polishing solution) flows on the grinding pad through the pipeline, so that the grinding agent has a lubricating effect in the grinding process, and the grinding agent can also have a proper chemical reaction with the ground silicon wafer, so that the grinding removal speed is improved.
As shown in fig. 3, which is a schematic structural diagram of adjacent memory cells in a split-gate memory array in the prior art, each memory cell includes a substrate 10, a source 12 and a drain 11 formed in the substrate 10, and a gate structure located on the substrate, a bit line 20 is led out on the drain 11, a source line 30 is led out on the source 12, and a word line 40 located between the source line 30 and the bit line 20.
On one hand, if the critical dimension of the word line in the chemical mechanical polishing process is small, the chemical mechanical polishing process of the word line can cause the problem that the SiN material of the side wall is etched. Specifically, fig. 3 schematically illustrates a case where the critical dimension of the memory cell of the cmp process is small. As shown in fig. 3, when the critical dimension of the word line in the subsequent word line chemical mechanical polishing process is small (for example, the critical dimension of the word line is less than 220nm), the problem of exposing the silicon nitride SiN material of the sidewall (i.e., exposing the floating gate isolation sidewall 41) may occur.
On the other hand, if the critical dimension of the word line is large (e.g., the critical dimension of the word line is larger than 270nm) in the cmp process, word line residue may occur to block the floating gate silicon nitride during the removal process of the floating gate silicon nitride.
Therefore, it is desirable to provide a method for effectively improving the window of the memory cell wordline cmp process in the case of smaller critical dimension of the wordline.
Disclosure of Invention
The present invention provides a method for effectively improving the window of the chemical mechanical polishing process for the word line of the memory cell under the condition of small critical dimension of the word line, aiming at the above-mentioned defects in the prior art.
To achieve the above technical object, according to the present invention, there is provided a method for improving a process window of a memory cell word line chemical mechanical polishing, comprising: the first step is as follows: forming a semiconductor structure having a memory cell word line; the second step is as follows: performing chemical mechanical polishing treatment on the semiconductor structure; the third step: forming a hard mask layer on the semiconductor structure; the fourth step: and etching the hard mask layer so as to form a hard mask covering object on the exposed floating gate isolation side wall.
Preferably, in the method for improving the process window of the memory cell word line chemical mechanical polishing, the memory region of the semiconductor structure includes a substrate, a source and a drain formed in the substrate, and a floating gate structure located on the substrate, a source polysilicon is provided between the two floating gate structures, and a floating gate isolation sidewall is formed at a side of the floating gate structure.
Preferably, in the method for improving the memory cell word line cmp process window, the critical dimension of the memory cell word line is smaller in the cmp process.
Preferably, in the method for improving the memory cell word line chemical mechanical polishing process window, in the chemical mechanical polishing process, the critical dimension of the memory cell word line is less than 220 nm.
Preferably, in the method for improving the process window of the memory cell word line by chemical mechanical polishing, after the chemical mechanical polishing, the memory cell word line exposes the floating gate isolation sidewall adjacent to the memory cell word line.
Preferably, in the method for improving the process window of the memory cell word line chemical mechanical polishing, the material of the floating gate isolation sidewall is silicon nitride.
Preferably, in the method for improving the process window of the memory cell word line chemical mechanical polishing, the material of the hard mask layer is ethyl orthosilicate.
Preferably, in the method for improving the memory cell word line chemical mechanical polishing process window, the chemical mechanical polishing process is used for planarizing the word line polysilicon.
Preferably, in the method for improving the memory cell word line chemical mechanical polishing process window, the method for improving the memory cell word line chemical mechanical polishing process window is used for manufacturing a split gate structure memory.
In the invention, under the condition that the floating gate isolation side wall silicon nitride is exposed by the memory unit word line chemical mechanical polishing process, the hard mask covering is formed on the exposed floating gate isolation side wall, so that the floating gate isolation side wall is prevented from being corroded by solutions such as phosphoric acid, and the memory unit word line chemical mechanical polishing process window under the condition that the word line has smaller critical dimension can be effectively improved.
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A more complete understanding of the present invention, and the attendant advantages and features thereof, will be more readily understood by reference to the following detailed description when considered in conjunction with the accompanying drawings wherein:
fig. 1 schematically illustrates a structure diagram of an adjacent memory cell in a split gate structure memory array in the prior art.
Fig. 2 schematically shows a device structure diagram of specific process steps of a method for improving a memory cell word line cmp process window according to a preferred embodiment of the present invention.
Fig. 3 schematically shows a device structure diagram of specific process steps of a method for improving a memory cell wordline cmp process window according to a preferred embodiment of the present invention.
Fig. 4 schematically shows a device structure diagram of specific process steps of a method for improving a memory cell wordline cmp process window according to a preferred embodiment of the present invention.
Fig. 5 schematically shows a device structure diagram of specific process steps of a method for improving a memory cell wordline cmp process window according to a preferred embodiment of the present invention.
FIG. 6 schematically illustrates a flow chart of a method for improving a memory cell wordline CMP process window in accordance with a preferred embodiment of the present invention.
It is to be noted, however, that the appended drawings illustrate rather than limit the invention. It is noted that the drawings representing structures may not be drawn to scale. Also, in the drawings, the same or similar elements are denoted by the same or similar reference numerals.
Detailed Description
In order that the present disclosure may be more clearly and readily understood, reference will now be made in detail to the present disclosure as illustrated in the accompanying drawings.
First, it is to be understood that, unless otherwise specified, all technical and/or scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Although methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present invention, the exemplary methods and/or materials are described below. In case of conflict, the patent specification, including definitions, will control. In addition, the materials, methods, and examples are illustrative only and not necessarily for the purpose of limitation.
Fig. 3 is a schematic diagram of a memory cell with a small critical dimension according to a preferred embodiment of the present invention, and a device structure of a specific process step of a method for improving a process window of a memory cell word line chemical mechanical polishing according to a preferred embodiment of the present invention. Fig. 4 and 5 also schematically illustrate device structure diagrams of specific process steps of a method for improving a memory cell wordline cmp process window according to a preferred embodiment of the present invention. In addition, FIG. 6 schematically illustrates a flow chart of a method for improving a memory cell wordline CMP process window according to a preferred embodiment of the present invention.
For example, the method for improving the memory cell word line chemical mechanical polishing process window shown in fig. 2, 3, 4, 5 and 6 is used for manufacturing the split gate structure memory.
Specifically, as shown in fig. 2, 3, 4, 5 and 6, the method for improving the process window of the memory cell word line cmp process according to the preferred embodiment of the present invention comprises:
first step S1: forming a semiconductor structure having a memory cell word line;
in particular, FIG. 2 shows partial details of a particular device structure of a memory region of the semiconductor structure. At this time, as shown in fig. 2, since the word line 40 is high, it is necessary to perform the chemical mechanical polishing process on the word line 40.
Specifically, the memory region of the semiconductor structure includes: the memory comprises a substrate 10, a source electrode 12 and a drain electrode 11 which are formed in the substrate 10, and a gate structure which is positioned on the substrate, wherein a bit line 20 is led out from the drain electrode 11, a source line 30 is led out from the source electrode 12, and a word line 40 which is positioned between the source line 30 and the bit line 20. The gate structure has floating gate isolation spacers 41 formed between the gate structure and the word lines 40.
The material of the floating gate separation sidewall spacers 41 is, for example, silicon nitride.
Second step S2: a chemical mechanical polishing process is performed on the semiconductor structure. For example, in a particularly preferred embodiment, the chemical mechanical polishing process is preferably used to planarize the word line polysilicon.
Moreover, in the chemical mechanical polishing process, the critical dimension of the memory cell word line is small, for example, the critical dimension of the memory cell word line is less than 220 nm; in this case, as shown in fig. 3, after the cmp process, the memory cell word lines expose the floating gate isolation sidewall spacers 41 adjacent to the memory cell word lines.
Third step S3: forming a hard mask layer 50 on the semiconductor structure, as shown in fig. 5;
for example, in a particularly preferred embodiment, the material of the hard mask layer 50 is preferably tetraethylorthosilicate TEOS.
Fourth step S4: etching the hard mask layer 50 to form a hard mask covering 51 on the exposed floating gate isolation sidewall spacers 41, as shown in fig. 6; in other words, in the fourth step S4, the hard mask layer 50 is etched, and only the hard mask layer 50 (hard mask cover 51) on the exposed floating gate isolation sidewall spacers 41 is left.
In the invention, under the condition that the floating gate isolation side wall silicon nitride is exposed by the memory unit word line chemical mechanical polishing process, the hard mask covering is formed on the exposed floating gate isolation side wall, so that the floating gate isolation side wall is prevented from being covered by phosphoric acid H3PO4Such as etching, thereby effectively improving the window of the memory cell word line chemical mechanical polishing process under the condition of smaller critical dimension of the word line. For example, the invention can effectively improve the critical dimension of the word line of the memory cell to be less than 220nmThe memory cell wordline cmp process window in the case of (1).
In addition, it should be noted that the terms "first", "second", "third", and the like in the specification are used for distinguishing various components, elements, steps, and the like in the specification, and are not used for indicating a logical relationship or a sequential relationship between the various components, elements, steps, and the like, unless otherwise specified or indicated.
It is to be understood that while the present invention has been described in conjunction with the preferred embodiments thereof, it is not intended to limit the invention to those embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
It is to be further understood that the present invention is not limited to the particular methodology, compounds, materials, manufacturing techniques, uses, and applications described herein, as such may, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "an element" means a reference to one or more elements and includes equivalents thereof known to those skilled in the art. Similarly, as another example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. Thus, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Structures described herein are to be understood as also referring to functional equivalents of such structures. Language that can be construed as approximate should be understood as such unless the context clearly dictates otherwise.
Moreover, implementation of the method and/or system of embodiments of the present invention may include performing the selected task manually, automatically, or in combination. Moreover, the actual instrumentation and equipment according to embodiments of the method and/or system of the present invention may utilize an operating system to accomplish several selected tasks either in hardware, software, or a combination thereof.

Claims (7)

1. A method for improving a memory cell wordline cmp process window, comprising:
the first step is as follows: forming a semiconductor structure with a memory cell word line, wherein a memory region of the semiconductor structure comprises a substrate, a source electrode and a drain electrode which are formed in the substrate, and a floating gate structure positioned on the substrate, a bit line is led out from the drain electrode, an active line is led out from the source electrode, and the memory cell word line is positioned between the active line and the bit line;
the second step is as follows: performing chemical mechanical polishing treatment on the semiconductor structure, wherein the key size of the word line of the memory unit is smaller than 220nm in the chemical mechanical polishing treatment, and the word line of the memory unit exposes the floating gate isolation side wall adjacent to the word line of the memory unit after the chemical mechanical polishing treatment;
the third step: forming a hard mask layer on the semiconductor structure;
the fourth step: and etching the hard mask layer to form a hard mask covering object on the exposed floating gate isolation side wall, wherein the hard mask covering object exposes partial top surfaces of the word lines of the memory units so as to control the key size of the word lines of the memory units in the subsequent word line chemical mechanical polishing process.
2. The method of claim 1, wherein a source polysilicon is between two floating gate structures.
3. The method of claim 2, wherein the gate structure has a floating gate isolation sidewall formed between the gate structure and the word line.
4. The method of claim 1 or 2, wherein the material of the floating gate isolation sidewall spacers is silicon nitride.
5. The method of claim 1 or 2, wherein the material of the hard mask layer is ethyl orthosilicate.
6. The method of claim 1 or 2, wherein the CMP process is used to planarize the word line polysilicon.
7. The method for improving the memory cell word line CMP process window of claim 1 or 2, wherein the method for improving the memory cell word line CMP process window is used for manufacturing a split gate structure memory.
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CN109119403B (en) * 2017-06-22 2020-11-27 中芯国际集成电路制造(上海)有限公司 Mask for forming word line, semiconductor memory device and test structure

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5948698A (en) * 1996-10-15 1999-09-07 Kabushiki Kaisha Toshiba Manufacturing method of semiconductor device using chemical mechanical polishing
US6569770B2 (en) * 2001-06-28 2003-05-27 Chartered Semiconductor Manufacturing Ltd. Method for improving oxide erosion of tungsten CMP operations
CN102200686A (en) * 2010-03-26 2011-09-28 中芯国际集成电路制造(上海)有限公司 Mask layout and method for monitoring process window for chemical mechanical polishing by using the same
CN103346127A (en) * 2013-06-28 2013-10-09 上海宏力半导体制造有限公司 Flash memory device structure and manufacturing method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5948698A (en) * 1996-10-15 1999-09-07 Kabushiki Kaisha Toshiba Manufacturing method of semiconductor device using chemical mechanical polishing
US6569770B2 (en) * 2001-06-28 2003-05-27 Chartered Semiconductor Manufacturing Ltd. Method for improving oxide erosion of tungsten CMP operations
CN102200686A (en) * 2010-03-26 2011-09-28 中芯国际集成电路制造(上海)有限公司 Mask layout and method for monitoring process window for chemical mechanical polishing by using the same
CN103346127A (en) * 2013-06-28 2013-10-09 上海宏力半导体制造有限公司 Flash memory device structure and manufacturing method

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