CN101083285A - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- CN101083285A CN101083285A CN 200710108821 CN200710108821A CN101083285A CN 101083285 A CN101083285 A CN 101083285A CN 200710108821 CN200710108821 CN 200710108821 CN 200710108821 A CN200710108821 A CN 200710108821A CN 101083285 A CN101083285 A CN 101083285A
- Authority
- CN
- China
- Prior art keywords
- semiconductor device
- drain region
- channel region
- region
- district
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
A semiconductor device includes: a semiconductor substrate; a device active portion formed in the semiconductor substrate; a device isolation portion formed in the semiconductor substrate so as to surround the periphery of the device active portion; an insulating film stacked on the device active portion; and a gate electrode stacked on the insulating film. The device active portion includes: a source region and a drain region located opposite each other in a gate length direction, and a channel region interposed between the source region and the drain region. The channel region includes: a central region connecting the source and drain regions and having an approximately rectangular shape, and a protruding region protruding from one side end of the central region in a gate width direction. The channel region is located inwardly of the gate electrode when viewed in the stacking direction.
Description
Technical field
The present invention relates to a kind of semiconductor device, more particularly, relate to a kind of device isolation semiconductor device partly that uses STI (shallow isolating trough) to form that comprises.
Background technology
Semiconductor integrated circuit comprises insulated gate FET (hereinafter being called " transistor ").In described Semiconductor substrate, by device isolation part with these transistors each other electricity separate.The method that is used to form this device isolation part is to use STI (shallow trenchisolation: device isolation method shallow isolating trough).By in Semiconductor substrate, forming groove and forming STI with this groove of filling insulating material then.The STI that allows to form the device isolation part with narrower isolation width is the recent main flow device isolation method of manufacture craft on a small scale.
Yet in the semiconductor device that uses the STI device isolation method to make, described transistorized threshold voltage characteristic may be degenerated.Specifically, as shown in figure 13, described transistor shows the so-called protruding peak feature (representing with solid line) that increases leakage current, rather than its original transistors characteristics (dotting).Therefore compare with original transistors characteristics, increased leakage current.This phenomenon is because following former resulting: the threshold voltage in the core that is lower than described channel region that becomes of the threshold voltage in the part of the boundary vicinity between described STI and described channel region, so that cause that those parts that are positioned at described boundary vicinity are as parasitic transistor work.
A reason that forms described parasitic transistor is the shape of cross section of the boundary member between described STI and the described channel region.In Japanese Patent Application Publication No.2004-288873 (patent documentation 1), as shown in Figure 8, if shown in shape of cross section angle is arranged, electric field concentrates in the part (100A and 100B) of the boundary member between described STI and the described substrate, causes that the threshold voltage in these parts reduces.Another reason is that near the channel doping density of the boundary member between described STI and the described channel region reduces.During the annealing process of carrying out in semiconductor device fabrication process, the diffusion of impurities that is incorporated into described channel region causes near the impurity concentration of described STI to reduce in described STI.The impurity concentration that is reduced causes the threshold voltage of the boundary vicinity between described STI and the described channel region to descend.
In recent years, required semiconductor device to reduce its power consumption so that be applied to mobile device.Therefore, it is very important suppressing protruding peak feature.Be generally suitable for preventing that the method example of protruding peak feature from comprising: the method that wherein reduces the density of electric field by the shape of cross section that reduces the boundary member between described STI and the described channel region; And wherein in forming the step of described STI, before with the described groove of filling insulating material, impurity is incorporated in the side of described groove, thereby prevents the method that near the impurity concentration the described STI reduces.
Another kind of protruding peak feature prevents that method from being to construct transistor (for example, shown in the Fig. 1 in the patent documentation 1, Fig. 5 etc.) according to the mode that the boundary portion office between described STI and described channel region does not form parasitic transistor.In the transistor shown in the patent documentation 1, the boundary portion office between described STI and described channel region forms zone (the semiconductor region 1A that does not occur gate electrode on it
-2).This semiconductor region shows as the conduction type opposite with the drain region with described source area.For example, if source area and drain region are the n N-type semiconductor Ns, described semiconductor region then is the p N-type semiconductor N.Therefore, the boundary portion office between described STI and described channel region does not form parasitic transistor, so that protruding peak feature do not occur.
Usually, in n transistor npn npn manufacture craft, after forming gate electrode, n type impurity introduced in large quantities comprise in the zone that will become source area, drain region and gate electrode, thereby form described source area and drain region.
Yet, in patent documentation 1 described transistor, when a large amount of introducing n type impurity, need to cover and protection will become the zone of semiconductor region, so that form the semiconductor region that shows with the conduction type of the conductivity type opposite of described source area and drain region.According to patent documentation 1, the size of described semiconductor region is the same with the minimum feature size of photoetching little.This precise and tiny zone of the covering of pinpoint accuracy is very difficult.
Summary of the invention
Therefore, an object of the present invention is to provide a kind of semiconductor device, wherein suppressed protruding peak feature, and can be according to making than the easier mode of conventional semiconductor devices.
In one aspect of the invention, semiconductor device comprises Semiconductor substrate, device active part, device isolation part, dielectric film and gate electrode.In the main surface of described Semiconductor substrate, form described device active part.In the main surface of described Semiconductor substrate, form described device isolation part, so that center on the periphery of described device active part.Described insulating film layer is stacked on the described device active part.Described gate electrode layer is stacked on the described dielectric film.Described device active part comprises source area, drain region and channel region.Described source area and described drain region are provided with relative to one another along the grid length direction.Described channel region is inserted between described source area and the described drain region, and shows the conduction type different with the drain region with described source area.Described channel region comprises the center and protrudes the district.Described center connects described source area and described drain region, and has approximate rectangular shape.The side of described protrusion district along the grid width direction from described center is terminal to be protruded.Described channel region is when the inside that is positioned at described gate electrode when described laminated direction is watched.
In above-mentioned semiconductor device, because increased the channel length (length of sub-channel) of parasitic transistor, and increased the resistance of described parasitic transistor thus, can reduce leakage current by described parasitic transistor.Allow to suppress protruding peak feature like this.In addition, when when described laminated direction is watched, described channel region is positioned at the inside of described gate electrode.Therefore, different with conventional situation, do not need to cover and protect specific zone, allow to make described semiconductor device than the easier mode of conventional semiconductor devices.
In another aspect of the present invention, semiconductor device comprises Semiconductor substrate, device active part, device isolation part, dielectric film and gate electrode.In the main surface of described Semiconductor substrate, form described device active part.In the main surface of described Semiconductor substrate, form described device isolation part, so that center on the periphery of described device active part.Described insulating film layer is stacked on the described device active part.Described gate electrode layer is stacked on the described dielectric film.Described device active part comprises source area, drain region and channel region.Described source area and described drain region are provided with relative to one another along the grid length direction.Described channel region is inserted between described source area and the described drain region, and shows the conduction type different with the drain region with described source area.Described channel region comprises center and recessed district.Described center connects described source area and described drain region, and has approximate rectangular shape.The side end of the female district along the grid width direction from described center is to described center internal recess.When described laminated direction is watched, described channel region is positioned at the inside of described gate electrode.
Description of drawings
Figure 1A shows the plane graph according to the semiconductor device of embodiment of the present invention.
Figure 1B is the cross-sectional view of the semiconductor device that obtains along the Ib-Ib line among Figure 1A.
Fig. 1 C is the cross-sectional view of the semiconductor device that obtains along the Ic-Ic line among Figure 1A.
Fig. 1 D is the cross-sectional view of the semiconductor device that obtains along the Id-Id line among Figure 1A.
Fig. 2 shows the extension width of channel region and leaks the curve that concerns between the feature.
Fig. 3 shows the plane graph that independent common gate electrode is arranged on the example layout on a plurality of device active parts.
Fig. 4 is the plane graph that is used to explain the bottom end width that protrudes the district.
Fig. 5 is the plane graph that is used to explain the shape in described protrusion district.
Fig. 6 is another plane graph that is used to explain the shape in described protrusion district.
Fig. 7 is another plane graph that is used to explain the shape in described protrusion district.
Fig. 8 is the plane graph that is used to explain the shape of source area and described drain region.
Fig. 9 is another plane graph that is used to explain the shape of source area and described drain region.
Figure 10 is the plane graph that is used to explain extension area.
Figure 11 is another plane graph that is used to explain described extension area.
Figure 12 is the plane graph that is used to explain recessed district.
Figure 13 is the curve that is used to explain protruding peak feature.
Embodiment
Hereinafter, will be described in detail with reference to the attached drawings embodiments of the present invention.
(first execution mode)
Figure 1A shows the plane graph according to the semiconductor device of first embodiment of the invention.Figure 1B, Fig. 1 C and Fig. 1 D are the cross-sectional views of the described semiconductor device that obtains along the Ib-Ib among Figure 1A, Ic-Ic and Id-Id line respectively.
Described semiconductor device comprises Semiconductor substrate 100, device active part 101, device isolation part 102, gate insulating film 103 and gate electrode 104.
In the described main surface of described Semiconductor substrate 100, form described device active part 101.In the described main surface of described Semiconductor substrate 100, form, for example as STI (shallow isolating trough), described device isolation part 102 so that around the periphery of described device active part 101.On the described gate electrode 104 stacked described device active parts 101, gate insulating film 103 places between described gate electrode 104 and the device active part 101.
Described device active part 101 comprises source area 105, drain region 106 and channel region 107.Form described source area 105 and described drain region 106 toward each other in described grid length direction (length direction of described gate electrode 104).Described channel region 107 is formed between described gate regions 105 and the described drain region 106.Along described grid width direction (along the Width of described gate electrode 104), the grid width of described gate electrode 104 is greater than the length of described channel region 107, and all extend on described device isolation part 102 at the two ends of described gate electrode 104.
When described stacked direction is watched, described channel region 105 is positioned at from the inside direction of described gate electrode 104.Described channel region 107 comprises center 107a and protrudes district 107b and 107c.When described stacked direction is watched, described center 107a has along described grid length direction, the rectangular shape that extends to the side of described drain region 106 from the side of described source area 105.When described stacked direction is watched, the side of described protrusion district 107b along described grid width direction from described center 107a protrudes, and described protrusion district 107c another side along described grid width direction from described center 107a protrudes.
Described source area 105 has identical conduction type with described drain region 106.The conductivity type opposite of the conduction type of described channel region 107 and described source area and drain region 105 and 106.For example, when described source area and drain region 105 and 106 were the n type semiconductor layer, described channel region 107 was p type semiconductor layer.
Although not shown, in described gate electrode 104, described source area 105 and described drain region 106, form distribution by contacting.This distribution allow the semiconductor device shown in Figure 1A in semiconductor integrated circuit as transistor work.
Now, will the sub-channel that form in the channel region 107 shown in Fig. 1 be described.Described sub-channel be threshold voltage than the raceway groove that in described center 107a, forms low and raceway groove that occur in the part that is arranged in the described channel region 107 of the boundary vicinity of described device isolation part 102.
In channel region shown in Figure 1 107, form one of described sub-channel along the periphery of described protrusion district 107b.Compare with the situation that does not wherein form described protrusion district 107b (that is, under side of described center 107a and the situation that described device isolation part 102 contacts), therefore the length of the described sub-channel among the described protrusion district 107b become bigger.Do not compare with wherein forming described protrusion district 107b, this bigger length causes that the resistance of described sub-channel increases, thereby has reduced the quantity of electric charge by described sub-channel.For described protrusion district 107c is so equally, and has reduced wherein the quantity of electric charge by described sub-channel.Therefore, can reduce leakage current.
Fig. 2 shows the 3-D device simulation result who concerns between the extension width (that is the protrusion length of described protrusion district 107b and 107c) of described channel region 107 and the leakage current.Described emulation is that 0.1 micron and grid width (source width, drain region width) are that 0.16 micron transistor carries out at grid length.In simulation result shown in Figure 2, when the protrusion length in described protrusion district during more than or equal to 10nm, described leakage current obviously reduces.The lower limit of the described protrusion length in described protrusion district changes according to grid length, grid width and other parameters in the described semiconductor device.
As mentioned above, suppressed protruding peak feature.In addition, when when described stacked direction is watched, described channel region is positioned at from the inside direction of described gate electrode.Therefore, different with (shown in the patent documentation 1) conventional situation, do not need to cover and the protection specific region, allow to compare in the mode that is more prone to and make described semiconductor device with conventional situation.Promptly, when forming described device isolation part 102, just enough in the mode that in step subsequently, can form described protrusion district to described device active part Butut, thus do not need to increase another step (that is, being used to form the covering step of semiconductor region).Specifically, in such a way described device active part is carried out Butut, promptly in described grid width direction, making to become the length of that part of length of the device of channel region active part greater than which part that will become described source electrode and drain region 105 and 106, and just enough less than the length (grid width) of the described gate electrode that will form subsequently.
Equally, under conventional situation (shown in patent documentation 1), form semiconductor region in corresponding those parts in two ends owing to position on Semiconductor substrate and described gate electrode, layout has been forced many restrictions.For example, be used for the layout of inverter circuit etc., crossing a plurality of transistors (device active part) and arrange single common gate electrode.In this layout, can not be that each device active part forms semiconductor region as conventional situation.On the contrary, as shown in Figure 3, in the semiconductor device of this execution mode, in order to form inverter circuit, single common gate electrode can be set on a plurality of device active parts, and compare, reduce and forced at limiting to a number or amount on the described layout with conventional situation.
(the improvement embodiment of described device active part).
Next with reference to figure 4 to Figure 12, will describe the improvement embodiment of device active part 101 as shown in Figure 1 in detail.
(1) the bottom width in described protrusion district
As shown in Figure 4, the bottom width X of described protrusion district 107b can be less than the width Y of the side of described center 107a.That is,, can reduce leakage current if the bottom width in described protrusion district is less than or equal to the width of a side of described center.
(2) shape in described protrusion district
As shown in Figure 5, the shape that reduces gradually along direction of the described protrusion district 107b width that can have its projection from its bottom to its top.Alternatively, as shown in Figure 6, described protrusion district 107b can have opposite shape, that is, the width of its projection increases gradually along the direction from its bottom to its top.In addition, the top section of described protrusion district 107b can launch as shown in Figure 7.That is, described protrusion district 107b can have along protruding its protrusion width continually varying shape of direction that district 107b protrudes.It should be noted, shown in to protrude district 107b be as shown in Figure 5 circle.
(3) shape of the side end of described source area and described drain region
As shown in Figure 8, described source area 105 can be formed the width that makes its side end little by little increases in the direction towards described center 107a.Equally, as shown in Figure 9, the two ends of the side end of the described source area 105 that contacts with described channel region (center 107a, protrusion district 107b and 107c) can be circular.For described drain region 106 also is like this.
(4) extension area
As shown in figure 10, described device active part 101 can comprise extension area 108, and this extension area 108 extends from the edge that protrudes the distal portions of distinguishing 107c.That is, the part of described channel region can extend beyond described gate electrode 104.Described extension area 108 is the parts when the described channel region that extends when described stacked direction is watched, to described gate electrode 104 outside directions.The conduction type of described extension area 108 can be identical or different with the conduction type of described protrusion district 107c.When the conduction type of the conduction type of described extension area 108 and described protrusion district 107c was identical, described extension area 108 can be used as substrate contact region.
If determine to form described extension area 108 by considering, also can realize layout as shown in Figure 3 at diverse location.For example, as the device active region shown in the left-hand part of Fig. 3,, can form extension area 108 as shown in figure 11 if on described protrusion district 107c, there is not the end of described gate electrode 104.
(5) recessed district
As shown in figure 12, can form recessed district 201b and 201c at the two ends of described center 107a and replace protruding the district.The female district 201b is in described grid width direction, from the side of the described center 107a internal recess to described center.The female district 201c is in described grid width direction, from another side of described center internal recess to described center.In this case,, compare, further reduced leakage current with the situation that does not form the female district 201b because form sub-channel along the periphery of the female district 201b.
In the above description, if form among described at least protrusion district 107b or the 107c any one, can realize reducing the effect of leakage current.Equally, if form among the female district 201b at least or the 201c any one, also can realize reducing the effect of leakage current.
In addition, the protruding peak of existing typical case prevents method, for example be used to make the conglobate technology of shape of cross section of the boundary member between described STI and the described channel region, and the technology that is used for when forming described STI impurity being introduced the described side of described groove can be used with above-mentioned technology of the present invention.
Aspect suppressing protruding peak feature and reducing leakage current, semiconductor device according to the present invention is effectively, thereby has reduced the power consumption of described circuit.
Claims (10)
1. semiconductor device comprises:
Semiconductor substrate;
The device active part that forms at the first type surface of described Semiconductor substrate;
Form at the first type surface of described Semiconductor substrate, with device isolation part around the periphery of described device active part;
Be layered in the dielectric film on the described device active part; And
Be layered in the gate electrode on the described dielectric film;
Wherein, described device active part comprises:
Along source area and the drain region that the grid length direction is provided with relative to one another; And
Place between described source area and the described drain region, and present the channel region of different conduction-types with described source area and drain region;
Described channel region comprises:
Connect described source area and described drain region, and the center with approximate rectangular shape; And
The protrusion district that a side along the grid width direction from described center protrudes; And
When described laminated direction is watched, described channel region is positioned at from the inside direction of described gate electrode.
2. semiconductor device according to claim 1, wherein, the width of bottom, described protrusion district is equal to or less than the width of a side of described center.
3. semiconductor device according to claim 1 and 2, wherein, the direction that the width of the ledge in described protrusion district protrudes along described protrusion district changes continuously.
4. semiconductor device according to claim 3, wherein, the width of the ledge in described protrusion district reduces continuously along the direction that described protruding segments protrudes.
5. semiconductor device according to claim 3, wherein, the width of the ledge in described protrusion district increases continuously along the direction that described protruding segments protrudes.
6. semiconductor device according to claim 1, wherein, described device active part also comprises the extension area that extends from the edge of the distal portion in described protrusion district; And
When described extension area when described laminated direction is watched stretches out from described gate electrode.
7. semiconductor device according to claim 6, thereafter, described extension area has the identical conduction type of conduction type with described protrusion district.
8. semiconductor device according to claim 6, wherein, described extension area has the different conduction type of conduction type with described protrusion district.
9. semiconductor device according to claim 1, wherein, the length of the described ledge of described extension area is more than or equal to 10nm.
10. semiconductor device comprises:
Semiconductor substrate;
The device active part that forms at the first type surface of described Semiconductor substrate;
Form at the first type surface of described Semiconductor substrate, with device isolation part around the periphery of described device active part; And
Be layered in the gate electrode on the described dielectric film,
Wherein, described device active part comprises:
Along source area and the drain region that the grid length direction is provided with relative to one another; And
Place between described source area and the described drain region, and present the channel region of different conduction types with described source area and described drain region;
Described channel region comprises:
Connect described source area and described drain region, and the center with approximate rectangular shape; And
Side along the grid width direction from described center is to the recessed district of described center internal recess; And
When described stacked direction is watched, described channel region is positioned at from the inside direction of described gate electrode.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006151605 | 2006-05-31 | ||
| JP2006151605 | 2006-05-31 | ||
| JP2007110657 | 2007-04-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101083285A true CN101083285A (en) | 2007-12-05 |
Family
ID=38912679
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200710108821 Pending CN101083285A (en) | 2006-05-31 | 2007-05-31 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101083285A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103219385A (en) * | 2013-04-09 | 2013-07-24 | 上海华力微电子有限公司 | Symmetrical high-voltage MOS (Metal Oxide Semiconductor) device |
| CN103247692A (en) * | 2012-02-03 | 2013-08-14 | 索尼公司 | Thin-film transistor, display unit, and electronic apparatus |
| CN105322004A (en) * | 2014-07-11 | 2016-02-10 | 联华电子股份有限公司 | Field-effect transistor and method for forming field-effect transistor |
| WO2016034123A1 (en) * | 2014-09-02 | 2016-03-10 | 无锡华润上华半导体有限公司 | Semiconductor device and manufacturing method therefor |
| CN108231883A (en) * | 2016-12-15 | 2018-06-29 | 财团法人工业技术研究院 | Transistor arrangement |
| CN109786436A (en) * | 2017-11-14 | 2019-05-21 | 台湾积体电路制造股份有限公司 | Integrated chip and forming method thereof |
| CN111129011A (en) * | 2018-10-30 | 2020-05-08 | 台湾积体电路制造股份有限公司 | Integrated chip and forming method thereof |
| WO2022232988A1 (en) * | 2021-05-06 | 2022-11-10 | 京东方科技集团股份有限公司 | Display substrate and display device |
| US11810959B2 (en) | 2017-11-14 | 2023-11-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Transistor layout to reduce kink effect |
-
2007
- 2007-05-31 CN CN 200710108821 patent/CN101083285A/en active Pending
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103247692B (en) * | 2012-02-03 | 2019-07-09 | 株式会社日本有机雷特显示器 | Thin film transistor (TFT), display unit and electronic equipment |
| CN103247692A (en) * | 2012-02-03 | 2013-08-14 | 索尼公司 | Thin-film transistor, display unit, and electronic apparatus |
| CN103219385A (en) * | 2013-04-09 | 2013-07-24 | 上海华力微电子有限公司 | Symmetrical high-voltage MOS (Metal Oxide Semiconductor) device |
| CN105322004A (en) * | 2014-07-11 | 2016-02-10 | 联华电子股份有限公司 | Field-effect transistor and method for forming field-effect transistor |
| CN105322004B (en) * | 2014-07-11 | 2020-08-18 | 联华电子股份有限公司 | Field effect transistor and method of forming a field effect transistor |
| WO2016034123A1 (en) * | 2014-09-02 | 2016-03-10 | 无锡华润上华半导体有限公司 | Semiconductor device and manufacturing method therefor |
| CN105448734A (en) * | 2014-09-02 | 2016-03-30 | 无锡华润上华半导体有限公司 | Method for improving double-hump effect of device, and semiconductor device |
| CN108231883A (en) * | 2016-12-15 | 2018-06-29 | 财团法人工业技术研究院 | Transistor arrangement |
| CN109786436A (en) * | 2017-11-14 | 2019-05-21 | 台湾积体电路制造股份有限公司 | Integrated chip and forming method thereof |
| CN109786436B (en) * | 2017-11-14 | 2022-08-23 | 台湾积体电路制造股份有限公司 | Integrated chip and forming method thereof |
| US11688784B2 (en) | 2017-11-14 | 2023-06-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Transistor layout to reduce kink effect |
| US11810959B2 (en) | 2017-11-14 | 2023-11-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Transistor layout to reduce kink effect |
| CN111129011A (en) * | 2018-10-30 | 2020-05-08 | 台湾积体电路制造股份有限公司 | Integrated chip and forming method thereof |
| CN111129011B (en) * | 2018-10-30 | 2023-03-24 | 台湾积体电路制造股份有限公司 | Integrated chip and forming method thereof |
| WO2022232988A1 (en) * | 2021-05-06 | 2022-11-10 | 京东方科技集团股份有限公司 | Display substrate and display device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101083285A (en) | Semiconductor device | |
| US8362556B2 (en) | Semiconductor device | |
| JP5172654B2 (en) | Semiconductor device | |
| KR101666752B1 (en) | Semiconductor device and radio frequency module formed on high resistivity substrate | |
| US7618854B2 (en) | High frequency MOS transistor, method of forming the same, and method of manufacturing a semiconductor device including the same | |
| US20090166721A1 (en) | Quasi-vertical gated npn-pnp esd protection device | |
| US7081394B2 (en) | Device for electrostatic discharge protection and method of manufacturing the same | |
| JP2001102586A (en) | High breakdown voltage semiconductor device | |
| US10381441B2 (en) | Semiconductor device and method for manufacturing the same | |
| US8198684B2 (en) | Semiconductor device with drain voltage protection for ESD | |
| US10262997B2 (en) | High-voltage LDMOSFET devices having polysilicon trench-type guard rings | |
| KR101692625B1 (en) | Semiconductor device and radio frequency module formed on high resistivity substrate | |
| US20070278613A1 (en) | Semiconductor device | |
| US7821082B1 (en) | Method for increasing breaking down voltage of lateral diffused metal oxide semiconductor transistor | |
| US8853787B2 (en) | High voltage semiconductor device | |
| CN106257671B (en) | Semiconductor device and radio frequency module formed on high-resistance substrate | |
| CN102569392B (en) | Laterally diffused metal oxide semiconductor (LDMOS) transistor, layout method and manufacture method | |
| CN101297407B (en) | Transistor device and manufacturing method thereof | |
| US9972673B2 (en) | Electrostatic discharge protection device | |
| KR101710268B1 (en) | Passive device and radio frequency module formed on high resistivity substrate | |
| KR20190087052A (en) | Semiconductor device formed on a SOI substrate | |
| CN216054707U (en) | Semiconductor device for battery protection | |
| TWI708364B (en) | Semiconductor device and manufacturing method thereof | |
| CN112054061B (en) | Body contact structure of partially depleted silicon on insulator and manufacturing method thereof | |
| US11848328B2 (en) | Semiconductor device having STI regions |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Open date: 20071205 |