CN101071776A - 共漏极双半导体芯片级封装以及制造该种封装的方法 - Google Patents

共漏极双半导体芯片级封装以及制造该种封装的方法 Download PDF

Info

Publication number
CN101071776A
CN101071776A CNA2006101720467A CN200610172046A CN101071776A CN 101071776 A CN101071776 A CN 101071776A CN A2006101720467 A CNA2006101720467 A CN A2006101720467A CN 200610172046 A CN200610172046 A CN 200610172046A CN 101071776 A CN101071776 A CN 101071776A
Authority
CN
China
Prior art keywords
wafer
mosfet
common drain
level package
common
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2006101720467A
Other languages
English (en)
Other versions
CN100495669C (zh
Inventor
孙明
龚德梅
何约瑟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chongqing Wanguo Semiconductor Technology Co ltd
Alpha and Omega Semiconductor Ltd
Original Assignee
Alpha and Omega Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alpha and Omega Semiconductor Inc filed Critical Alpha and Omega Semiconductor Inc
Publication of CN101071776A publication Critical patent/CN101071776A/zh
Application granted granted Critical
Publication of CN100495669C publication Critical patent/CN100495669C/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本发明提供一种共漏极双MOSFET芯片级封装以及制造该封装的方法。制造大量共漏极双MOSFET芯片级封装的方法包括以下步骤：提供具有在其上设置的大量共漏极双MOSFET器件的晶片，隔离晶片的背漏极金属表面，在每个共漏极双MOSFET器件上进行球栅阵列区的底部凸点金属化，在晶片上漏印焊料掩模以暴露球栅阵列区，回流焊料膏或预形成的焊料球以形成焊料凸点的球栅阵列，和将晶片切割成大量芯片级封装。

Description

共漏极双半导体芯片级封装以及制造该种封装的方法
技术领域
本发明总体涉及一种功率半导体封装，尤其涉及共漏极双MOSFET芯片级封装以及制造该种封装的方法。
背景技术
随着诸如手机通讯产品、便携式数字助理和便携式个人电脑等的移动设备的广泛应用，独立电子元件和器件的尺寸、重量和价格就成为评价设计成功与否的关键要素。例如，用于这样的设备的电池组保护装置可以要求结合了若干占据小面积图形的分立芯片的印刷电路板(PCB)。
一种这样的现有技术电池保护电路板在名为“具有集成无源元件的电池保护电路”，公布号为US 2004/0256738 A1的美国专利申请中已经公开。为了达到空间守恒和效率，上述公开的PCB具有嵌入到PCB体内的无源元件，所述PCB带有诸如以共漏极结构连接的充电MOSFET和放电MOSFET的有源器件和用于控制所述器件的控制IC。表面安装器件和嵌入的无源元件的互联通过适当的导电路径等实现。充电MOSFET和放电MOSFET限定了一种双向MOSFET芯片级封装。
芯片级封装(CSP)是将封装结构的尺寸减少到芯片尺寸封装的晶片水平的封装过程。在应用于集成电路(IC)的CSP中，集成电路的外围键合区通过重新分布层路径连接到I/O焊接球，这些导电的I/O焊接球或焊料凸点能够通过倒装法或载带自动键合附贴将IC连接到诸如PCB的高水平的电路结构上。
与减小包括共漏极双MOSFET芯片封装的独立电子元件的尺寸、重量和成本的需求相一致，技术上有对于这种类型的具有小足印的器件封装的需要。对于具有低轮廓剖面和良好的热耗散的共漏极双MOSFET器件封装有进一步的要求，要求共漏极双MOSFET器件封装有更轻的重量，低电感或者无电感，还进一步要求共漏极双MOSFET器件封装具有低Rds(on)。对于制造这样的共漏极双MOSFET封装还要求低成本的生产工艺。
发明内容
本发明提供了一种达到技术上的要求的制造具有共漏极结构的共漏极双MOSFET芯片级封装的新颖的晶片水平的工艺。该工艺包括用介电材料涂层隔离晶片的背漏极金属表面的步骤。所述介电材料涂层提供对于背漏极金属表面的保护，使其免受包括形成球栅阵列凸点的后继工艺过程的影响。所述涂层进一步增加了晶片的机械强度，有利地提高了制造共漏极双MOSFET芯片级封装的生产率和产量。
根据本发明的一个方面，制造大量共漏极双MOSFET芯片级封装的方法包括提供具有在其上设置的大量共漏极双MOSFET器件的晶片，隔离晶片的背漏极金属表面，在每个共漏极双MOSFET器件上进行球栅阵列区的底部凸点金属化，在晶片上漏印焊料掩模以暴露球栅阵列区，回流焊料膏或预形成的焊料球以形成焊料凸点的球栅阵列，和将晶片切割成大量芯片级封装的步骤。
根据本发明的另一方面，共漏极双MOSFET芯片级封装包括一个隔离层，所述隔离层相邻于双MOSFET芯片级封装的背漏极金属表面设置。
为了使下文对本发明的详尽描述得到更好理解，也使本发明对技术领域的贡献受到更好的评价，上文的概述相当宽泛地概括了本发明的重要特征。当然本发明还有其他特征，这些特征将在下文进行描述并构成本文附后的权利要求的主题。
在这些方面，在详尽解释本发明的至少一个实施例之前，应该理解的是，本发明的应用并不局限于下文描述和附图显示的功能元件的细节以及这些元件的排布，本发明还可以有其他的实施方式以及可以用多种方式实现和完成。还应该理解，本文使用的措辞和术语以及摘要是为了描述的目的而不应被认为是对本发明的限制。
这样，本技术领域中的熟练技术人员将理解，作为本发明的基础的原理可以被容易地用作实现本发明的若干目的的其他方法和系统的设计基础。因此，重要的是，权利要求应被认为包括没有背离本发明的精神和范围的所有等同的结构。
附图说明
通过参照附图将使本发明更容易理解，同时本发明的众多特征和优点对于本技术领域的熟练技术人员也就更显而易见。
图1是根据本发明的制造工艺的流程图；
图1A是根据本发明的图1所示的制造工艺的示意图；
图2是根据本发明的载带自动键合附贴的示意图；
图3A是显示没有模制成型和底部填充的电路板布局的示意图；
图3B是显示根据本发明的可选择的底部填充物的示意图。
具体实施方式
本发明公开了一种制造大量共漏极双MOSFET芯片级封装的晶片水平的方法。该方法有利地提供一种制造工艺，通过该工艺共漏极双MOSFET芯片级封装可以用7至8mil(密耳)厚度的薄晶片形成，现有技术工艺中遇到的包括由于晶片挠曲引起的产量损耗的问题通过本发明的新颖工艺而得到克服。
如图1所示，总体由100标示的制造共漏极双MOSFET的方法包括提供具有在其上设置的大量共漏极双MOSFET器件的晶片的第一步骤105。在步骤115中，晶片的背漏极金属表面被隔离。所述背漏极金属表面可以用固化的介电材料涂层隔离。所述固化的介电材料涂层提供对背漏极金属表面的保护使其不受包括底部凸点金属化和球栅阵列凸点形成的后继工艺的影响。所述涂层进一步增加了晶片的机械强度，在共漏极双MOSFET芯片级封装的生产过程中有利地提高了产量。
底部凸点金属化(UBM)步骤120可包括Ni/Au金属化工艺，该Ni/Au金属化工艺已经在申请日为2004年9月30日，题为“金属化半导体芯片的源极、栅极和漏极接触区域的晶片水平的方法”的共同转让的美国专利申请系列号11/242,625中公开。Ni/Au金属化工艺有利地提供了在凸点栅阵列上形成的Ni层以及保护Ni层的Au层。因为Ni没有扩散进凸点栅阵列接触区域的Al，由Ni/Al组成的金属间层就提供了焊料凸点可以附接到其上的高密度层。
在步骤130中可以漏印焊料掩模133，从而提供用于焊料膏或预形成的焊料球回流的掩模以在步骤140中形成焊接BGA焊料凸点。独立的芯片可在步骤150中切割。然后共漏极双MOSFET芯片级封装就被准备好向PCB进行表面安装。
图1A用示意图显示了制造共漏极双MOSFET的方法100。诸如7至8mil(密耳)晶片的薄晶片155可被接纳在加工机械中。该晶片可以具有已设置在其上的大量共漏极双MOSFET器件160。共漏极双MOSFET160可以包括为避免受到损坏而用固化的介电材料涂层165隔离的背漏极金属表面163，所述固化的介电材料涂层165可向共漏极双MOSFET160进一步提供机械强度。
底部凸点金属化可包括用Ni/Au的凸点栅阵列的金属化。可以进行焊料掩模170的漏印从而为焊膏或预形成的焊料球回流提供掩模以形成焊接BGA焊料凸点173。然后晶片155可以被切割以形成大量共漏极双MOSFET芯片级封装210。
如图2所示，载带自动键合附贴工艺可以包括载带200，包括共漏极双MOSFET芯片级封装210，包括电阻215和电容217的分立无源元件以及控制IC芯片级封装220的大量电子元件被附装到载带200上。该载带自动键合附贴工艺可被用来将共漏极双MOSFET芯片级封装210，分立无源元件215和217以及控制IC芯片级封装220附贴到PCB230上。
图3A显示了安装到PCB230上但没有模制成型或底部填充的共漏极双MOSFET芯片级封装210和IC芯片级封装220，而图3B显示了被模制并且用底部填充物300进行底部填充的同一个元件。涉及底部填充物300的使用的各种考虑包括芯片尺寸的匹配，Pb/Sn焊料的使用，机械性能以及器件应用。
本发明的制造大量共漏极双MOSFET芯片级封装的晶片水平的方法提供了一种工艺，通过该工艺共漏极双MOSFET芯片级封装可以用7至8密耳的薄晶片形成。该晶片水平的方法进一步提供了可靠且成本有效的封装。根据本发明的共漏极双MOSFET芯片级封装具有良好的热耗散和短互联路径。本发明的封装也提供了低电感和低电阻以及紧凑的封装结构。本封装可对当前的表面安装装配工艺进行修正。
当然，应该理解的是，上文的叙述涉及本发明的优选实施例以及可以对其进行各种修改而不背离附后的权利要求阐述的本发明的精神和范围。

Claims (12)

1.一种制造大量共漏极双MOSFET芯片级封装的方法，其特征在于，该方法包括以下步骤：
提供具有在其上设置的大量共漏极双MOSFET器件的晶片；
隔离晶片的背漏极金属表面；
在每个共漏极双MOSFET器件上进行球栅阵列区的底部凸点金属化；
在晶片上漏印焊料掩模以暴露球栅阵列区；
回流焊料膏以形成球栅阵列焊料凸点；和
将晶片切割成大量芯片级封装。
2.如权利要求1所述的方法，其特征在于，其中隔离背漏极金属表面包括用固化的介电材料进行隔离。
3.如权利要求1所述的方法，其特征在于，其中所述底部凸点金属化包括Ni/Au镀覆。
4.一种共漏极双MOSFET芯片级封装，其特征在于，该封装包括：
隔离层，该隔离层相邻于共漏极双MOSFET芯片的背漏极金属表面设置。
5.如权利要求4所述的共漏极双MOSFET芯片级封装，其特征在于，其中所述隔离层包括固化的介电材料。
6.如权利要求4所述的共漏极双MOSFET芯片级封装，其特征在于，该封装进一步包括Ni/Au镀覆的底部凸点金属化区域。
7.如权利要求6所述的共漏极双MOSFET芯片级封装，其特征在于，该封装进一步包括形成于凸点金属化区域上的焊料凸点的球栅阵列。
8.如权利要求7所述的共漏极双MOSFET芯片级封装，其特征在于，其中所述焊料凸点通过焊料膏的回流形成。
9.如权利要求7所述的共漏极双MOSFET芯片级封装，其特征在于，其中所述焊料凸点通过预形成的焊料球的回流形成。
10.一种制造大量共漏极双MOSFET芯片级封装的方法，其特征在于，该方法包括以下步骤：
提供具有在其上设置的大量共漏极双MOSFET器件的晶片；
隔离晶片的背漏极金属表面；
在每个共漏极双MOSFET器件上进行球栅阵列区的底部凸点金属化；
在晶片上漏印焊料掩模以暴露球栅阵列区；
回流预形成的焊料球以形成球栅阵列焊料凸点；和
将晶片切割成大量芯片级封装。
11.如权利要求10所述的方法，其特征在于，其中隔离背漏极金属表面包括用固化的介电材料进行隔离。
12.如权利要求10所述的方法，其特征在于，其中所述底部凸点金属化包括Ni/Au镀覆。
CNB2006101720467A 2005-12-22 2006-12-21 共漏极双半导体芯片级封装以及制造该种封装的方法 Active CN100495669C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/316,692 US20070148875A1 (en) 2005-12-22 2005-12-22 Common drain dual semiconductor chip scale package and method of fabricating same
US11/316,692 2005-12-22

Publications (2)

Publication Number Publication Date
CN101071776A true CN101071776A (zh) 2007-11-14
CN100495669C CN100495669C (zh) 2009-06-03

Family

ID=38194375

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2006101720467A Active CN100495669C (zh) 2005-12-22 2006-12-21 共漏极双半导体芯片级封装以及制造该种封装的方法

Country Status (3)

Country Link
US (1) US20070148875A1 (zh)
CN (1) CN100495669C (zh)
TW (1) TWI367534B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110289340A (zh) * 2019-05-09 2019-09-27 无锡光磊电子科技有限公司 倒装led芯片焊盘及其制备方法
CN110416096A (zh) * 2018-06-07 2019-11-05 李湛明 GaN功率器件的缺陷可容布局和封装

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080290482A1 (en) * 2007-05-25 2008-11-27 National Semiconductor Corporation Method of packaging integrated circuits

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6306680B1 (en) * 1999-02-22 2001-10-23 General Electric Company Power overlay chip scale packages for discrete power devices
CN1315195C (zh) * 2000-02-10 2007-05-09 国际整流器有限公司 在单面上带块形连接的垂直导电倒装芯片式器件
US6326698B1 (en) * 2000-06-08 2001-12-04 Micron Technology, Inc. Semiconductor devices having protective layers thereon through which contact pads are exposed and stereolithographic methods of fabricating such semiconductor devices
US6762503B2 (en) * 2002-08-29 2004-07-13 Micron Technology, Inc. Innovative solder ball pad structure to ease design rule, methods of fabricating same and substrates, electronic device assemblies and systems employing same
US7135385B1 (en) * 2004-04-23 2006-11-14 National Semiconductor Corporation Semiconductor devices having a back surface protective coating

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110416096A (zh) * 2018-06-07 2019-11-05 李湛明 GaN功率器件的缺陷可容布局和封装
CN110416096B (zh) * 2018-06-07 2023-04-18 苏州量芯微半导体有限公司 GaN功率器件的缺陷可容布局和封装
CN110289340A (zh) * 2019-05-09 2019-09-27 无锡光磊电子科技有限公司 倒装led芯片焊盘及其制备方法
CN110289340B (zh) * 2019-05-09 2022-03-29 无锡光磊电子科技有限公司 倒装led芯片焊盘的制备方法

Also Published As

Publication number Publication date
CN100495669C (zh) 2009-06-03
TW200746327A (en) 2007-12-16
US20070148875A1 (en) 2007-06-28
TWI367534B (en) 2012-07-01

Similar Documents

Publication Publication Date Title
US7872343B1 (en) Dual laminate package structure with embedded elements
CN110034106B (zh) 封装结构及其制造方法
CN102487021B (zh) 形成用于倒装半导体管芯的焊盘布局的半导体器件和方法
CN102237281B (zh) 半导体器件及其制造方法
CN102487020B (zh) 形成引线上凸块互连的半导体器件和方法
US5903052A (en) Structure for semiconductor package for improving the efficiency of spreading heat
US9721925B2 (en) Semiconductor device and method of forming overlapping semiconductor die with coplanar vertical interconnect structure
CN102244012B (zh) 半导体器件及其制造方法
CN102157391B (zh) 半导体器件和形成垂直互连的薄外形wlcsp的方法
CN101996895B (zh) 半导体器件及其制造方法
US6803254B2 (en) Wire bonding method for a semiconductor package
CN101996896B (zh) 半导体器件及其制造方法
US7205178B2 (en) Land grid array packaged device and method of forming same
TWI528465B (zh) 半導體元件和形成具有嵌入半導體晶粒的預先製備散熱框之方法
CN102386113A (zh) 一种半导体器件及其制造方法
US20070216008A1 (en) Low profile semiconductor package-on-package
US8169071B2 (en) Semiconductor device having vertically offset bond on trace interconnects on recessed and raised bond fingers
CN103681607A (zh) 半导体器件及其制作方法
KR101119708B1 (ko) 집적 회로 다이를 패키징하는 방법
KR101519062B1 (ko) 반도체 소자 패키지
WO2007027790A2 (en) Reversible-multiple footprint package and method of manufacturing
US11869829B2 (en) Semiconductor device with through-mold via
US7846773B2 (en) Multi-chip semiconductor package
US7361995B2 (en) Molded high density electronic packaging structure for high performance applications
US20080251938A1 (en) Semiconductor chip package and method of manufacture

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C41 Transfer of patent application or patent right or utility model
COR Change of bibliographic data

Free format text: CORRECT: ADDRESS; FROM: CANON YARD, NO.22, HAMILTONIAN VICTORIA STREET,BAIMUDA TO: NO.495,SUNNYVALE MERCURY AVENUE, CALIFORNIA, USA

TR01 Transfer of patent right

Effective date of registration: 20100412

Address after: No. 495 California Avenue, Sunnyvale mercury

Patentee after: Alpha and Omega Semiconductor Inc.

Address before: Bermuda Hamilton No. 22 Vitoria street Canon hospital

Patentee before: ALPHA & OMEGA SEMICONDUCTOR, Ltd.

CP01 Change in the name or title of a patent holder
CP01 Change in the name or title of a patent holder

Address after: No. 495 California Avenue, Sunnyvale mercury

Patentee after: ALPHA & OMEGA SEMICONDUCTOR, Ltd.

Address before: No. 495 California Avenue, Sunnyvale mercury

Patentee before: Alpha and Omega Semiconductor Inc.

TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20170713

Address after: Chongqing District of Beibei city and the high and New Technology Industrial Park Road No. 5 of 407 Hon

Patentee after: Chongqing Wanguo Semiconductor Technology Co.,Ltd.

Address before: Bermuda Hamilton Church 2 Cola Lunden House Street

Patentee before: ALPHA & OMEGA SEMICONDUCTOR, Ltd.

Effective date of registration: 20170713

Address after: Bermuda Hamilton Church 2 Cola Lunden House Street

Patentee after: ALPHA & OMEGA SEMICONDUCTOR, Ltd.

Address before: No. 495 California Avenue 94085 Sunnyvale mercury

Patentee before: ALPHA & OMEGA SEMICONDUCTOR, Ltd.

PE01 Entry into force of the registration of the contract for pledge of patent right
PE01 Entry into force of the registration of the contract for pledge of patent right

Denomination of invention: Common drain dual semiconductor chip scale package and method of fabricating same

Effective date of registration: 20191210

Granted publication date: 20090603

Pledgee: Chongqing Branch of China Development Bank

Pledgor: Chongqing Wanguo Semiconductor Technology Co.,Ltd.

Registration number: Y2019500000007

PC01 Cancellation of the registration of the contract for pledge of patent right
PC01 Cancellation of the registration of the contract for pledge of patent right

Granted publication date: 20090603

Pledgee: Chongqing Branch of China Development Bank

Pledgor: Chongqing Wanguo Semiconductor Technology Co.,Ltd.

Registration number: Y2019500000007