CN101071632A - Storage unit detecting circuit with power-saving and speed promotion capability and its method - Google Patents
Storage unit detecting circuit with power-saving and speed promotion capability and its method Download PDFInfo
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- CN101071632A CN101071632A CN 200610081943 CN200610081943A CN101071632A CN 101071632 A CN101071632 A CN 101071632A CN 200610081943 CN200610081943 CN 200610081943 CN 200610081943 A CN200610081943 A CN 200610081943A CN 101071632 A CN101071632 A CN 101071632A
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Abstract
The invention discloses a memory cell detection circuit with power-saving and speed-raising abilities and the detecting method thereof, where a detection signal is supplied to generate a first pulse signal and a second pulse signal, the first pulse controls to switch on the memory cell detection circuit and after a detection result is obtained, latches the detection result and switches off the memory cell detection circuit, so as to save power consumption of the memory cell detection circuit; the second pulse signal controls to make the memory cell detection circuit fast change from a first state to a second state so as to obtain the detection result to raise the detecting speed of the memory cell detection circuit.
Description
Technical field
Relevant a kind of storage unit detecting circuit of the present invention and method.Specifically, relevant a kind of storage unit detecting circuit and the method thereof of the present invention with power saving and speed promotion capability.
Background technology
Storer is indispensable element in the modern various electronic installation, and all with the form appearance of memory cell array, promptly have the capable and multiple memory cell row of multiple memory cell on the array, and described storage unit constitutes with a MOS transistor normally.When the desire selection is moved to a storage unit, one array selecting signal is provided to select the row at this storage unit place earlier, then delegation selects signal to be provided to select the row at this storage unit place, can write and detect (reading) action this moment to this storage unit, with with in the data write storage unit, or storage unit institute deposit data read, wherein detect carrying out of action with a storage unit detecting circuit.
The connection diagram that is storer and conventional detection circuitry thereof shown in Figure 1, wherein storer 12 be by row position 0 to a row position n and row position 0 to the row position memory cell array form that m constituted, signal deteching circuit 11 can in time detect this storage unit in that a storage unit to be detected is selected.
Figure 2 shows that the storer of Fig. 1 and the detailed maps of conventional detection circuitry thereof.As shown in the figure, this storage unit detecting circuit 21 comprises a first transistor M1, a transistor seconds M2, a not gate INV and closes/opens and uses rejection gate NOR, and is connected to described storage unit 22 with this transistor M2.Transistor M1 can be a PMOS transistor or nmos pass transistor (being the PMOS transistor shown in the figure), and receives a direct current voltage VDD with its source electrode (or drain electrode), and its grid is connected to ground.Transistor M2 is a nmos pass transistor, and its drain electrode is joined by the drain electrode (or source electrode) of a node A and transistor M1, and its grid joins with an output terminal of closing/opening with rejection gate NOR, and its source electrode then joins by a Node B and this storer 22.This storer 22 has the capable and multiple memory cell of multiple memory cell row, promptly as shown in Figure 1, but only shows a row position MOS transistor M3 and the position MOS transistor M4 of delegation among the figure, and with this row position MOS transistor M4 as a storage unit to be detected.
When data are " 1 " among the transistor M4, itself conducting, DC voltage VDD provides an electric current flow through transistor M1, M2, M3 and M4, and the electric current of flowing through on this transistor M1 and M4 equates to end, and this moment, the voltage of node A was low level voltage, i.e. " 0 "; This low level voltage is output as high-level voltage " 1 " via phase inverter INV.When data are " 0 " among the transistor M4, itself not conducting, transistor M2 and M3 charging on the path that this moment, transistor M1 constituted node A, B and C are output as a low level signal " 0 " via phase inverter INV when the voltage height to of node A is fixed in advance.When on the path of node A, B and C formation a heavy load being arranged, transistor M1 certainly will need can be charged to a specific potential for a long time and be output as " 0 " by phase inverter INV, and promptly the detected speed that gets of " 0 " data is slow in this storage unit.Therefore, present storage unit detection technique truly has the necessity that is promoted on speed.
In addition, an external signal CE is in order to open and to close this testing circuit 21 among the figure.When signal CE is when continuing the low level signal, rejection gate NOR can be in always and use electricity condition, and the path that transistor M4 also can make transistor M1, M2, M3 and M4 constitute when conducting is in uses electricity condition, data promptly do not need the idea of electricity consumption not to be inconsistent after detected in this and a certain storage unit, so be to be in a power consumption state.Therefore, at present storage unit detecting circuit truly has in addition necessity of electricity-saving function.
In view of the above problems, the inventor develops a kind of storage unit detecting circuit with power saving and pulling speed ability at last through intensive test and research, and it is enough to overcome the shortcoming of prior art, and has industry applications.
Summary of the invention
In view of above-mentioned, purpose of the present invention promptly is to propose a kind of the have storage unit detecting circuit of power saving ability and the method for saving storage unit detecting circuit, so as to saving the power consumption of this storage unit detecting circuit.
Another object of the present invention is to propose a kind of method method that has the storage unit detecting circuit of pulling speed ability and promote the detection speed of storage unit circuit, so as to quickening the detection speed of this storage unit detecting circuit.
An aspect of the present invention is a kind of storage unit detecting circuit, it comprises a main detecting unit, a digital unit, a latch lock unit, an On/Off unit and a delay cell, this main detecting unit is connected in series in regular turn with a chosen particular column position storage unit and a particular row position storage unit, have one first state and one second state, and when this first and second state, export an anti-phase testing result of this storage unit; This digital unit is in order to anti-phase in addition and obtain the testing result of a digital form to this anti-phase testing result; This latch lock unit is in order to this testing result breech lock in addition; The running of this main detecting unit is opened or closes in this On/Off unit in order to control; This delay cell has one first delay circuit, in order to receive a detection signal, and export one first according to this detection signal and postpone pulse wave signal, when this detection signal is initial, make this main detecting unit of unlatching to control this On/Off unit, and control this latch lock unit this testing result of breech lock when this main detecting unit reaches this second state.
Another storage unit detecting circuit of the present invention comprises a main detecting unit, a digital unit, an On/Off unit, a speed lift unit and a delay cell; This main detecting unit is connected in series in regular turn with a chosen particular column position storage unit and a particular row position storage unit, has one first state and one second state, and export an anti-phase testing result of this storage unit when this first and second state; This digital unit is in order to anti-phase in addition and obtain the testing result of a digital form to this anti-phase testing result; The running of this main detecting unit is opened or closes in this On/Off unit in order to control; This speed lift unit is predetermined to be an opening, so that this main detecting unit reaches this second state sooner by this first state after this On/Off unit is unlocked, this speed lift unit also is unlocked after this main detecting unit reaches this second state once again; This delay cell comprises one first delay circuit, in order to receive a detection signal, and export one first according to this detection signal and postpone pulse wave signal, close this speed lift unit in order to be controlled at this detection signal after the initial schedule time, and be controlled at and open this speed lift unit when this main detecting unit reaches this second state.
Another aspect again of the present invention is a kind of method of saving the power consumption of storage unit detecting circuit, and it comprises the following step: open this storage unit detecting circuit; Treat that this storage unit detecting circuit is unlocked schedule time and after obtaining a testing result this testing result of breech lock; And close this storage unit detecting circuit.
Of the present invention again again an aspect be a kind of method that promotes the detection speed of storage unit detecting circuit, it comprises the following step: promote this storage unit detecting circuit from one first state to, second state, wherein this first state is meant that this storage unit detecting circuit exports one first state as a result the time, and this second state is meant that this storage unit detecting circuit exports one second state as a result the time; And when treating that this second result is obtained, the carrying out that stops this lifting step.
By to enforcement of the present invention, the operation of storage unit detecting circuit can save energy and fast speed under finish.
Other purpose of the present invention, feature and effect can further be understood after consulting civilian later embodiment.
Description of drawings
Preferred embodiment of the present invention cooperates following accompanying drawing to be illustrated, wherein:
Fig. 1 is the connection diagram of storer and conventional detection circuitry thereof;
Fig. 2 is the storer of Fig. 1 and the detailed maps of conventional detection circuitry thereof;
Fig. 3 is the functional block diagram with storage unit detecting circuit of power saving and speed promotion capability of the present invention;
Fig. 4 is of the present invention one synoptic diagram with storage unit detecting circuit preferred embodiment of power saving and speed promotion capability;
Fig. 5 A and Fig. 5 B are the coherent signal oscillogram of the delay circuit of storage unit detecting circuit of the present invention;
Fig. 6 is for producing a circuit embodiments synoptic diagram of Fig. 5 coherent signal waveform;
Fig. 7 is the process flow diagram of method of the power consumption of saving storage unit detecting circuit of the present invention; And
Fig. 8 is the process flow diagram of method of the detection speed of lifting storage unit detecting circuit of the present invention.
Embodiment
The present invention discloses a kind of storage unit detecting circuit and method thereof with power saving and speed promotion capability, its content will be described as follows by preferred embodiment, yet described embodiment only is preferably wherein, enforcement of the present invention is not limited only to described preferred embodiments, the personage who is familiar with the same domain technology can be according to except that carrying out the present invention by the embodiment through both having disclosed, it can derive out other embodiment according to spirit of the present invention, and described embodiment all ought belong to scope of the present invention.
See also Fig. 3, it is the calcspar with storage unit detecting circuit of power saving and speed promotion capability of the present invention.As shown in the figure, this storage unit detecting circuit 30 comprises a main detecting unit 31, a digital unit 32, a latch lock unit 33, an On/Off unit 34 1 speed lift units 35 and a delay cell 36.This main detecting unit 31 joins with a chosen cell group, have one first state and one second state, and when this first and second state, export an anti-phase testing result of this storage unit, this cell group comprises row position storage unit and delegation's position storage unit, and this row position storage unit is a storage unit to be detected.This digital unit 32 is in order to this anti-phase testing result phase in addition, to obtain the testing result DR of a digital form.This latch lock unit 33 is in order to this testing result DR breech lock in addition, is closed when obtaining this anti-phase testing result DR so as to making main detecting unit 31, to save the power consumption of entire circuit 30.This On/Off unit 34 is the runnings of opening or closing this main detecting unit 31 in order to control, saves the power consumption of entire circuit 30 to cooperate this latch lock unit 33.This speed lift unit 35 is in order to should main detecting unit 31 and to make entire circuit 30 fast obtain this testing result DR in this testing result DR fast transition to should second state time to this second state from this first state.This delay cell 36 has one first and one second delay circuit, in order to receive a detection signal, and export one first and one second inhibit signal respectively, wherein this first inhibit signal is to open this main detecting unit 31 in order to control this On/Off unit 34 when this detection signal is initial, and control this latch lock unit 33 when this main detecting unit 31 enters this second state to this testing result DR breech lock in addition, this second inhibit signal is in order to the unlatching of controlling this speed lift unit 35 and closes, as previously mentioned.
Fig. 4 is of the present invention one synoptic diagram with storage unit detecting circuit preferred embodiment of power saving and speed promotion capability.As shown in the figure, this circuit 40 comprises first and second transistor M1, M2 (being above-mentioned main detecting unit), a phase inverter (being above-mentioned digital unit) INV, a latch circuit (being above-mentioned latch lock unit) Latch, one or non-(NOR) logic gate (being above-mentioned On/Off unit) NOR, one the 3rd MOS transistor M3 (being above-mentioned speed lift unit) and a delay circuit (being above-mentioned delay cell) DCKT.
This first MOS transistor M1 can be a PMOS transistor or a nmos pass transistor, its source electrode or drain electrode receive a direct current voltage VDD, its grid is connected to ground, but itself thinks still that PMOS transistor (as shown in FIG.) is for preferable, because of the voltage that it provided can not lack a critical voltage Vt.Transistor seconds M2 is a nmos pass transistor, and connect drain electrode or the source electrode of the first MOS transistor M1 with its drain electrode, its source electrode or drain electrode are connected to the row position storage unit M4 of preamble via a Node B, this row position storage unit M4 joins with row position storage unit M5 again, and this row position storage unit M5 then is connected to ground again.
This phase inverter INV and this first and second transistor M1, the node A between M2 joins, and wherein on this node A an anti-phase testing result is arranged, and this anti-phase testing result is sent to phase inverter INV to obtain a testing result DR.Then, this testing result DR is sent to this latch circuit Latch, so as to utilizing the breech lock mode to export this testing result DR in an opportune moment (seeing also the explanation of following cooperation Fig. 5).The output terminal of this NOR-logic door NOR and the grid of the second MOS transistor M2 join, and the source electrode of the one input end and the second MOS transistor M2 joins.The 3rd transistor M3 can be a PMOS transistor or a nmos pass transistor, but still think that the PMOS transistor is for better, its drain electrode (or source electrode) is joined with this node A, when being " 0 " the second MOS transistor M2 and a row position storage unit M4 are charged so as to data among the storage unit M5 that is expert at, make node A can reach a high levels state fast so that really survey action when carrying out, even testing result DR obtains fast in reality.
This delay circuit DCKT produces two pulse wave inhibit signals in order to the detection signal DOCLK according to a pulse wave form, so as to controlling the running of above-mentioned latch circuit Latch, NOR-logic door NOR and the 3rd transistor M3 respectively.Specifically, one external circuit produces this detection signal DOCLK, adjacent rising edge and the falling edge of this detection signal DCOLK constitute a sense cycle, and described rising edge and falling edge can be utilized with this two pulse waves inhibit signal of triggering for generating, be connected to this latch circuit and NOR-logic door NOR and the 3rd transistor M3 (as shown in Figure 4) respectively, so as to reaching above-mentioned to latch circuit Latch, the control function of NOR-logic door NOR and the 3rd transistor M3 running, and then reach the power saving of whole memory unit testing circuit and speed promotes effect, it illustrates further and will cooperate Fig. 5 to carry out.In fact, this inhibit signal DOCLK also can be one and produces in order to the selection signal CE that selects this note to translate born of the same parents' testing circuit.
Fig. 5 A and Fig. 5 B are depicted as the coherent signal oscillogram of the delay circuit of storage unit detecting circuit of the present invention.Please consult Fig. 4, Fig. 5 A and Fig. 5 B simultaneously, this detection signal DOCLK represents when a rising edge occurring that desire detects testing result DR, this moment triggering for generating one first pulse wave inhibit signal PULSE1 falling edge, so as to opening this transistor seconds M2 via aforementioned NOR-logic door NOR, and making first and second transistor M1, M2 is operated and this row position storage unit M5 is detected.Back a period of time appears in the rising edge for the treatment of the first pulse wave inhibit signal PULSE1, this detection signal triggers this second pulse wave inhibit signal PULSE2 and produces a rising edge, so as to closing the 3rd MOS transistor, make it to stop the 3rd transistor M3 and row position storage unit M4 are carried out preliminary filling, to save the power consumption of entire circuit.When testing result DR is obtained, this first pulse wave inhibit signal PULSE1 the falling edge triggering for generating of the detected signal DOCLK of rising edge, in order to in addition breech lock output of this testing result DR, and the output of NOR-logic door NOR reduced to low level, with breech lock this testing result DR and close transistor seconds M2, so as to reducing the power consumption (shown in Fig. 5 A) of entire circuit 40.If when the rising edge of this first pulse wave inhibit signal PULSE1 occurred early than the falling edge of detection signal DOCLK, it was to produce (shown in Fig. 5 B) voluntarily by delay circuit DCKT.In addition, the falling edge of the falling edge of detection signal DOCLK and the triggering for generating second pulse wave signal PULSE2, to utilize the 3rd transistor M3 to advance preliminary filling, so that transistor seconds M2 and row position storage unit M4 are charged to a certain bits standard in advance when carrying out next sense cycle, and be charged to this second state that reaches rapidly when making data at row positions storage unit M4 for " 0 ", testing result " 0 " can be obtained fast.
Figure 6 shows that a circuit embodiments synoptic diagram that produces Fig. 5 A and Fig. 5 B coherent signal waveform.Please consult Fig. 4 and shown in Figure 6 simultaneously, this circuit selection signal CE and this detection signal DOCLK detect required person for carrying out this row position storage unit M5, and all be to provide by outside institute, this moment, the testing result DR that must meet storage unit detecting circuit that provides of this detection signal DOCLK exported the cycle.In addition, detection signal DOCLK also can and produce by a plurality of logic gate receiving circuits selection signal CE.Aforementioned delay circuit comprises one first delay circuit DCKT1 and first a plurality of logic gates (circuit one indication among the figure), one second delay circuit DCKT2 and second a plurality of logic gates (circuit two indications among the figure), reaches the 3rd a plurality of logic gates (all the other logic gate indications among the figure).When circuit selection signal CE and detection signal DOCLK are received, first and second delay circuit DCKT1, DCKT2 and this first and second a plurality of logic gates cooperate the 3rd outside a plurality of logic gates will change this first and second pulse wave inhibit signal PULSE1 into, PULSE2, so this latch circuit Latch, the 3rd transistor M3 and NOR-logic door NOR are controlled, also therefore the purpose of power saving and speed lifting is able to be reached.Yet the logic gate that delay circuit cooperated shown in Figure 6 only is an example wherein, and any other can cooperate the logic gate design of reaching this purpose all applicable.In the present invention, this first pulse wave inhibit signal is to be carried out and to postpone to name because of its low level place time partly, and the time that this second pulse wave inhibit signal then partly occurs because of its high levels is delayed to be named.
See also Fig. 7, it is the process flow diagram of method of the power consumption of saving storage unit detecting circuit of the present invention.As shown in the figure, this method comprises the following step: open this storage unit detecting circuit (S71).Treat that this storage unit detecting circuit is unlocked schedule time and after obtaining a testing result this testing result of breech lock (S72).At last, close this storage unit detecting circuit (S73).
See also Fig. 8, it is the process flow diagram of method of the detection speed of lifting storage unit detecting circuit of the present invention.As shown in the figure, this method comprises the following step: promote this storage unit detecting circuit from one first state to a particular state, more to be bordering on one second state (S81), wherein this first state is meant that this storage unit detecting circuit exports one first state as a result the time, and this second state is meant that this storage unit detecting circuit exports one second state as a result the time.Then, when treating that this second result is obtained, stop the carrying out (S82) of this lifting step.
By to enforcement of the present invention, the operation of storage unit detecting circuit can save energy and fast speed under finish.
The present invention must can also make all change that is equal to or replacement by the skilled personnel, yet neither disengaging is as the desire protection of additional copy application right claimed range institute.For example, the definition of data can be opposite in the storage unit of the present invention, and the phase inverter number in the digital unit can change at this moment.In addition, the high low level of first and second pulse wave inhibit signal (rising edge and falling edge) can be designed arbitrarily, and this moment is as long as cooperated change to described logic gate and described MOS transistor.In addition, the NOR-logic door of On/Off unit can also replace by other Different Logic door, as long as can reach identical function.In addition, above-mentioned speed promotes and relevant first and second pulse wave inhibit signal of the function of saving energy can independently provide and only has wherein a kind of function.
Claims (11)
1. storage unit detecting circuit comprises:
One main detecting unit is connected in series in regular turn with a chosen particular column position storage unit and a particular row position storage unit, has one first state and one second state are arranged, and export an anti-phase testing result of this storage unit when this first and second state;
One digital unit is in order to anti-phase in addition and obtain the testing result of a digital form to this anti-phase testing result;
One latch lock unit is in order to this testing result breech lock in addition;
One On/Off unit is in order to control the running of opening or closing this main detecting unit;
One delay cell, have one first delay circuit is arranged, in order to receive a detection signal, and export one first according to this detection signal and postpone pulse wave signal, when this detection signal is initial, make this main detecting unit of unlatching to control this On/Off unit, and control this latch lock unit this testing result of breech lock when this main detecting unit reaches this second state.
2. storage unit detecting circuit as claimed in claim 1, it is characterized in that: also comprise a speed lift unit, and this delay cell also comprises one second delay circuit and postpones pulse wave signal to receive and to export one second according to this detection signal, in order to be controlled at initial preceding this speed lift unit of opening of this detection signal, so that this main detecting unit reaches this second state fast by this first state after this On/Off unit is unlocked, and be controlled at and close this speed lift unit after this main detecting unit reaches this second state.
3. storage unit detecting circuit as claimed in claim 2 is characterized in that:
When this detection signal finishes, if this first delay pulse wave signal is still when this main detecting unit of control is unlatching, this first postpones pulse wave signal and is triggered by accurate transition edge of this detection signal and the accurate transition edge of another one respectively to carry out to the unlatching of this On/Off unit and to the control to the breech lock of this testing result of this latch lock unit, and this second delay pulse wave signal is triggered by this accurate transition edge of this detection signal and the accurate transition edge of this another one respectively to carry out for closing and opening of this speed lift unit;
Before finishing early than this detection signal, this first delay pulse wave signal closes this latch lock unit, then this first postpones pulse wave signal to the closing and the control of turning of this latch lock unit is triggered by accurate transition edge of this detection signal and the accurate transition edge of another one respectively to carry out of this On/Off unit, and this second delay pulse wave signal is triggered by this accurate transition edge of this detection signal and the accurate transition edge of this another one respectively to carry out for closing and opening of this speed lift unit; And/or
This detection signal is to select signal to be produced through at least one logic gate by a storage unit detecting circuit.
4. storage unit detecting circuit as claimed in claim 2 is characterized in that this detection pulse wave signal is that an external circuit provides, wherein:
This main detecting unit comprises:
One first MOS transistor, be one of PMOS transistor and nmos pass transistor, comprise a drain electrode, a grid and one source pole, and for this PMOS transistor the time, receive a direct current voltage with this source electrode, and receive this DC voltage with this drain electrode when being this nmos pass transistor, this grid is connected to ground; And
One second MOS transistor is a nmos pass transistor, and having has a drain electrode, a grid and one source pole, and the drain electrode when being the PMOS transistor with this drain electrode and this preliminary filling transistor is electrically connected, and the source electrode when being nmos pass transistor with this preliminary filling transistor is electrically connected;
This digital unit is a phase inverter, have an input end and an output terminal are arranged, this input end and this first transistor are electrically connected for the PMOS transistor drain, and with this first transistor be that the source electrode of nmos pass transistor is electrically connected, to export a testing result at this output terminal;
This latch lock unit is a latch circuit, is electrically connected with the output terminal of this phase inverter, with to this testing result breech lock in addition;
This On/Off unit is a NOR-logic door, has two input ends and an output terminal are arranged, and this two input end receives this first inhibit signal respectively and is electrically connected to the source electrode of this second MOS transistor;
This first delay circuit and this second delay circuit respectively are to constitute with a plurality of logic gates; And
This speed lift unit is one the 3rd MOS transistor, be one of PMOS transistor and nmos pass transistor, have a drain electrode, a grid and one source pole are arranged, for this PMOS transistor the time, receive this DC voltage with this source electrode, be electrically connected to the drain electrode of this second MOS transistor with this drain electrode, and when being this nmos pass transistor, receive this DC voltage, be electrically connected to the drain electrode of this second MOS transistor with this source electrode with this drain electrode, and receive this with this grid and second postpone pulse wave signal
Wherein the 3rd MOS transistor is when receiving to such an extent that also opened by this second delay pulse wave signal, to this second MOS transistor and this particular column position storage unit preliminary filling in addition, so that this second MOS transistor and this particular column position storage unit is subjected to precharge when this main detecting unit is in this first state and make this main detecting unit be in this second state.
5. storage unit detecting circuit comprises:
One main detecting unit is connected in series in regular turn with a chosen particular column position storage unit and a particular row position storage unit, has one first state and one second state are arranged, and export an anti-phase testing result of this storage unit when this first and second state;
One digital unit is in order to anti-phase in addition and obtain the testing result of a digital form to this anti-phase testing result;
One On/Off unit is in order to control the running of opening or closing this main detecting unit;
One speed lift unit, be predetermined to be an opening, so that this main detecting unit reaches this second state fast by this first state after this On/Off unit is unlocked, this speed lift unit also is unlocked after this main detecting unit reaches this second state once again;
One delay cell, comprise one first delay circuit, in order to receive a detection signal, and export one first according to this detection signal and postpone pulse wave signal, close this speed lift unit in order to be controlled at this detection signal after the initial schedule time, and be controlled at and open this speed lift unit when this main detecting unit reaches this second state.
6. storage unit detecting circuit as claimed in claim 5, it is characterized in that also comprising a latch lock unit, and this delay cell also comprises one second and postpones pulse wave signal, when this detection signal is initial, make this main detecting unit of unlatching in order to control this On/Off unit, and control this latch lock unit this testing result of breech lock when this main detecting unit reaches this second state.
7. storage unit detecting circuit as claimed in claim 6 is characterized in that:
When this detection signal finishes, if this first delay pulse wave signal is still when this main detecting unit of control is unlatching, this first postpones pulse wave signal and is triggered by accurate transition edge of this detection signal and the accurate transition edge of another one respectively to carry out to the unlatching of this On/Off unit and to the control to the breech lock of this testing result of this latch lock unit, and this second delay pulse wave signal is triggered by this accurate transition edge of this detection signal and the accurate transition edge of this another one respectively to carry out for closing and opening of this speed lift unit;
Before finishing early than this detection signal, this first delay pulse wave signal closes this latch lock unit, then this first postpones pulse wave signal to the closing and the control of turning of this latch lock unit is triggered by accurate transition edge of this detection signal and the accurate transition edge of another one respectively to carry out of this On/Off unit, and this second delay pulse wave signal is triggered by this accurate transition edge of this detection signal and the accurate transition edge of this another one respectively to carry out for closing and opening of this speed lift unit;
This detection signal is to select signal to be produced through at least one logic gate by a storage unit detecting circuit; And/or
This detection pulse wave signal is that an external circuit provides.
8. method of saving the power consumption of storage unit detecting circuit comprises the following step:
Open this storage unit detecting circuit;
Treat that this storage unit detecting circuit is unlocked schedule time and after obtaining a testing result this testing result of breech lock; And
Close this storage unit detecting circuit.
9. the method for the power consumption of saving storage unit detecting circuit as claimed in claim 8 is characterized in that:
This storage unit detecting circuit before opening this storage unit detecting circuit step, this also comprises the step of selecting this storage unit detecting circuit, so that can detect to this testing result when this unlatching step is carried out;
This unlatching and to close step be to carry out with control signal control;
This method also comprises a step that a detection signal is provided, so as to this control signal of triggering for generating;
This detection signal and control signal respectively are a pulse wave signal; And
This detection signal and control signal respectively have a rising edge and a falling edge, wherein:
The rising edge of this detection signal and falling edge trigger the generation of the falling edge and the rising edge of this control signal respectively, so as to opening this storage unit detecting circuit respectively and closing this storage unit detecting circuit and this testing result of breech lock; Or
This control signal is to be produced by a control circuit, the falling edge of this control signal of rising edge triggering for generating of this detection signal wherein, this control circuit produces the falling edge of this control signal, so as to opening this storage unit detecting circuit respectively and closing this storage unit detecting circuit and this testing result of breech lock.
10. method that promotes the detection speed of storage unit detecting circuit comprises the following step:
Promote this storage unit detecting circuit from one first state to, second state, wherein this first state is meant that this storage unit detecting circuit exports one first state as a result the time, and this second state is meant that this storage unit detecting circuit exports one second state as a result the time; And
When treating that this second result is obtained, the carrying out that stops this lifting step.
11. the method for the detection speed of lifting storage unit detecting circuit as claimed in claim 10 is characterized in that:
This storage unit detecting circuit before opening this storage unit detecting circuit step, this also comprises the step that this storage unit detecting circuit of selection is provided, so that can detect to this testing result when this unlatching step is carried out;
This unlatching and to close step be to carry out with control signal control;
This method also comprises a step that a detection signal is provided, so as to this control signal of triggering for generating;
This detection signal and control signal respectively are a pulse wave signal; And
This detection signal and control signal respectively have a rising edge and a falling edge, the rising edge of this detection signal and falling edge trigger the generation of the rising edge and the falling edge of this control signal respectively, close this speed lift unit and are controlled at this speed lift unit of the obtained back unlatching of this testing result after being controlled at a schedule time respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100819437A CN100538888C (en) | 2006-05-11 | 2006-05-11 | Storage unit detecting circuit and method thereof with power saving and speed promotion capability |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100819437A CN100538888C (en) | 2006-05-11 | 2006-05-11 | Storage unit detecting circuit and method thereof with power saving and speed promotion capability |
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| Publication Number | Publication Date |
|---|---|
| CN101071632A true CN101071632A (en) | 2007-11-14 |
| CN100538888C CN100538888C (en) | 2009-09-09 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100819437A Expired - Fee Related CN100538888C (en) | 2006-05-11 | 2006-05-11 | Storage unit detecting circuit and method thereof with power saving and speed promotion capability |
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| Country | Link |
|---|---|
| CN (1) | CN100538888C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101814314A (en) * | 2009-02-23 | 2010-08-25 | 台湾积体电路制造股份有限公司 | Using possibility to write programmes to mram cell |
| CN101470652B (en) * | 2007-12-27 | 2010-12-15 | 英业达股份有限公司 | Warning method and system for no memory insertion |
-
2006
- 2006-05-11 CN CNB2006100819437A patent/CN100538888C/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101470652B (en) * | 2007-12-27 | 2010-12-15 | 英业达股份有限公司 | Warning method and system for no memory insertion |
| CN101814314A (en) * | 2009-02-23 | 2010-08-25 | 台湾积体电路制造股份有限公司 | Using possibility to write programmes to mram cell |
| US8451655B2 (en) | 2009-02-23 | 2013-05-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | MRAM cells and circuit for programming the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100538888C (en) | 2009-09-09 |
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