CN1010647B - High-speed digital loop transceiver - Google Patents

Abstract

Be used for the high-speed figure transmitter-receiver of Private Branch Exchange PBX PBX equipment, exchange speech by the general twisted-pair power cable electric wire with block form, data and control information are with the pulse inner control information communication of grouping alternate mark inversion code (AMI).It is synchronous that utilization obtains synchronous digital circuit achieve frame in first pulse from this machine high-frequency clock.In addition, a receiving unit uses threshold value to select circuit.It is minimum by the digital pre-compensating that provides in transmitting intersymbol interference effect to be reduced to.

Description

High-speed digital loop transceiver

The present invention relates to the digital telecommunication device, the digital telecommunication device that transmits with the megabit per second data rate ranges particularly, this device uses one several thousand feet long standard twisted-pair feeder telephone cable.The present invention mainly is the home loop that is used for the digital subscriber telephone system, can support to transmit speech, data and image.But, device of the present invention also can be used for data acquisition and digital control work.

In the past, the digital information transmission that frequency surpasses megabit per second generally is to finish with expensive cable line system, such as using coaxial cable, shielded twisted-pair cable and optical cable.In the past, these systems generally need complicated data recovery technique, comprise analog balanced and Phase synchronization.

This technology that everybody is familiar with can be used to the information exchange between the computer equipment, although expense is not a principal element, but, be necessary to provide a kind of price low also more reliable system simultaneously here, preferably use price not too expensive, through standard twisted-pair cable commonly used.For this purpose, a transceiver not only must satisfy economic index but also will be able to satisfy strict bit error rate standard, emission standard and cross-talk standard.

For phone and various types of digital communication equipment provide the requirement of interface to increase, these digital communication equipments comprise personal computer etc., before being connected on the twisted-pair cable of installing.Be used for realizing that a possible technology of shared speech and data communication is to use packet switching, comprise speech, numeral or control and signal message in its grouping information.For the purpose of effectively, packet switching communication must have very high speed to be enough to and can to transmit voice signal under the condition of minimum time-delay, so that engage in the dialogue communication.In a private branch exchange (PBX) equipment, the there requires to reduce number of lines as far as possible, preferably by transmitting same physical circuit power supply of data.This just requires numerical data is to exchange that (ac) form is carried out and not have direct current (dc) skew.Like this, transmitter can be connected with transfer medium with pulse converter with receiver, also must use data and coded system such as alternate mark inversion code (AMI) simultaneously.Alternate mark inversion (AMI) coded system is suitable for transformer coupled circuit, but alternate mark inversion code (AMI) system is not self synchronous, therefore loses easily synchronously.General solution is with modified alternate mark inversion code (AMI) system, and that is exactly to consider long arbitrarily null sequence, so, just has the time of any length between pulse.The improvement system has inserted the bipolar violation of having a mind in data flow.The check system of these systems generally is complicated and expensive.

Surpass the highfrequency transmission systems of working on the distance of hundreds of foot general adopt a kind of own coding system and employing have continuous frequency and (or) the phase-locked loop simultaneous techniques of Phase Tracking.The phase-locked loop simultaneous techniques need have a limited acquisition time when each frame begins, so that bandwidth suppresses and time-delay seriously hinders in having the high-speed equipment of Frequency Synchronization and uses.Usually need four-wire system to obtain the full duplex ability in addition, because in prior art systems, the speed of the turnover of circuit is slowed down by synchronizing relay.

The another one problem especially adopts the occasion that surpasses the long standard twisted-pair cable of hundreds of foot, and Here it is because the low pass filter effect that line itself causes.The transmission medium relevant with low-pass filter characteristic can cause distortion, and when data speed during near the bandwidth of transmission medium, this distortion meeting increases the interference of intersymbol.In the past, low-pass filter characteristic has been compensated with the receiving terminal of analog balanced at a channel, so that obtain the acceptable bit error rate.Analog balanced itself does not possess the integrated condition of numeral, thereby has reduced the benefit of gained from other circuit extensive integrated.In addition, the interference of intersymbol is also to being used for the requirement that the detection threshold of discriminate between logical value " 1 " and " 0 " produces mutual contradiction.Such as, be used for selecting the voltage threshold that pulse is arranged and do not have pulse separation to open lowly as much as possible, so that the influence of compensation intersymbol interference.If but handle is used for distinguishing pulse and does not have the threshold voltage of pulse to select lowly excessively, then the transmission back of a pulse does not and then have pulse, and this pulse may be detected improperly at receiving terminal is consecutive pulses.This misreading is owing to long the causing discharge time of the transmission medium that plays the low pass filter effect.Directly detection system is more complicated, is non-self-timing because there is not the DC component coded system as alternate mark inversion code (AMI).For synchronous purpose, in alternate mark inversion (AMI) coding, usually to comprise a clock signal.Regrettably this clock signal can produce an artificial DC component.

Such-and-such problem has put forward, and is resolved in the improvement that is suitable for the high-speed figure transmitter-receiver of transporting speech and data in a private branch exchange (PBX) equipment.

A kind of digital transmitting and receiving machine is used for exchanging speech and data by grouping rules in a private branch exchange (PBX) equipment.This private branch exchange (PBX) equipment comprises that twisted-pair cable connects similar transceiver and communicates with the speed of megabit per second, especially, each transceiver communicates with the grouping pulse code modulation information mode of pure alternate mark inversion (AMI) coding.Frame synchronization obtains by using an adjustable length Frequency Synchronization window, and this Frequency Synchronization window is obtained by the high-speed counter that a high-frequency clock drives synchronously.Just not needing synchronously to obtain a phase-locked loop synchro system and the limited phase detection time-delay of generation therefrom with a high-speed counter.In addition, the receiving unit of transmitter-receiver also uses a kind of device of selecting between a plurality of threshold values.Any expectation that does not have bipolar violation in the action response transmission signals of its exchange.The influence of intersymbol interference is further reduced to minimum by transmission signals is carried out digital precompensation, make the switching rate between the continuous position rise to the highest.The basis of precompensation circuit is the knowledge of energy size contained in bit figure and the bit sequence.

The present invention realizes the data set size and the DS1(T1 of this agreement in grouping full duplex two-wire speech that uses table tennis communication protocol and digital communication system) frame of pulse code modulation data communication is compatible mutually.Per 125 microseconds, 16 byte frames can be transmitted the maximum data rate of relative 1.024 megabit per seconds of this frame at most.Actual transfer rate on twisted-pair cable is 2 megabit per seconds, adapts to like this to realize the full duplex dual-wire communications on a twisted-pair cable.The full duplex ability is to transmit one group of data set in a frame in one direction, transmits in the opposite direction in next frame then that one group of data set realizes.Must change on each frame synchronously, be that per 125 microseconds are changed once synchronously in the specific embodiment in this manual.Use the frame synchronization clock of a high-speed counter can realize fast synchronously based on a kind of principle commonly used.

Detailed description by following connection with figures will make everybody further understand the present invention.

Fig. 1 is the block diagram of transmitter-receiver of the present invention.

Fig. 2 is the schematic diagram of receiver section of the present invention.

Fig. 3 is the schematic diagram that has the transmitter section of pre-compensating among the present invention.

Fig. 4 A is for sending the oscillogram of ripple among the present invention.

Fig. 4 B is for receiving the oscillogram of waveform with variable thresholding among the present invention.

Fig. 4 C represents the oscillogram of this data window signal for be considered to the valid period at data-signal.

Fig. 5 A is the oscillogram of expression data output waveform or synchronization bit signal.

Fig. 5 B is expression a part of oscillogram frame or FRM.

Fig. 5 C is a typical clock signal.

Fig. 5 D is an oscillogram with the typical data window signal of the waveform equivalence of Fig. 4 C.

Fig. 5 E is the oscillogram of a typical data output signal of representative.

Fig. 1 is the block diagram of the dual-purpose machine 10 of digital transmitting and receiving of the present invention. Its input comprises eight bit data line and three control lines, and they are connected to the end of one group of transmission register 12 equal number; This group emitter register 12 is connected to a parallel-to-serial converter 14, and the reception signal on all parallel data lines changes series form under clock control (clock is not expressed at this) there. A modulator and pre-compensating circuit 16 are sent in the output of parallel-to-serial converter 14. Modulator and pre-compensating circuit 16 executable operations change serial digital signal into digit pulse, according to the present invention with each pulse of enough power generations so that between continuous impulse, produce optimal conversion (will be described below). For those of ordinary skill, if provide the standard of the output characteristics of modulator, realize that the function of the modulator part of circuit 16 is apparent. It is under the control of sequence controller 18 that modulator/predistorter circuit 16 can be chosen as. Sequence controller 18 monitors that tablet pattern also will be about notifying modulator predistorter 16 by amplitude sum total representative, that be included the energy in each pulse.

The output of modulator/pre-compensating circuit 16 is sent to an output, and this output jumps on the balanced load that comprises resistance R 1 and R2 by a pulse transformer 20. Pulse becomes Depressor 20 comprises: one have terminal 131,133 and 134 with centre tapped primary coil 21, and a pair of secondary coil 23 and 25 with bias voltage, the negative pole that first secondary coil is connected to first lead 24 of a twisted-pair cable 22 and DC current DC bias voltage (for example, direct current-48V DC), second secondary coil is connected to second lead 26 of twisted-pair cable 22 and the zero volt end of dc source DC. It is in order to power to remote station by direct-coupling that direct current connects. Signal coupling between two secondary coils 23 of pulse transformer 20 and 25 is finished by a coupling capacitor 28. Therefore, this AC signal and dc power supply are realized completely uncoupling.

The chosen path of reception signal of sending into twisted-pair cable is sent into the tap 30 and 32 in the primary coil 21 of pulse transformer 20.

Twisted-pair cable 22 is connected to a far-end transmitter-receiver (not expressing at this).Because the receiving unit of transmitter-receiver 10 is same, so we only note the receiving unit 33 of transmitter-receiver 10.Passing threshold controller 36, but differential received unit 34 receive threshold signalizations.Threshold controller 36 can be a fixing voltage source, maybe can detect the voltage level on tap 30 and 32 and produce a reference voltage level on datum line 38.The voltage reference level of regulation preferably amplitude agile and based on the average power or the amplitude of the pulse between positive transition and the negative sense saltus step.Such threshold value setting is conventional.Because it and claim of the present invention have nothing to do, just do not describe in detail at this.Datum line 38 is connected to the benchmark input end 40 and 42 of receiver 34.Acceptor unit 34 produces the RI+ signal and produces the RI-signal at output 46 at output 44.Output 44 and 46 is connected to data and recovers and sync logic 48.Logical circuit 48 uses an internal clocking, perhaps import a high-frequency clock in addition, thereby its speed can drive internal clocking for fast six times than minimum bit rate at least, and this point will be explained hereinafter.Logical circuit 48 is also connected to sequence controller 18.The implementation of logical circuit 48 also will be explained hereinafter.

Data are recovered and the output of sync logic 48 is to represent from the coded data of alternate mark inversion code AMI and a serial mode of data recovered.Serial transducer 50 is sent in this output, by it then be connected to receiving register 52.Receiving register 52 has for example 8 bit data output lines, a frame synchronization line and a timer clock line, and this clock signal can be for further processing according to the packet format that is limited.The details of this packet format has not just been discussed at this, because the present invention only relates to the operation by the grouping environmental limitations, promptly needs the operation of the synchronous table tennis protocols limit of rapid and frequent acquisition.

In order to help to understand coding techniques and sign indicating number recovery technology, please refer to accompanying drawing 4A to 4C.Fig. 4 A is the oscillogram on the coordinate at one time to 4C, and they are represented transmitted waveform 200 respectively, receive waveform 300 and receive waveform data window wave shape 400 in order to detect.Below data window waveform 400 is a clock signal high speed, pinpoint accuracy, for example, and with the clock signal of six times of data window waveform 400 representative signal rates speed operations.A data window as window A, is started in the half period, and therefore, 6 variations of a such high-frequency clock on each data window produce three complete cycles.The number of times that each data window changes is represented phase-resolved degree, and this point hereinafter will be explained.

Alternate mark inversion (AMI) coding of Fig. 4 A explanation emission wherein, has pulse, counterlogic " 1 ", and do not have pulse, counterlogic " 0 ".According to pulse of the present invention is eternal alter polarity.According to the present invention, Alternate Mark Inversion encoding wherein must comprise all non-existent bipolar violations of having a mind to.

About Fig. 4 B, represented a representative that receives waveform 300 here, i.e. signal that is admitted to transmission medium is because the restriction of medium frequency bandwidth makes it be subjected to intersymbol interference.If the time interval of two adjacent pulses is shorter than the complete discharge time of sending into the emission media pulse, intersymbol interference will take place.Waveform shown in Fig. 4 B is the effect of the received pulse waveform on typical twisted-pair cable.Its data rate is greater than 0.5 megabit per second, and from the distance of the transmitter of transmitter-receiver greater than 200 meters.Clearly, receive waveform and can not be set to null value, this is because the time that two actual intersymbol intervals allow greater than two intersymbols, as by data window 400(Fig. 4 c) " height " or " permission " of each state A, B, C, D etc. (ENABLED) represented.

Therefore, according to the present invention, used the dual threshold system, the threshold value that wherein is used to distinguish pulse and do not have pulse is modified to the history and the transmitted waveform that receive according to signal and does not comprise bipolar violation knowledge.For example, in the beginning of accepting, when energy in certain received signal surpasses threshold value 310 or threshold value 320, will indicate to receive a pulse.In the example shown in the figure, under data window A condition, reach valve 310 for the first time.As below will explaining, circuit when next data window state, i.e. cutoff threshold 310 and keep threshold value 320 during data window state B.In data window state B, the pulse of an indication logical one value is detected.Threshold value 320 is mirror image or the complementary of threshold value 310 about dc dc reference value 330.

After a pulse was detected, the threshold value behind the data window state B was by anti-phase.Therefore, in data window state C, threshold value 310 is resumed, and indicates effective pulse must have the intersymbol interference of enough energy with previous symbol before overcoming.In data window state C, threshold value is provided with by anti-phase, since intersymbol interference, one zero pulse of pronouncing of reading in the quilt mistake.When pulse takes place once more above threshold value 310 (in data window state D), threshold value 310 is recovered threshold value 320 once more by anti-phase.Threshold value 310 is still worn-out by screen, and greater than threshold value 320, it takes place in the data window state I up to a negative-going pulse.Threshold value 310 is anti-phase once more, so that in data window state J, detects a pulse.Between this, threshold value is anti-phase once more so that avoid mistake to read in data window state K.

Referring to the oscillogram of Fig. 4 B and 4C, data window state A is synchronized to and occurs first surpassing on the waveform that is received of threshold value 310 or 320.Therefore, only after one occurs greater than threshold value 310 or greater than pulse in the threshold value 320, allow data mode A during predetermined at one.The timing relevant with data window state A and all each data windows subsequently equally are the high-speed clock signal decisions below it.Log-on data window state A during the transition next time of a signal high-speed clock signal in its lower section that surpasses threshold value 310 or threshold value 320.Therefore, the resolution of a data window relevant with the waveform of this reception is relevant with subsequently high-speed clock signal transition recently.Since with respect to data window begin two possible transition are arranged, may be synchronously with receive data pulse take place before or following closely threshold value synchronous.

High-frequency clock is preferably taken from a high-precision oscillator.Bit stream be the frame orientation synchronously.In the following specific embodiment of saying, per 125 microseconds produce synchronous acquisition.Synchronous acquisition according to the present invention begins to carry out in first pulse of back at each frame.If the time of at least 5 microseconds is arranged, intersymbol interference will not influence in pulse; Therefore, the forward position of first pulse is used to start first data window in pulse train.If operating in of this machine clock exceeds predetermined allowing outside the clock rate, only be a relevant problem synchronously after this.Furtherly, people will think better of, and only the sub-fraction of 125 seconds frame will be used to do transmission of Information.Therefore, on each node high precision oscillator is housed in system, the oscillator of operating under the frequency of same nominal can be as this machine control of data window.As long as the beginning of this machine clock and each frame is synchronous, then do not need general clock.As an example of desired drift value in the system of a reality, supposing has two oscillators, and one of them is on the switching node of center, and another is on the remote equipment of finish node.If each oscillator has 50(PPm) precision, then the image duration of 125 microseconds the maximum drift amount be 12.5 nanoseconds.This drift value is the permission limit of frame synchronization.In fact, accuracy is much higher, because only used the sub-fraction of 125 microsecond frames, and is following a free time synchronization acquistion and can not take place, up to carrying out actual transfer of data.

According to the present invention, use a shift register that links to each other with a high-resolution counter to finish synchronization acquistion.Conventional synchronous capture technology uses a kind of phase-locked loop of precision.The capture time of phase-locked loop is in fact long than the capture time among the present invention, and with the conventional getable precision of phase-locked loop systems, can be than the getable precision height of the present invention.

Referring to Fig. 2, it shows in order to overcome intersymbol interference and to obtain synchronous logical circuit.The output 44 and 46 of the comparator 34 among Fig. 1 is imported into data and recovers and synchronous logic 48(Fig. 2) in.A high-frequency clock 54 connects the input end of clock of first shift register 56 and second shift register 58.High-frequency clock 54 is preferably with the speed operation faster at least 6 times than the lowest order speed of wanting data recovered.Resemble above say drive high-frequency clocks 54 by a high precision oscillator 60.High-frequency clock 54 and high precision oscillator 60 needn't aim at the data recovery and sync logic 48 is equipped with, and it also can be needed other parts of digital dock to share in the transmitter-receiver simultaneously.Logical circuit 48 also comprises a bistable multivibrator or 62, one first on trigger and 64 and one second at door and door 66, and wherein each output corresponding and door 64 and 66 is connected to the data input pin of shift register 56 and 58.Each shift register 56 and 58 has two outputs: its first feedback output end is by corresponding inverter 68 and 70; In addition, the output 72 and 74 of synchronous output end is received one or 76.Or door 76 output is a sync bit signal, is sent to the input end of clock of trigger 78.

And the threshold value masking operation of logical circuit 48 among Fig. 2 is significantly for the person of ordinary skill of the art, and the explanation of its operation has enlightenment.Before the accepting state of logical circuit 48 begins, a frame signal FRM on the holding wire 90 is changed to logical zero by an asserts signal that is input to the set input of trigger 78, and the NAND gate 80 of this holding wire 90 and formation trigger 62 links to each other with an end of three inputs separately of 82.Therefore, two of trigger 62 outputs are set to logical one.Do the time spent with door 64 and 66 effectively at its input 44 or input 46, will produce an output.With the output state of door 64 and 66, under the control of high-frequency clock 54, be shifted continuously through shift register 56 and 58.When occurring greater than the signal by the set threshold value of threshold controller 36, the input 46 that is added with the input 44 of signal RI+ or has a signal RI-produces a logical one at the data input pin that connects serial-to-parallel shift register 56 or 58.Data will be shifted by the shift register that starts, up to being ended through the feedback output of inverter 68 or the feedback output of process inverter 70.This feedback output is represented by R2 and R1 respectively.The R2 signal is fed back to the R2 input of NAND gate 82.The R1 signal is fed back to the R1 input of NAND gate 80.According to the position in the shift register of confessing data at this, infeed a signal and after the fixing limited delay, produce above-mentioned these complement code signals through one at data input pin.

Send into and door 64 or 66 time when the signal that is transmitted by holding wire 44 or 46, corresponding signal is fed to the input of shift register 56 or 58, because the output of two NAND gate 80 and 82 is high level at first.Signal is transported to the output tap by shift register.For example, if signal RI+ allows a logical one is added on the data input pin of shift register 56, produce the input that signal R2 is added to NAND gate 82 by inverter 68.During beginning, because frame signal line 90 is to be in the logical zero value, this signal is effect not.Yet, the data-signal in the shift register 56 by or door 76 deliver to the input end of clock of trigger 78 and then deliver to output line 12.The data input pin of trigger 78 is predisposed to logical one (+5V voltage) at terminal Z place.Therefore, when logical one was sent into the input end of clock of trigger 78, the output on the main feed line 90 became logical one, was sent to the input of NAND gate 80 and 82 simultaneously.The firm logical one that becomes of frame signal FRM on the line 90, the output of NAND gate 80 becomes logical zero, thereby causes and door 64 input becomes logical zero.So according to the present invention, any signal on the input 44 can not enter shift register 56 with conductively-closed.The input signal that shift register 58 keeps response to provide by output 46 is as long as just maintain on the logical one because the output of NAND gate 82 has an input to remain logical value " 0 ".In this case, therefore the output of NAND gate 80 made the output of NAND gate 82 maintain on the logical one value by the end of cross-couplings to three inputs of NAND gate 82.After a predetermined period, when the logical zero of the data input pin of shift register 56 was sent through shift register, signal R2 replied and is the logical one state.Logical circuit 48 will be waited for the pulse that receives the next designation number " 1 " in the input 46.If do not receive pulse signal the period in the regulation of data window on the output 46, it is digital " 0 " that circuit is then deciphered this signal.Yet if there is a signal for numeral " 1 " to be added on the input 46, such signal is by delivering to shift register 58 with door 66, and this register back during presetting is showed logical zero at the R1 output then outputed to NAND gate 80.Then NAND gate 80 is forced the logical one state, and it again then force NAND gate 82 to be fallen for the signal shielding of logical zero state in order to the shift register 58 that will send into from input 46.In this method, the width of each pulse is not fixed against the developed width of the pulse on the transmission medium, is by the decision of the primary data pulse on the transmission medium with respect to the initial threshold polarity of a neutral benchmark.

With reference to figure 2, wherein show a data window circuit 92 of the present invention again.Data window circuit 92 comprises a serial-to-parallel shift register 94, is connected on the clock adapter circuit 96.The purpose of clock adapter circuit 96 is to provide a clock signal at the rising edge and the trailing edge of each output pulse of high-frequency clock 54, the polarity of this clock signal with inceptive impulse and the polarity of the signal pulse that all continues consistent.

Shift register 94 is connected to the frame signal FRM on its CLEAR input reception line 90, and receives the clock signal C LOCK of self-clock adapter circuit 96.In a specific embodiment, the 3rd output tap of shift register 94 is fed the input endpoint 100 that is input to shift register 94 by an inverter 98.The output of this shift register is a data window signal on online 102, and receives on the NAND gate 104 with two inputs.NAND gate 104 its another input accept from or the sync bit signal of door 76.The output of NAND gate 104 is at a valid data window state required data output signal (as Fig. 5 E) of (as Fig. 5 D) between the emergence period.Particularly about having represented an example with shift register 94 related timing sequences among Fig. 5 A, 5B, 5C, 5D and the 5E.Fig. 5 A represented by or a sync bit signal providing of door 76 output.At the trailing edge of sync bit signal, (Fig. 5 B) produces a frame signal on the line 90.The removing input (Fig. 2) that this frame signal is sent to shift register 94 is removed the whole remaining datas in the shift register 94.Signal that comes self-clock adapter 96 to produce on online 106 is in order to drive shift register 94.In a preferred embodiment, the clock pulse of a forward rising edge of these shift register 94 responses.After predetermined several clock cycle (in this specific embodiment, be three cycles after), deliver to output signal on the line 102 by shift register 94.This is a data window signal that outputs to NAND gate 104 and inverter 98.The output of inverter 98 is fed back to the output 100 of shift register 94.With reference to Fig. 5 D, the data window signal response is activated (Fig. 5 C) and is cut off in response to the forward rising edge that comes next of clock signal in the positive rising edge of clock signal.The AND operation of the data-signal of (shown in Fig. 5 A) and data window signal (shown in Fig. 5 B) produces an indication (being designated as a numeral " 1 ") that occurs pulse in received signal, the indication (being designated as a digital " 0 ") that perhaps produces a no pulse on synchronous bit line.

Further explain clock adapter 96, there is shown first trigger 108 and second trigger 110, they have output and connect respectively and door 112 and 114, should be connected to one or 116 with door output, should or door on clock line 106, produce an output signal.Trigger 108 and trigger 110 are driven by high-frequency clock 54, and wherein making two triggers with an inverter 118 is anti-phase relation.High-frequency clock 54 is also by second input of anti-phase driving with door 114.Its noninverting clock signal drives second input with door 112.Each data input pin of trigger 108 and trigger 110 be through or door 76 sync bit signal.The complementary output of trigger 108 and trigger 110 is by difference cross-couplings clear " 0 " CLEAR input to another trigger 110 and trigger 108.Therefore a rising edge clock output signal is exported in the cooperation of foregoing circuit element, and with the first homophase of each frame data and synchronously.

Fig. 3 is the schematic diagram of pre-compensating circuit 120 of the present invention, and this circuit is used to provide the transmission pre-compensating, can be used in the modulator predistorter 16 among Fig. 1.We are only interested in pre-compensating circuit 120 at this, and other wherein used circuit has been general, just do not need to describe in detail for medium technical staff.The pre-compensating circuit 120 that constitutes according to the present invention is the purposes for transmission pulse, in this mode, for example at the receiving terminal of the transmission medium of a twisted-pair cable, makes its data recover to go up the intersymbol interference effect and produces minimum influence.Pre-compensating is to carry out in one one mode, makes intersymbol switching rate maximum (consider preceding two transmission position), and provides a pre-compensating signal to next subsequent bit (according to front two bit code shapes).Particularly with reference to each element among Fig. 3, data be from string-and shift register 122 previous stage receive, the output of its register is connected to the input (MSB) of the highest significant position address of a programmable read only memory PROM124 concurrently.Export a least significant bit address (LSB) via the counter that this machine high frequency clock 154 drives.This machine high frequency clock 154 is preferably used the same clock in the receiver, and the output of programmable read only memory PROM124 preferably has at least three data bit lines to be connected to shift register 126.This data output provides the selection of 8 dynamic levels that can limit, and the width that is used for subsequent treatment.Particularly register 126 is the shift registers as latch operation, data from programmable read only memory PROM124 are adorned wherein, its each output is connected to and drives loading resistor 128, offers shown in pulse transformer 20(Fig. 1) pulse.(pulse transformer among Fig. 3 is not the part of predistorter circuit 16 just to being convenient to understanding).

In a specific embodiment, register 126 has four outputs, and each is exported all through a resistor R 3, R4, R5, R6, and an end of each resistor all is connected to an end or the other end of the elementary input of pulse transformer.Particularly first output resistor R3 is connected across between first input 21 and register 126 first outputs 130 of pulse transformer 20 primary coils.Second output resistor R4 is connected across between the input 21 and the second register output 132 of primary coil.The 3rd output resistor R5 is connected across between the 3rd output 136 of the input of pulse transformer 20 or tap 134 and register 126.The 4th output resistor R6 is connected across between the 4th output 138 of the tap 134 of pulse transformer 20 and register 126.Resistor R 3 preferably and resistor R 5 be same value; Resistor R 4 preferably and resistor R 6 be same value so that keep the balance between pulse transformer 20 primary coils jointly.

The operating process of pre-compensating circuit 120 is as follows:

In the beginning of one-period, one two megahertz or other data high-speed clock pulse is removed counter 125, is " 0 " count status, and the shift register 122 of beginning enable clock pulse input serial-to-parallel.154 pairs of counters 125 of a high frequency clock are with than the speed of high several times of the input clock of two megahertzes regularly, and this two mhz frequency makes least significant bit (LSB) address in the read-only memory 124 come the data of relevant pulse of access and width size.

Be input to shift register 122 with a suitable continuous clock pulse with two megahertzes, the data that are input to shift register 122 are sent to highest significant position (MSB) address of read-only memory 124.Continuous clock will be by shift register 122 mobile datas, therefore make highest significant position (MSB) graphic change of address part in the read-only memory 124.So, the data of input are used to the different zone of selected read-only memory 124, make it come access data according to the counting sequence that counter 125 produces, data in the read-only memory 124 in each section are that they will be provided for the transmitter output network for regularly previously selected with the amplitude characteristic of the compensation effect of wanting.For example, one or more sections may contain the sky data, and other section may contain data to represent concrete length and pulse amplitude in conjunction with (pulse shape).Section carries out addressing based on the combination of the historical bit of the existing and tight front of the data input pin that offers shift register 122, for example, for for input data of three continuous " 1 " representatives, to go the data segments of addressing to carry out addressing to each lowest order of permission, this data represented a kind of high-amplitude datagraphic of short pulse relatively that has.Each signal is delivered on resistance R 3, R4, R5 and the R6, to be combined into the amplitude peak of regulation.Pulse will be terminated by the empty data on the lowest address unit in the section of address.Send an analog signal according to the time of the non-NULL figure place that comprises in the section of address.

Be based on the datagraphic of wanting to increase switching rate according to pre-compensating method of the present invention, this increase is by previously existing pulse to increase amplitude peak and make pulse length reduce to minimum in the past to obtain based on being right after.Carried out a kind of logic decision of three level.

Figure according to a particular embodiment of the invention is as follows:

If current transmission position is " 1 " (pulse is arranged), and be right after two of fronts and be " 0 " (not having pulse), the pulse that produces with the read-only memory data is to have a long low amplitude figure of holding time, if current transmission position is " 1 ", first position that is right after the front is " 1 ", and second position that is right after the front be for " 0 ", and what then produced by the read-only memory stored data bit is the figure with medium pulse length moderate range.If current transmission position be " 1 ", and the position that or all are right after the front is " 1 ", and what the read-only memory stored data bit produced is high-amplitude pulse pattern of weak point.If present bit is " 1 ", the position that is right after the front is for " 0 ", and second position that is right after the front be " 1 ", and data bit represents to have the amplitude pulses of intermediate length.Its purpose is to provide identical gross energy in each pulse.

The present invention has explained in conjunction with each specific embodiment.Other embodiment will be fairly obvious concerning one of ordinary skill in the art.So, the present invention is not added restriction in addition except described in the appended claims.

Claims (8)

1, one is transmitted on twisted-pair feeder telephone cable transmission medium and the equipment of receiving digital data comprises:

Be used for from digital information signal, producing and transmitting the device of AMI signal; And

Be used to receive and detect the device of AMI signal, this checkout gear can be used for recovering above-mentioned digital information, and this checkout gear comprises the device that limits two detection thresholds, it is characterized in that, described generation and conveyer comprise:

Be used for producing and transmit the device that pure mark replaces reversed polarity sign indicating number (pure AMIPC) signal from digital information signal, described pure AMIPC signal do not contain bipolar violation and

Be used to receive the device of the signal of representing described pure AMIPC signal, described receiving system comprises:

Limit the device of the first threshold and second threshold value, described first threshold is used to discern the positive pulse of described pure AMIPC signal, described second threshold value is used to discern the negative pulse of described pure AMIPC signal, and the amplitude of the described first threshold and second threshold value is equal substantially;

First checkout gear is connected to described threshold value device for limiting, only is used for the signal of detected amplitude greater than described first threshold;

Second checkout gear is connected to above-mentioned threshold value device for limiting, only is used for the signal of detected amplitude greater than described second threshold value;

Be used for side by side starting the device of described first and second checkout gears till first representation signal that receives any polarity, described starting drive also is used for starting described first checkout gear till the representation signal that receives negative polarity according to the representation signal that receives positive polarity, and yet is used for starting described second checkout gear till the representation signal that receives positive polarity according to the representation signal that receives negative polarity; With

Timing device is used to set up the pulse duration of the reconstruction pulse of each described positive and negative polarity representation signal, and the width of described pulse duration and described representation signal is irrelevant, thereby makes the effect of inter-symbol minimum.

2, according to the equipment of claim 1, it is characterized in that, described generation and conveyer comprise and being used for according to the digital numerical value of information signal the preceding, the mark that digital ground pre-compensating is produced replaces the amplitude and the width of reversed polarity coded signal, thereby makes the intersymbol interference of received signal be minimum device.

According to the equipment of claim 2, it is characterized in that 3, described pre-compensation means comprises amplitude and the width that can select respectively to be transmitted pulse signal, thereby be maximum device keeping the approximately equalised conversion rates that makes simultaneously of each pulse energy.

According to the equipment of claim 2, it is characterized in that 4, described digital pre-compensation means comprises:

A shift register is used for accepting above-mentioned information signal;

A programmable read-only memory, by connecting, the output of going to receive this shift register is as the highest significant position address, so that select the section in the above-mentioned storage arrangement;

A digit counter is connected to the least significant bit address of above-mentioned memory, is used for producing an address sequence so that the data of reading in the section of being selected by information signal are supplied with above-mentioned shift register; And

A device that is used for the above-mentioned data transaction in the section of above-mentioned storage arrangement is become the analog signal that its amplitude and width determined by above-mentioned data.

5, according to the equipment of claim 1, it is characterized in that, above-mentioned reception and checkout gear comprise a digital device, be used for catching to the data window of every first pulse of the above-mentioned pulse signal that received synchronous, the pulse signal of above-mentioned reception is in the packet format of a finite width, above-mentioned synchronization acquiring device comprises this machine high precision clock, is used for keeping synchronously at above-mentioned finite width.

6, according to the equipment of claim 5, it is characterized in that, comprise that also is used for a device of selecting between first detection threshold and second detection threshold, first detection threshold is for first polarity pulse signal, and second detection threshold be for the pulse signal of first opposite polarity second polarity, the effect of this choice device is based on first the polarity in the above-mentioned pulse signal that is received.

7, equipment according to claim 1, it is characterized in that, also comprise a device, be used for the device between first detection threshold and second detection threshold, selected, first detection threshold is the pulse signal for first polarity, and second detection threshold be for the pulse signal of first opposite polarity second polarity, this choice device comprises a device, be used for every first polarity in the pulse signal that sensing accepts, and respond the polarity of institute's sensing and shield the next pulse signal of accepting same polarity, till an opposite polarity pulse signal is sensed.

8, according to the equipment of claim 7, it is characterized in that, also comprise first a polarity in response to the above-mentioned pulse signal that receives, thus the device of this machine of selection high-frequency clock polarity.

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