CN101055556A - Multiple CPU system and method for passing information between CPU - Google Patents
Multiple CPU system and method for passing information between CPU Download PDFInfo
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- CN101055556A CN101055556A CN 200610072755 CN200610072755A CN101055556A CN 101055556 A CN101055556 A CN 101055556A CN 200610072755 CN200610072755 CN 200610072755 CN 200610072755 A CN200610072755 A CN 200610072755A CN 101055556 A CN101055556 A CN 101055556A
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Abstract
The invention discloses a multi-CPU system, including: the whole system comprising a plurality of independent CPUs, a message-switching unit and a timing message transmitting unit. The CPUs are communicated with each other only via an exchange unit; the exchange unit is connected with each CPU by FIFO or a serial interface at high speed; the information is transmitted via message between CPU and the exchange unit; the exchange unit is cooperated with the timing message transmitting unit to monitor each state of CPU in the system in order that the abnormal is discovered in time and the normal operation is recovered.
Description
Technical field
The present invention relates to many CPU field of computer, in a kind of many CPU computer system, method for communicating between the composition structure of system and each CPU.
Background technology
Along with development of computer, and people are to the improving constantly of Computing Capability Requirement, descending of hardware cost in addition, and the computer system of many CPU is arisen at the historic moment.Many CPU computer system refers to a group separate processor, and each processor has programmable counter, program and the instruction of oneself.
Have a lot of sorting techniques to divide now, many CPU computer system is divided into two kinds here: one group has shared drive and is commonly referred to multiple processor system, and multiple processor system is applicable to parallel system, is generally used for solving same problem.One group of many CPU department of computer science that does not have shared drive is referred to as multicomputer system.And multicomputer system trends towards solving a plurality of problems, has various contacts certainly between each problem.
In multiple processor system, system resource is shared by all CPU in the system, and operating load is assigned on all available processors; Computing machine is simultaneously by the single duplicate of a plurality of processor operation system, and other resources of a shared drive and a computing machine.Though use a plurality of CPU simultaneously, from the angle of management, their performance is just as having only a CPU.System is distributed in task queue on a plurality of CPU, thereby has improved the data-handling capacity of total system widely.All processors can be according to certain strategy access memory, I/O and external interrupt.
A plurality of CPU shared drives in the existing multiple processor system are finished the work according to different demands is collaborative.The mode of shared drive is also adopted in communication between each CPU usually.A solution is, in the space that each CPU can both have access to, set up two formations, adopt reception pointer and send these two pointers of pointer to come formation is managed, reception pointer points to the current buffer zone address that is reading, send pointed and deposit the buffer zone address of next data to be sent, each formation is made up of the buffer zone of a plurality of fixed sizes, each buffer zone is deposited a needs data packets for transmission, the packet that certain CPU issues another CPU is deposited in formation, and the CPU of reception packet can read this packet.Fig. 1 is the synoptic diagram that communicates by shared drive according to each CPU in the existing multicomputer system (shared drive).In this system, a plurality of CPU connect by bus or other modes.A typical bus has 32 address wires, 32 data lines, 20 to 32 control lines.During read-write operation, CPU delivers to the address that will visit on the address bus, sends signal then on the control corresponding line, indicates it and wants the action done, and internal memory is just delivered to this word on the data bus, and CPU just can read data.
In the multiple processor system of shared drive, because the processing speed of CPU is inequality, the consistance of internal memory is a content of always studying.And the mechanism of shared drive can cause many safety problems, can be by the malice read-write of internal memory being influenced other CPU such as a CPU.
Another kind of in the multi-CPU system---each CPU has the internal memory that exclusively enjoys of self in the multicomputer system, and it can not directly visit the storer of other CPU.Fig. 2 according to each CPU in the existing multicomputer system (exclusively enjoying internal memory) by connecting the synoptic diagram that communicates at a slow speed.The communication of this system is between CPU and CPU, so the traffic is lacked several magnitude than CPU to the traffic between the internal memory.Contact in the existing multicomputer system between each CPU is more open, the general connection that relies on comparatively at a slow speed.Connected mode has bus type, grid and hypercube or the like.No matter which kind of connected mode all lacks fast contact closely, and the state of each CPU is not monitored between each CPU.
Summary of the invention
Therefore, the present invention is intended to overcome the above-mentioned defective that exists in the multi-CPU system of prior art, proposes a kind of multi-CPU system and its implementation.Intrasystem a plurality of CPU has the internal memory that exclusively enjoys separately, so belong to multicomputer system.This structure is in order to realize stronger stability, better security and communicating by letter between CPU faster, is fit to be applied to in the high system of real-time, security requirement.According to the present invention, a kind of multi-CPU system and its implementation are provided, comprising:
A kind of multi-CPU system, by a plurality of independent CPUs, a crosspoint and a timed message transmitting element are formed.
Multi-CPU system according to claim 1 is characterized in that, connects each other by described crosspoint between the described independent CPUs, and exchange message between each described separate CPU must be by described crosspoint.
Multi-CPU system according to claim 1 is characterized in that, being connected between described independent CPUs and the described crosspoint adopted direct connected mode at a high speed; Exchange messages by this connected mode between described crosspoint and the described independent CPUs.
Multi-CPU system according to claim 1 is characterized in that, described a plurality of independent CPUs, and described crosspoint and described timed message transmitting element are finished function with hardware.
Multi-CPU system according to claim 1, the method for exchange message is between the described independent CPUs:
A1, described independent CPUs and timed message transmitting element send to described message unit to the message of the information structuring one-tenth setting form that will send to described message then;
A2, described crosspoint are resolved message, learn the purpose CPU of described message; According to certain strategy message is filtered then, filter qualified message and deposit corresponding C PU in and treat in the Message Processing formation;
A3, described independent CPUs can constantly be handled the message in the pending Message Processing formation of this CPU in the described crosspoint under normal condition; For source address is the message of described timed message transmitting element, just abandons described message.
The method of exchange message between the CPU according to claim 5, described timed message transmitting element sends message to the pending message queue of described separate CPU in the described crosspoint according to the strategy of setting; Described crosspoint so that in time note abnormalities, recovers normally operation by the status information of described each separate CPU of monitoring message formation acquisition.
The method of exchange message between the CPU according to claim 5, if certain CPU is in abnomal condition, then this CPU can the described crosspoint of normal process in wait for the arrival of news message in the processing queue of this CPU, after a period of time, the processing queue that waits for the arrival of news of unusual CPU will be filled, then described crosspoint is judged this CPU abnormal state, and the system strategy according to setting resets to this CPU.
The safety problem that the method according to this invention has avoided shared drive to cause, and solved the consistency problem of the internal memory in the multiple processor system provides in the multi-CPU system new way of exchange message between each CPU; Simultaneously, but can provide system survivability and viability greatly to the monitoring of each CPU state in the system.According to the present invention, provide the system of a kind of high-level efficiency, high security.
Description of drawings
Fig. 1 is a bus type multicomputer system CPU communication mode synoptic diagram.
Fig. 2 is a bus type multicomputer system CPU communication mode synoptic diagram.
Fig. 3 is a multi-CPU system synoptic diagram shown in the present.
Fig. 4 is the schematic flow sheet that communicates between the CPU shown in the present.
Fig. 5 is the message format that each CPU of system shown in the present issues crosspoint.
Embodiment
The present invention is described in detail below in conjunction with the drawings and specific embodiments.
The present invention proposes the method that message is transmitted between a kind of multi-CPU system and CPU.The multi-CPU system that the present invention proposes comprises: a plurality of independent CPUs, a crosspoint.Wherein, each CPU is separate, and they connect each other by crosspoint pass-along message, and adopts high-speed channel directly to be connected between crosspoint and each CPU.The further system of many CPU that the present invention proposes comprises: a timed message transmitting element, and crosspoint and the cooperation of timed message transmitting element, the state of each CPU in the supervisory system so that in time note abnormalities, recovers the normal operation of CPU.
Fig. 3 is according to multi-CPU system synoptic diagram of the present invention.The multi-CPU system that the present invention proposes is by independently a plurality of CPU, crosspoint and timed message transmitting element constitute mutually.Wherein each CPU is separate, and has the internal memory that exclusively enjoys separately, and the communication between them realizes by crosspoint.
Crosspoint transmits module by message and the Filter module constitutes, and wherein message is transmitted module and is responsible for receiving the message of sending from separate CPU, and described message is sent to Filter module corresponding with the purpose CPU of message in the crosspoint; Each separate CPU in the multi-CPU system has a Filter module corresponding with it, is responsible for transmitting module from message and receives message, then described message is filtered, and is placed in the pending message queue of Filter module; The Filter module is known whether corresponding CPU is in normal condition, and in time the CPU that is in abnormality is recovered by the described pending message queue of monitoring.Because the CPU of operate as normal can take message within a certain period of time away and handle from pending message queue, therefore, as long as pending message queue is full, just show that corresponding CPU is in abnormality, crosspoint can reset to CPU, makes it recover the state of operate as normal.
The timed message transmitting element sends message by crosspoint to each independent CPUs according to the strategy of setting, and monitors the pending message queue of each CPU by crosspoint, in time finds to occur unusual CPU.Same CPU owing to operate as normal can take message within a certain period of time away and handle from pending message queue, therefore, as long as pending message queue is timed the message of message sending unit transmission and takes, just show that corresponding CPU is in abnormality, crosspoint can reset to CPU, makes it recover normal operation.
Among the present invention, the function of crosspoint itself is not subjected to the restriction of implementation method: can finish the required every function of crosspoint with a CPU in addition, can use hardware logic electric circuit to realize yet.The connected mode of each CPU and crosspoint is not subjected to the restriction of implementation method yet: can adopt a plurality of first in first out (FIFO) formation, can use high-speed serial communication yet.
Fig. 4 is the schematic flow sheet that communicates between the CPU shown in the present.Need the source CPU structure good news of transmission information, the form of message as shown in Figure 5.Then, source CPU transmits module to the message that the good message of structure sends in the crosspoint.Message is transmitted module the message that receives is resolved, learn according to the purpose CPU territory in the message which CPU is this message send to, because each separate CPU has a Filter module corresponding with it, message is transmitted module and is sent this message to the Filter module corresponding with purpose CPU, and promptly message is transmitted module and sent this message to the pending message queue corresponding with purpose CPU.The Filter module is filtered message according to the strategy of setting, a strategy that can adopt is: Filter is by the pending message queue of monitoring CPU, whether expired according to pending message queue and to have judged whether this CPU occurs unusually, the message that causes the CPU operation irregularity is put into the unexpected message storehouse, and regularly use existing feature extraction algorithm to carry out feature extraction to the unexpected message in the abnormal data storehouse, replace the unexpected message storage with the unexpected message feature, the unexpected message feature is classified to the reason that causes the CPU abnormality and is obtained; If the unexpected message feature that has in the message that receives and the unexpected message storehouse is identical, then this message will be filtered.The Filter module is put into the message that remains in the pending message queue of purpose CPU.CPU working properly can take message within a certain period of time away and handle from formation.If the message-length in the pending message queue of a CPU surpasses certain limit, then crosspoint just thinks that this CPU is in abnormality, so adopt certain measure that this CPU is recovered, for example CPU is resetted.
In order to make crosspoint learn that in time one does not need the CPU of processing messages whether working properly, the timed message transmitting element sends message according to the strategy of setting each separate CPU in multi-CPU system.The timed message transmitting element is the same with the connected mode of described crosspoint with other separate CPUs, directly links to each other with described crosspoint by high-speed channel.It sends message according to certain strategy to described crosspoint, and destination address is each separate CPU in the system, after described crosspoint is received this type of information, puts into the pending message queue of each separate CPU according to destination address.The message that it sends is a kind of special shape of described message, and the source is described timed message transmitting element.Described setting strategy can be every interval setting-up time length, and the timed message transmitting element just sends message to each separate CPU.
Fig. 5 is the message format that each CPU issues crosspoint.Message is made of four territories: source CPU, purpose CPU, message-length and message content.Wherein, on behalf of this message, source CPU by which CPU sent; Purpose CPU represents which CPU is this message send to; Message-length refers to how many bits are this message have; Message content then is the data content that sends to purpose CPU.
Crosspoint is monitored the pending message queue of each CPU, in time notes abnormalities and a specific embodiment recovering is:
Crosspoint is resolved message, is filtering each CPU is put in the back according to destination address pending message queue; Each separate CPU in the multi-CPU system is under normal condition, can constantly handle in the described crosspoint corresponding to the message in the pending message queue of this CPU, for source address is the message of other CPU, handle according to normal condition, for source address is described timed message transmitting element, just abandons this message; If certain CPU is in abnomal condition, then this CPU can the described crosspoint of normal process in corresponding to the message in the pending message queue of this CPU, after a period of time, the pending message queue of unusual CPU will be filled, and then described crosspoint is determined this CPU abnormal state.According to system strategy, this CPU is resetted.Can guarantee to find early the unusual of CPU, the normal operation that in time recovers CPU like this.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1, a kind of multi-CPU system comprises:
A plurality of independent CPUs;
A timed message transmitting element is used for sending message according to setting strategy to described separate CPU;
Whether a crosspoint be used to described independent CPUs and described timed message transmitting element pass-along message, and it is working properly to monitor described separate CPU.
2, multi-CPU system according to claim 1 is characterized in that, isolates mutually between the described independent CPUs, can only be by described crosspoint exchange message.
3, multi-CPU system according to claim 1 is characterized in that, described crosspoint comprises:
Message is transmitted module: be used to receive the message of sending from described separate CPU, and described message is sent to Filter module corresponding with the purpose CPU of described message in the described crosspoint;
The Filter module: each described separate CPU has the Filter module of a correspondence, is used for being responsible for to transmit module from message and receives message, then described message is filtered, and is placed in the pending message queue; Described Filter module is known whether corresponding CPU is in normal condition, and in time the CPU that is in abnormality is recovered by the described pending message queue of monitoring.
4, multi-CPU system according to claim 1, it is characterized in that, described timed message transmitting element sends message for described separate CPU according to the strategy of setting by described crosspoint, and described crosspoint finds in time by this message whether described separate CPU occurs unusually.
5, multi-CPU system according to claim 1 is characterized in that, being connected between described independent CPUs and the described crosspoint adopted the high speed serialization mode.
6, multi-CPU system according to claim 1 is characterized in that, pass-along message adopts first in first out Chinese FIFO mode between described independent CPUs and the described crosspoint.
7, a kind of based on the method that message is transmitted between the CPU in the described multi-CPU system of claim 1, between the described independent CPUs or described timed message transmitting element step from information to described independent CPUs that transmit be:
B1, described independent CPUs or timed message transmitting element are the message of the information structuring one-tenth setting form that will send, and the message that described message is sent in the described message unit is transmitted module then;
B2, described message are transmitted module parses message, learn the purpose CPU of described message, transmit the information to the corresponding Filter module with purpose CPU then;
B3, described Filter module are filtered the message that receives, and put into pending message queue then;
B4, described independent CPUs can constantly be taken message away and handle under normal condition from corresponding pending Message Processing formation; For source address is the message of described timed message transmitting element, just abandons described message.
8, the method for exchange message between the separate CPU according to claim 7, it is characterized in that, the method that described Filter filters message is: Filter is causing that the unusual message of CPU puts into the unexpected message storehouse, if the message that receives later on has identical feature with message in the abnormal data storehouse, then the described message screening that receives is fallen.
9, the method for exchange message between the separate CPU according to claim 7 is characterized in that the message of described setting form comprises: source CPU, purpose CPU, message-length and message content.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200610072755 CN100538690C (en) | 2006-04-10 | 2006-04-10 | The method that message is transmitted between a kind of multi-CPU system and the CPU |
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| CN 200610072755 CN100538690C (en) | 2006-04-10 | 2006-04-10 | The method that message is transmitted between a kind of multi-CPU system and the CPU |
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| CN101055556A true CN101055556A (en) | 2007-10-17 |
| CN100538690C CN100538690C (en) | 2009-09-09 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102185958A (en) * | 2010-12-23 | 2011-09-14 | 上海华勤通讯技术有限公司 | Method for sharing central processing unit (CPU) of intelligent mobile phone |
| CN103309840A (en) * | 2013-07-08 | 2013-09-18 | 天津汉柏汉安信息技术有限公司 | Connection establishment method and device |
| CN106293900A (en) * | 2015-05-20 | 2017-01-04 | 宇龙计算机通信科技(深圳)有限公司 | Processing method, device and the terminal of application in a kind of multiple operating system terminal |
| CN106598810A (en) * | 2016-12-16 | 2017-04-26 | 中国航空工业集团公司洛阳电光设备研究所 | Multi-CPU airborne data processing unit BIT monitoring architecture |
| CN111723919A (en) * | 2019-03-21 | 2020-09-29 | 中科寒武纪科技股份有限公司 | Data processing method and device and related products |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5581705A (en) * | 1993-12-13 | 1996-12-03 | Cray Research, Inc. | Messaging facility with hardware tail pointer and software implemented head pointer message queue for distributed memory massively parallel processing system |
| US5925099A (en) * | 1995-06-15 | 1999-07-20 | Intel Corporation | Method and apparatus for transporting messages between processors in a multiple processor system |
| FR2770665B1 (en) * | 1997-11-06 | 2002-12-20 | Alsthom Cge Alkatel | EXCHANGE DEVICE BETWEEN INFORMATION PROCESSING UNITS WITH PROCESSORS INTERCONNECTED BY A COMMON BUS |
| US20020161594A1 (en) * | 2001-04-27 | 2002-10-31 | Bryan Helen Elizabeth | Method and system for providing remote quality assurance audits |
| US20040107240A1 (en) * | 2002-12-02 | 2004-06-03 | Globespan Virata Incorporated | Method and system for intertask messaging between multiple processors |
| CN1295633C (en) * | 2002-12-26 | 2007-01-17 | 华为技术有限公司 | Method for multiple CPU communication |
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2006
- 2006-04-10 CN CN 200610072755 patent/CN100538690C/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102185958A (en) * | 2010-12-23 | 2011-09-14 | 上海华勤通讯技术有限公司 | Method for sharing central processing unit (CPU) of intelligent mobile phone |
| CN102185958B (en) * | 2010-12-23 | 2014-03-26 | 上海华勤通讯技术有限公司 | Method for sharing central processing unit (CPU) of intelligent mobile phone |
| CN103309840A (en) * | 2013-07-08 | 2013-09-18 | 天津汉柏汉安信息技术有限公司 | Connection establishment method and device |
| CN106293900A (en) * | 2015-05-20 | 2017-01-04 | 宇龙计算机通信科技(深圳)有限公司 | Processing method, device and the terminal of application in a kind of multiple operating system terminal |
| CN106598810A (en) * | 2016-12-16 | 2017-04-26 | 中国航空工业集团公司洛阳电光设备研究所 | Multi-CPU airborne data processing unit BIT monitoring architecture |
| CN111723919A (en) * | 2019-03-21 | 2020-09-29 | 中科寒武纪科技股份有限公司 | Data processing method and device and related products |
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| CN100538690C (en) | 2009-09-09 |
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Granted publication date: 20090909 Termination date: 20190410 |