CN106776462B - Computer with multiple processors and operation method thereof - Google Patents
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- CN106776462B CN106776462B CN201710011192.XA CN201710011192A CN106776462B CN 106776462 B CN106776462 B CN 106776462B CN 201710011192 A CN201710011192 A CN 201710011192A CN 106776462 B CN106776462 B CN 106776462B
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- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
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- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
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Abstract
The invention discloses a computer with multiple processors in the technical field of computers, which comprises a main processor, wherein the main processor is electrically input and connected with an input unit, the main processor is electrically connected with a data analysis system in a bidirectional way, the main processor is electrically output and connected with a driving unit, the driving unit is electrically output and connected with a display, the main processor is electrically connected with a switching unit in a bidirectional way, and the switching unit is respectively electrically connected with a high-performance slave processing system, a common-performance slave processing system and a low-performance slave processing system in a bidirectional way, no confusion occurs.
Description
Technical Field
The invention relates to the technical field of computers, in particular to a computer with multiple processors and an operation method thereof.
Background
A multiprocessor computer is a computer having a plurality of processors. The multiprocessor architecture has two objectives, one being to look at improving reliability to photograph certain high availability applications (or mission critical applications) that require a long-term, non-brief operation; the second is to increase the processing power of the computer. The former was the main goal in the 60-70 s, when the electronic circuits of the central processing units were complex, and when one or more processors failed, the system could still continue to work (the capacity may be reduced), and the current so-called "fault-tolerant computers" were often based on this principle. The 90 s were entered, with the primary objective being pursued. The multiprocessor structure has become a popular design method for computers of various grades, a high-grade PC adopts 2-4 processors, a mainframe can use dozens of processors, a huge computer can adopt hundreds of even thousands of processors, and with the development of the society, the data processing efficiency of a common single-processor computer cannot well meet the requirement of the data processing rate at present.
Disclosure of Invention
The present invention is directed to a computer with multiple processors and a method for operating the same, so as to solve the problem that the efficiency of processing data by the general single-processor computer proposed in the above background art cannot well meet the current requirement for data processing rate.
In order to achieve the purpose, the invention provides the following technical scheme: a computer with multiple processors comprises a main processor, wherein the main processor is electrically connected with an input unit in an input mode, the main processor is electrically connected with a data analysis system in a bidirectional mode, the main processor is electrically connected with a driving unit in an output mode, the driving unit is electrically connected with a display in an output mode, the main processor is electrically connected with a switching unit in a bidirectional mode, the switching unit is respectively electrically connected with a high-performance slave processing system, a common-performance slave processing system and a low-performance slave processing system in a bidirectional mode, the high-performance slave processing system is electrically connected with a first dual-port memory in a bidirectional mode, the first dual-port memory is electrically connected with a common-performance slave processing system in a bidirectional mode, the common-performance slave processing system is electrically connected with a second dual-port memory in a bidirectional mode, the second dual-port memory is electrically connected with a low, the third dual-port memory is electrically and bidirectionally connected with the high-performance slave processing system.
Preferably, the data analysis system comprises a data extraction unit, the data extraction unit is electrically connected with a microprocessor, the microprocessor is electrically connected with a data analysis unit, the data analysis unit is electrically connected with a judgment and inference unit, and the judgment and inference unit is electrically connected with a data feedback unit.
Preferably, the high-performance slave processing system comprises a first data receiving unit, the first data receiving unit is electrically connected with a first data query unit in output, the first data query unit is electrically connected with a first timer in input, the first data query unit is electrically connected with a high-performance slave processor in output, the high-performance slave processor is electrically connected with a first counter in input, the high-performance slave processor is electrically connected with a first local storage in both directions, and the high-performance slave processor is electrically connected with a first data transmission unit in output.
Preferably, the normal performance slave processing system comprises a second data receiving unit, the second data receiving unit is electrically connected with a second data query unit in output, the second data query unit is electrically connected with a second timer in input, the second data query unit is electrically connected with a normal performance slave processor in output, the normal performance slave processor is electrically connected with a second counter in input, the normal performance slave processor is electrically connected with a second local storage in both directions, and the normal performance slave processor is electrically connected with a second data transmission unit in output.
Preferably, the low-performance slave processing system comprises a third data receiving unit, the third data receiving unit is electrically connected with a third data query unit in output, the third data query unit is electrically connected with a third timer in input, the third data query unit is electrically connected with a low-performance slave processor in output, the low-performance slave processor is electrically connected with a third counter in input, the low-performance slave processor is electrically connected with a third local storage in two directions, and the low-performance slave processor is electrically connected with a third data transmission unit in output.
Preferably, the method for operating the computer with multiple processors includes the following specific steps:
s1: detection of the shared storage network: the first counter, the second counter and the third counter respectively count the operation of the high-performance slave processing system, the normal-performance slave processing system and the low-performance slave processing system in each second, and the data analysis system analyzes the feedback data to judge whether the operation of the shared storage network is normal or not;
s2: and (3) creating a task: inputting data of a task through an input unit, completing the creation of the task, and inputting processing requirements for the task into the created task data when the task is established;
s3: and (3) task allocation: analyzing the newly created task through a data analysis system, judging the requirement of the newly created task on the performance of a processor, judging the priority of the newly created task, and distributing the task after data judgment;
s4: task scheduling: scheduling the tasks distributed by each slave processor according to the priorities of the distributed tasks;
s5: summary and display of processed data: the processed data is displayed by controlling the driving unit to drive the display through the main processor.
Preferably, in step S1, the specific content of determining whether the shared storage network is operating normally includes that if the first counter, the second counter, and the third counter have the same value and the value is not zero, the shared storage network is normal, and if the first counter, the second counter, and the third counter have different values, the shared storage network is abnormal.
Preferably, in step S3, the specific content of allocating the tasks includes allocating the tasks with low requirements for processor performance to the low-performance slave processing system for processing, allocating the tasks with normal requirements for processor performance to the normal-performance slave processing system, and allocating the tasks with high requirements for processor performance to the high-performance slave processing system for processing.
Preferably, in step S4, the task scheduling manner includes preemptible scheduling, non-preemptible scheduling, and time slice rotating scheduling, where the preemptible scheduling refers to that based on the priority of the task, the task currently running by the slave processor can be given up to another task with a higher priority, the non-preemptible scheduling refers to that a task cannot be replaced once being run by the slave processor, unless the master processor forcibly suspends the task, and the time slice rotating scheduling refers to that when two or more tasks with the same priority are allocated to one slave processor, the tasks are scheduled according to the order of the allocated tasks.
Compared with the prior art, the invention has the beneficial effects that: compared with the existing single-processor computer, the invention has higher data processing efficiency, and the invention distributes the task data to different slave processors for processing through the analysis and judgment of the task data, thereby ensuring that a plurality of tasks can be carried out simultaneously, and the task scheduling can lead the task to be carried out more orderly without confusion.
Drawings
FIG. 1 is a schematic block diagram of the present invention;
FIG. 2 is a schematic block diagram of a data analysis system of the present invention;
FIG. 3 is a functional block diagram of a high performance slave processing system of the present invention;
FIG. 4 is a functional block diagram of a generic performance slave processing system of the present invention;
FIG. 5 is a functional block diagram of a low performance slave processing system of the present invention;
FIG. 6 is a flow chart of the method of operation of the present invention.
In the figure: 1 main processor, 2 input unit, 3 data analysis system, 4 drive unit, 5 display, 6 switching unit, 7 high performance slave processing system, 71 first data receiving unit, 72 first data query unit, 73 first timer, 74 high performance processor, 75 first counter, 76 first local memory, 77 first data transmission unit, 8 normal performance slave processing system, 81 second data receiving unit, 82 second data query unit, 83 second timer, 84 normal performance processor, 85 second counter, 86 second local memory, 87 second data transmission unit, 9 low performance slave processing system, 91 third data receiving unit, 92 third data query unit, 93 third timer, 94 low performance processor, 95 third counter, 96 third local memory, 97 third data transmission unit, 10 first dual port memory, 2 first data receiving unit, 72 first data query unit, 73 first timer, 74 second local memory, and 76 second local memory, 11 a second dual port memory, 12 a third dual port memory.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1-6, the present invention provides a technical solution: a computer with a plurality of processors comprises a main processor 1, wherein the main processor 1 is electrically connected with an input unit 2 in an input mode, data of tasks are input through the input unit 2, and the computer main body can be controlled and operated through the input unit 2, the main processor 1 is electrically connected with a data analysis system 3 in a two-way mode, the data analysis system 3 judges the priority level of the input task data, judges the requirement of the processor performance and judges whether the shared network operates normally or not, the main processor 1 is electrically connected with a driving unit 4 in an output mode, the driving unit 4 is electrically connected with a display 5 in an output mode, the main processor 1 controls the driving unit 4 to drive the display 5, the display 5 displays the processed data and the data input by the input unit 2, the main processor 1 is electrically connected with a switching unit 6 in a two-way mode, when the tasks are distributed, the auxiliary processing systems are switched through the switching unit 6, the switching unit 6 is electrically connected with the high-performance slave processing system 7, the normal-performance slave processing system 8 and the low-performance slave processing system 9 in a bidirectional manner, respectively, the high-performance slave processing system 7 is electrically connected with the first dual-port memory 10 in a bidirectional manner, the first dual-port memory 10 is electrically connected with the normal-performance slave processing system 8 in a bidirectional manner, the normal-performance slave processing system 8 is electrically connected with the second dual-port memory 11 in a bidirectional manner, the second dual-port memory 11 is electrically connected with the low-performance slave processing system 9 in a bidirectional manner, the low-performance slave processing system 9 is electrically connected with the third dual-port memory 12 in a bidirectional manner, the dual-port memories have very high communication rates, and flexible communication protocol establishing modes are adopted, and the high-performance slave processing system 7, the normal-performance slave processing system 8 and the low-performance slave processing system 9 are connected together in pairs through the first dual, thereby forming a shared memory network, and the third dual-port memory 12 is electrically connected to the high-performance slave processing system 7 in a bidirectional way.
The data analysis system 3 comprises a data extraction unit 31, the data extraction unit 31 is electrically connected with a microprocessor 32, the microprocessor 32 is electrically connected with a data analysis unit 33, the data analysis unit 33 is electrically connected with a judgment and inference unit 34, the judgment and inference unit 34 is electrically connected with a data feedback unit 35, the data analysis system 3 extracts the task data input by the input unit 2 and the data fed back from the high-performance slave processing system 7, the normal-performance slave processing system 8 and the low-performance slave processing system 9 through the data extraction unit 31, the extracted data is transmitted to the data analysis unit 33 through the microprocessor 32, the data analysis unit 33 analyzes the extracted data, and the specific analysis content comprises the analysis of the priority of the task data input by the input unit 2, the analysis of the required processor performance requirement of the task data input by the input unit 2 and the classification of the data fed back by the switching unit 6 Analyzing, the analyzed data is judged and inferred by the inference judging unit 34, the main judgment content comprises the judgment of the priority level of the input task data, the judgment of the requirement of the processor performance and the judgment of whether the shared network operates normally, and the judged data is fed back to the main processor 1 by the data feedback unit 35;
the high-performance slave processing system 7 comprises a first data receiving unit 71, the first data receiving unit 71 is electrically connected with a first data query unit 72 in output, the first data query unit 72 is electrically connected with a first timer 73 in input, the first data query unit 72 is electrically connected with a high-performance slave processor 74 in output, the high-performance slave processor 74 is electrically connected with a first counter 75 in input, the high-performance slave processor 74 is electrically connected with a first local memory 76 in bidirectional way, the high-performance slave processor 74 is electrically connected with a first data transmission unit 77 in output, the first data receiving unit 71 respectively receives task data transmitted by the switching unit 6 and data transmitted by the first dual-port memory 10 and the third dual-port memory 12, the data received by the first dual-port memory 10 and the third dual-port memory 12 are intermittently queried by the first data query unit 72, the first timer 73 counts the discontinuous period, the first data query unit 72 judges whether the first data receiving unit 71 receives data, the task data is transmitted to the high-performance slave processor 74 through the first data query unit 72 to perform task operation, the first counter 75 counts the operation transmission of the high-performance slave processor 74 every second to provide a data basis for detecting the shared storage network, the first local storage 76 stores all received data to facilitate subsequent data extraction, and the first data transmission unit 77 transmits the data after the task is completed and the data in the first local storage 76;
the normal performance slave processing system 8 comprises a second data receiving unit 81, the second data receiving unit 81 is electrically connected with a second data query unit 82 in output, the second data query unit 82 is electrically connected with a second timer 83 in input, the second data query unit 82 is electrically connected with a normal performance slave processor 84 in output, the normal performance slave processor 84 is electrically connected with a second counter 85 in input, the normal performance slave processor 84 is electrically connected with a second local memory 86 in two directions, the normal performance slave processor 84 is electrically connected with a second data transmission unit 87 in output, the second data receiving unit 81 respectively receives the task data transmitted by the switching unit 6 and the data transmitted by the first dual-port memory 10 and the second dual-port memory 11, the data received by the first dual-port memory 10 and the second dual-port memory 11 is subjected to intermittent query by the second data query unit 82, the second timer 83 times the discontinuous period, the second data querying unit 82 is used for judging whether the second data receiving unit 81 receives data, the task data is transmitted to the normal performance slave processor 84 through the second data querying unit 82 for task operation, the second counter 85 counts the operation transmission of the normal performance slave processor 84 per second to provide a data basis for detection of the shared storage network, the second local storage 86 stores all the received data to facilitate subsequent data extraction, and the second data transmission unit 87 transmits the data after the task is completed and the data in the second local storage 86;
the low-performance slave processing system 9 comprises a third data receiving unit 91, the third data receiving unit 91 is electrically connected with a third data query unit 92 in output, the third data query unit 92 is electrically connected with a third timer 93 in input, the third data query unit 92 is electrically connected with a low-performance slave processor 94 in output, the low-performance slave processor 94 is electrically connected with a third counter 95 in input, the low-performance slave processor 94 is electrically connected with a third local memory 96 in two directions, the low-performance slave processor 94 is electrically connected with a third data transmission unit 97 in output, the third data receiving unit 91 respectively receives task data transmitted by the switching unit 6 and data transmitted by the second dual-port memory 11 and the third dual-port memory 12, and data received by the second dual-port memory 11 and the third dual-port memory 12 are queried discontinuously through the third data query unit 92, the third timer 93 times the discontinuous period, the third data query unit 92 is used for judging whether the third data receiving unit 91 receives data, the task data is transmitted to the low-performance slave processor 94 through the third data query unit 92 for task operation, the third counter 95 counts the operation transmission of the low-performance slave processor 94 per second, a data basis is provided for detection of the shared storage network, the third local storage 96 stores all received data, subsequent data extraction is facilitated, and the third data transmission unit 97 transmits the data after the task is completed and the data in the third local storage 96;
an operation method of a computer with multiple processors includes the following steps:
s1: detection of the shared storage network: the first counter 75, the second counter 85, and the third counter 95 respectively count the operations of the high-performance slave processing system 7, the normal-performance slave processing system 8, and the low-performance slave processing system 9, namely, the high-performance slave processor 74, the normal-performance slave processor 84, and the low-performance slave processor 94, each second, and analyze the feedback data through the data analysis system 3, thereby determining whether the operations of the shared storage network are normal, in step S1, the specific content of determining whether the operations of the shared storage network are normal includes that if the values of the first counter 75, the second counter 85, and the third counter 95 are the same and the value is not zero, the shared storage network is normal, and if the values of the first counter 75, the second counter 85, and the third counter 95 are not the same, the shared storage network is not normal;
s2: and (3) creating a task: inputting data of a task through the input unit 2, completing creation of the task, and inputting processing requirements for the task into the created task data when the task is established;
s3: and (3) task allocation: analyzing the newly created task through the data analysis system 3, judging the requirement of the newly created task on the performance of the processor, judging the priority of the newly created task, and distributing the task after data judgment, wherein in step S3, the specific content of distributing the task comprises distributing the task with low requirement on the performance of the processor to the low-performance slave processing system 9 for processing, distributing the task with ordinary requirement on the performance of the processor to the ordinary-performance slave processing system 8, and distributing the task with high requirement on the performance of the processor to the high-performance slave processing system 7 for processing;
s4: task scheduling: scheduling the tasks allocated to each slave processor according to the priorities of the allocated tasks, wherein in step S4, the task scheduling modes include preemptive scheduling, non-preemptive scheduling and time slice rotating scheduling, the preemptive scheduling refers to the priority based on the tasks, the task currently running by the slave processor can be given up to other ready tasks with higher priority, the non-preemptive scheduling refers to a task which cannot be replaced once being run by the slave processor, unless the master processor 1 forcibly suspends the task, the time slice rotating scheduling refers to scheduling according to the sequence of the allocated tasks after two or more tasks with the same priority are allocated to one slave processor;
s5: summary and display of processed data: the processed data is displayed by controlling the driving unit 4 through the main processor 1 to drive the display 5.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (1)
1. A method of operation of a computer having multiple processors, comprising a main processor (1), characterized by: the main processor (1) is electrically connected with the input unit (2) in an input mode, the main processor (1) is electrically connected with the data analysis system (3) in a two-way mode, the main processor (1) is electrically connected with the driving unit (4) in an output mode, the driving unit (4) is electrically connected with the display (5) in an output mode, the main processor (1) is electrically connected with the switching unit (6) in a two-way mode, the switching unit (6) is respectively and electrically connected with the high-performance slave processing system (7), the common-performance slave processing system (8) and the low-performance slave processing system (9) in a two-way mode, the high-performance slave processing system (7) is electrically connected with the first dual-port memory (10) in a two-way mode, the first dual-port memory (10) is electrically connected with the common-performance slave processing system (8, the second dual-port memory (11) is electrically and bidirectionally connected with the low-performance slave processing system (9), the low-performance slave processing system (9) is electrically and bidirectionally connected with the third dual-port memory (12), and the third dual-port memory (12) is electrically and bidirectionally connected with the high-performance slave processing system (7);
the data analysis system (3) comprises a data extraction unit (31), the data extraction unit (31) is electrically connected with a microprocessor (32) in output, the microprocessor (32) is electrically connected with a data analysis unit (33) in output, the data analysis unit (33) is electrically connected with a judgment and inference unit (34) in output, and the judgment and inference unit (34) is electrically connected with a data feedback unit (35) in output;
the high-performance slave processing system (7) comprises a first data receiving unit (71), wherein the first data receiving unit (71) is electrically connected with a first data query unit (72) in output, the first data query unit (72) is electrically connected with a first timer (73) in input, the first data query unit (72) is electrically connected with a high-performance slave processor (74) in output, the high-performance slave processor (74) is electrically connected with a first counter (75) in input, the high-performance slave processor (74) is electrically connected with a first local memory (76) in both directions, and the high-performance slave processor (74) is electrically connected with a first data transmission unit (77) in output;
the common performance slave processing system (8) comprises a second data receiving unit (81), the second data receiving unit (81) is electrically connected with a second data query unit (82) in output, the second data query unit (82) is electrically connected with a second timer (83) in input, the second data query unit (82) is electrically connected with a common performance slave processor (84) in output, the common performance slave processor (84) is electrically connected with a second counter (85) in input, the common performance slave processor (84) is electrically connected with a second local memory (86) in two ways, and the common performance slave processor (84) is electrically connected with a second data transmission unit (87) in output;
the low-performance slave processing system (9) comprises a third data receiving unit (91), the third data receiving unit (91) is electrically connected with a third data query unit (92) in an input mode, the third data query unit (92) is electrically connected with a third timer (93) in an output mode, the third data query unit (92) is electrically connected with a low-performance slave processor (94) in an output mode, the low-performance slave processor (94) is electrically connected with a third counter (95) in an input mode, the low-performance slave processor (94) is electrically connected with a third local memory (96) in a bidirectional mode, and the low-performance slave processor (94) is electrically connected with a third data transmission unit (97) in an output mode;
the operation method of the computer with the multiple processors comprises the following specific steps:
s1: detection of the shared storage network: the first counter (75), the second counter (85) and the third counter (95) respectively count the operation of the high-performance slave processing system (7), the normal-performance slave processing system (8) and the low-performance slave processing system (9) in the high-performance slave processing system (74), the normal-performance slave processing system (84) and the low-performance slave processing system (94) every second, and the data analysis system (3) analyzes the fed-back data to judge whether the operation of the shared storage network is normal or not;
s2: and (3) creating a task: inputting data of a task through an input unit (2), completing creation of the task, and inputting processing requirements for the task into the created task data when the task is established;
s3: and (3) task allocation: analyzing the newly created task through the data analysis system (3), judging the requirement of the newly created task on the performance of the processor, judging the priority of the newly created task, and distributing the task after data judgment;
s4: task scheduling: scheduling the tasks distributed by each slave processor according to the priorities of the distributed tasks;
s5: summary and display of processed data: the processed data is displayed by controlling a driving unit (4) to drive a display (5) through a main processor (1);
in step S1, the specific content of determining whether the shared storage network is operating normally includes that if the first counter (75), the second counter (85), and the third counter (95) have the same value and the value is not zero, the shared storage network is normal, and if the first counter (75), the second counter (85), and the third counter (95) have different values, the shared storage network is not normal;
in step S3, the specific content of allocating the tasks includes allocating the tasks with low requirements for processor performance to the low-performance slave processing system (9) for processing, allocating the tasks with normal requirements for processor performance to the normal-performance slave processing system (8), and allocating the tasks with high requirements for processor performance to the high-performance slave processing system (7) for processing;
in step S4, the task scheduling manners include preemptive scheduling, non-preemptive scheduling, and time slice rotation scheduling, where the preemptive scheduling refers to that a task currently running on the slave processor can be given up to another task with a higher priority at any time based on the priority of the task, the non-preemptive scheduling refers to that a task cannot be replaced once the slave processor runs, unless the master processor (1) forcibly suspends the task, and the time slice rotation scheduling refers to that when two or more tasks with the same priority are allocated to one slave processor, the tasks are scheduled according to the order of the allocated tasks.
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