CN116150051A

CN116150051A - Command processing method, device and system

Info

Publication number: CN116150051A
Application number: CN202211475666.3A
Authority: CN
Inventors: 陈永光; 黄勇平
Original assignee: Shenzhen Yunbao Intelligent Co ltd
Current assignee: Shenzhen Yunbao Intelligent Co ltd
Priority date: 2022-11-23
Filing date: 2022-11-23
Publication date: 2023-05-23

Abstract

The invention discloses a command processing method, a device and a system, wherein the method comprises the following steps: under the condition that the current credit value to be used of the host module meets the command sending condition, sending a command to be processed to the bus interconnection module so as to send the command to be processed to the slave module through the bus interconnection module; and receiving and updating the credit value to be currently used according to a first signal sent by the bus interconnection module and/or a second signal sent by the slave module, wherein the first signal indicates that the bus interconnection module has responded to the command to be processed, the second signal indicates that the slave module has responded to the target command, and the target command is the command to be processed or other commands to be processed cached on a link between the host module and the slave module, and the time of the other commands to be processed is sent before the sending time value of the command to be processed. Through the technical scheme, labor cost and time cost are effectively reduced, iteration efficiency is improved, and command transmission of the host module can be accurately controlled.

Description

Command processing method, device and system

Technical Field

The present invention relates to the field of computer technologies, and in particular, to a method, an apparatus, and a system for processing a command.

Background

In large-scale digital chip designs, there are often multiple functional modules, and different host modules may need to access the slave modules to perform different processes on the data, so there are cases where multiple host modules access the same slave module, and this access is typically accomplished through standard bus protocols and bus interconnect modules. In the case where multiple host modules access the same slave module, command buffering is typically present on the link because the physical distance between the modules is large, which makes timing closure difficult.

At present, the host module, the slave module and the bus interconnection module are the IPs (Intelligent Peripheral ) purchased from third-party manufacturers or the IPs multiplexed by a plurality of items in a company, and these IPs do not consider the problem of command caching, i.e. do not set up interfaces for counting cache commands. In this case, significant labor and time costs are required to custom modify these IPs. If the number of the switchboard modules is modified, the IPs are also modified, and quick iteration cannot be realized. In addition, because of the existence of the command cache, the number of commands received by the slave modules is different from that of commands sent by each host module, and functional errors such as command overflow are easy to generate.

Disclosure of Invention

The invention provides a command processing method, a device and a system, which are used for avoiding the problem of command overflow in a slave module, effectively reducing labor cost and time cost, improving iteration efficiency and precisely controlling the number of commands to be processed on a link from a host module to the slave module.

According to an aspect of the present invention, there is provided a command processing method including:

under the condition that the current credit value to be used of the host module meets the command sending condition, the host module sends a command to be processed to a bus interconnection module so as to send the command to be processed to a slave module through the bus interconnection module;

the host module receives and updates the current credit value to be used according to a first signal sent by the bus interconnection module and/or a second signal sent by the slave module, wherein the first signal is used for indicating that the bus interconnection module has responded to the command to be processed, the second signal is used for indicating that the slave module has responded to a target command, the target command is the command to be processed or other commands to be processed cached on a link between the host module and the slave module, and the time for sending the other commands to be processed by the host module is earlier than the sending time of the command to be processed.

Preferably, the credit value updating unit is specifically configured to:

when the host module only receives the first signal, the host module obtains the updated credit value to be used by subtracting one from the current credit value to be used.

Preferably, the credit value updating unit is specifically configured to:

when the host module only receives the second signal, the host module adds one to the current credit value to be used to obtain the updated credit value to be used.

Preferably, the credit value updating unit is specifically configured to:

and when the host module receives the first signal and the second signal simultaneously, the current credit value to be used is used as the updated value to be used.

According to another aspect of the present invention, there is provided a command processing apparatus configured in a host module, comprising:

a credit value determining unit for determining that the credit value to be used currently meets the command sending condition;

a sending unit, configured to send a command to be processed when the current credit value to be used meets a command sending condition;

the receiving unit is used for receiving the first signal sent by the bus interconnection module and/or the second signal sent by the slave module;

And the credit value updating unit is used for updating the credit value to be currently used according to the first signal and/or the second signal, wherein the first signal is used for indicating that the bus interconnection module has responded to the command to be processed, the second signal is used for indicating that the slave module has responded to a target command, the target command is the command to be processed or other commands to be processed, which are cached on a link between the host module and the slave module, and the time for the host module to send the other commands to be processed is earlier than the sending time of the commands to be processed.

Preferably, the updating, by the host module, the current credit value to be used according to the first signal sent by the bus interconnection module specifically includes:

Preferably, the updating, by the host module, the current credit value to be used according to the second signal sent by the slave module specifically includes:

Preferably, the updating, by the host module, the current credit value to be used according to the first signal sent by the bus interconnection module and the second signal sent by the slave module specifically includes:

Preferably, the method further comprises:

and the host module receives the back pressure signal sent by the slave module, and responds to the back pressure signal, the host module stops sending the command to be processed.

According to another aspect of the present invention, there is provided a command processing system, the system comprising: the system comprises at least one host module, a bus interconnection module and a slave module, wherein the host module is in communication connection with the bus interconnection module, and the bus interconnection module is in communication connection with the slave module; wherein, the host module is used for:

According to the technical scheme, under the condition that the credit value to be used of the host module meets the command sending condition, the host module sends the command to be processed to the bus interconnection module, so that the command to be processed is sent to the slave module through the bus interconnection module, and the sending of the command to be processed can be determined through the credit value to be used of the host module; the host module receives and updates the current credit value to be used according to the first signal sent by the bus interconnection module and/or the second signal sent by the slave module, wherein the first signal is used for indicating that the bus interconnection module has responded to the command to be processed, the second signal is used for indicating that the slave module has responded to the command to be processed or other commands to be processed which are cached on a link between the host module and the slave module and whose sending time is earlier than the command to be processed, the current credit value to be used of the host module can be updated according to the response states of the bus interconnection module and the slave module, the problem of command overflow in the slave module caused by the fact that the number of the commands to be processed sent by the host module and the number of the commands to be processed cached on the link cannot be monitored is solved, the technical effects of effectively reducing labor cost and time cost, improving iteration efficiency and precisely controlling the command sending number of the host module are achieved.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a flow chart of a command processing method according to an embodiment of the invention;

fig. 2 is a schematic structural diagram of a command processing device according to a fourth embodiment of the present invention;

FIG. 3 is a schematic diagram of a command processing system according to a third embodiment of the present invention;

FIG. 4 is a schematic diagram of an example architecture of a command processing system according to a fifth embodiment of the present invention;

fig. 5 is a schematic structural diagram of an electronic device according to a sixth embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

It will be appreciated that the data (including but not limited to the data itself, the acquisition or use of the data) involved in the present technical solution should comply with the corresponding legal regulations and the requirements of the relevant regulations.

Example 1

Fig. 1 is a flow chart of a command processing method according to an embodiment of the present invention, where the embodiment is applicable to a case where one or more host modules send a command to be processed to a slave module, so that the slave module responds to the command to be processed and performs corresponding processing, the method may be performed by a command processing device, and the command processing device may be implemented in a form of hardware and/or software, and the command processing device may be configured in an electronic device.

As shown in fig. 1, the method includes:

s110, under the condition that the credit value to be used of the host module meets the command sending condition, the host module sends a command to be processed to the bus interconnection module, so that the command to be processed is sent to the slave module through the bus interconnection module.

The host module may be a module that issues a command to be processed, and may generally be a functional module under a bus architecture. The credit value to be used may be a value that measures whether the host module is able to issue the number of commands to be processed. Each host module is pre-assigned a credit upper limit. The upper credit limits of different host modules may be the same or different. The credit value to be used of the host module is related to the actual working state of the host module, and the upper limit of the credit value is not exceeded. Specifically, the credit value to be used may be updated according to the transmission and processing of the command to be processed.

Optionally, for each host module, the host module determines an upper credit limit corresponding to the host module according to the concurrency capability of the host module. The concurrency capability may be a basic capability of the host module, and is used to describe the number of requests that can be processed in a unit time. Specifically, the upper limit of the credit value corresponding to each host module may be determined in the same manner for each host module, and thus one of the host modules is illustrated as an example. The host module can determine own concurrency capability, and determine the credit value upper limit corresponding to the host module according to the preset corresponding relation between the concurrency capability and the credit value upper limit.

The command sending condition may be a condition that determines whether a command to be processed can be sent according to the credit value to be used, for example, the command sending condition may be that the credit value to be used is greater than zero. The bus interconnect module may be a module responsible for command arbitration and access routing for the host module, for connecting the host module and the slave module. The bus interconnect module may have multiple levels or multiple levels, and the specific bus architecture is set according to the actual requirements. The command to be processed may be a command sent by the host module, a command responded by the slave module may be an information access command, etc. The slave module may be an accessed module for responding to pending commands sent by the host module and other pending commands buffered on the link between the host module and the slave module.

Specifically, the host module determines whether the credit value to be used satisfies the command transmission condition. If not, the host module can wait for the preset time to judge again. If so, the host module can send the command to be processed to the bus interconnection module so as to send the command to be processed to the slave module for response and processing through the bus interconnection module.

And S120, the host module receives and updates the credit value to be used currently according to the first signal sent by the bus interconnection module and/or the second signal sent by the slave module.

The first signal is used for indicating that the bus interconnection module has responded to the to-be-processed command, the second signal is used for indicating that the slave module has responded to a target command, the target command is the to-be-processed command or other to-be-processed commands cached on a link between the host module and the slave module, and the time for the host module to send the other to-be-processed commands is earlier than the sending time of the to-be-processed command.

For example, the first signal may be generated by the bus interconnection module according to a host port number corresponding to the command to be processed, and sent to the host module corresponding to the host port number. The host port number may be a port number of a host module corresponding to the command to be processed, where the host port number is used to distinguish different host modules. Specifically, the bus interconnect module may generate the first signal in response to completing the pending command. Further, the bus interconnect module may send the first signal to a host module corresponding to a host port number in the command to be processed.

Optionally, when the bus interconnection module receives the command to be processed, a host port number corresponding to the command to be processed is determined. And carrying the host port number in the command to be processed to obtain the updated command to be processed. The method has the advantages that the host port number is carried in the command to be processed, so that the host module corresponding to the command to be processed can be rapidly and accurately determined when the subsequent command to be processed is processed, and subsequent command response and signal transmission are facilitated.

Similarly, the slave module may generate a second signal in the event that the slave module has responded to the target command. The host port number carried by the target command may then be parsed from the target command. And further, the second signal is sent to the host module corresponding to the host port number through the bus interconnection module, so that the host module can update the credit value to be used according to the second response signal, and can send a new command to be processed.

Optionally, the updating, by the host module, the current credit value to be used according to the first signal sent by the bus interconnection module specifically includes: when the host module only receives the first signal, the host module obtains the updated credit value to be used by subtracting one from the current credit value to be used.

In other words, the host module obtains the updated credit value to be used after subtracting one from the credit value to be used if the bus interconnection module is detected to have received the command to be processed and the second signal indicating that the slave module has responded to the target command is not received.

Specifically, the mode of detecting whether the bus interconnection module receives the command to be processed by the host module may be active monitoring or passive acquisition. The active monitoring mode may be that the host module monitors the bus interconnection module through a preset monitor, and determines whether the bus interconnection module receives a command to be processed. The passive acquisition mode may be that when the bus interconnection module receives a command to be processed, the bus interconnection module sends a message to a host module corresponding to the command to be processed, so as to inform the host module that the command to be processed has been received. Of course, the host module may also use other manners to detect whether the bus interconnect module receives the pending command, and the specific manner of use is not specifically limited in this embodiment. Under the condition that the host module detects that the bus interconnection module receives the command to be processed, the credit value to be used of the host module can be reduced, so that the host module is prevented from sending excessive commands to be processed subsequently.

For example, the credit value to be used is 2, and when the host module sends a command to be processed to the bus interconnection module and determines that the bus interconnection module receives the command to be processed, the credit value to be used of the host module may be 2-1, i.e. 1, and the credit value to be used is updated to be 1. At this time, if the command sending condition is that the credit value to be used is greater than zero, the host module may send a new command to be processed to the bus interconnection module.

Optionally, the updating, by the host module, the current credit value to be used according to the second signal sent by the slave module specifically includes: when the host module only receives the second signal, the host module adds one to the current credit value to be used to obtain the updated credit value to be used.

In other words, the host module adds one to the credit value to be used after the update in case that the slave module has responded to the target command and does not receive the first signal indicating that the bus interconnect module has responded to the pending command.

It may be understood that if no other command to be processed exists on the cache link, the target command is a command to be processed, and if other command to be processed exists on the cache link, the target command is other command to be processed, where the processing order of the other command to be processed may be determined by the design of the cache link, and in this embodiment, the specific limitation is not made. Typically, the order of processing of the other pending commands may be determined based on the time at which the host module sent each of the other pending commands. The cache link may be a data structure, such as a cache queue or the like, for storing cached pending commands.

Illustratively, the slave module invokes and responds to the target command from the cache link while in the idle state. The idle state refers to a state in which the slave module can respond to the target command. If the slave module cannot respond to the target command, the slave module can determine that the state is a busy state. It should be noted that, when the slave module responds to the processing to complete a pending command, the slave module may transition from the busy state to the idle state, and when the slave module starts to process a new pending command, the slave module may transition from the idle state to the busy state.

Specifically, the slave module may determine that the slave module is capable of responding to the target command in the cache link when in the idle state. At this time, the target command may be fetched according to the input/output logic of the cache link, and the fetched target command may be responded.

It should be noted that, the slave module may buffer a plurality of tasks to be processed, the number of buffered tasks to be processed may be recorded by commanding the buffer number, and the tasks to be processed may be buffered by the buffer link, so as to queue and manage the plurality of tasks to be processed buffered in the slave module.

Specifically, the mode of the host module for detecting whether the slave module responds to the target command may be active monitoring or passive acquisition. For example, a response port may be configured on the slave module, and in the case that the slave module responds to the target command, the response port is enabled, and when the master module detects that the response port is enabled, the slave module is determined to respond to the target command. Of course, the master module may also use other ways to detect whether the slave module responds to the target command, and the specific way of use is not specifically limited in this embodiment. The host module indicates that corresponding processing is performed on the target command when detecting that the slave module responds to the target command, and in this case, the credit value to be used of the host module can be increased, so that the host module has more credit values to be used to send the command to be processed.

For example, if the credit value to be used is 0 and the command sending condition is that the credit value to be used is greater than 0, the host module cannot continue to send a new command to be processed to the bus interconnection module, and the host module needs to wait for the credit value to be used to update to a value greater than 0 before continuing to send the command to be processed. If the host module determines that the slave module has responded to the target command, the credit value to be used of the host module may be updated to 0+1, i.e., 1. At this time, the host module may send a new pending command to the bus interconnect module.

It should be noted that, since one slave module may correspond to a plurality of host modules, when receiving a command to be processed, the response and the processing may not be directly performed, and therefore, a buffer link is set on the slave module to buffer the command to be processed, so as to facilitate subsequent sequential processing. When the slave module receives the command to be processed, the command to be processed still occupies the cache of the slave module and is not processed yet. The slave module responds to the target command, namely, the slave module finishes processing the target command, the processed target command does not occupy the buffer of the slave module any more, and at the moment, the credit value to be processed of the host module can be correspondingly updated. By the method, the problem of overflow of the to-be-processed command stored in the cache of the slave module can be avoided, and the effectiveness of command processing is improved.

Optionally, the updating, by the host module, the current credit value to be used according to the first signal sent by the bus interconnection module and the second signal sent by the slave module specifically includes: and when the host module receives the first signal and the second signal simultaneously, the current credit value to be used is used as the updated value to be used.

According to the technical scheme, under the condition that the credit value to be used of the host module meets the command sending condition, the host module sends a command to be processed to the bus interconnection module, so that the command to be processed is sent to the slave module through the bus interconnection module, and the sending of the command to be processed can be determined through the credit value to be used of the host module; the host module receives and updates the current credit value to be used according to the first signal sent by the bus interconnection module and/or the second signal sent by the slave module, wherein the first signal is used for indicating that the bus interconnection module has responded to the command to be processed, the second signal is used for indicating that the slave module has responded to the command to be processed or other commands to be processed which are cached on a link between the host module and the slave module and whose sending time is earlier than the command to be processed, the current credit value to be used of the host module can be updated according to the response states of the bus interconnection module and the slave module, the problem of command overflow in the slave module caused by the fact that the number of the commands to be processed sent by the host module and the number of the commands to be processed cached on the link cannot be monitored is solved, the technical effects of effectively reducing labor cost and time cost, improving iteration efficiency and precisely controlling the command sending number of the host module are achieved.

On the basis of the above technical solution, in order to avoid the error of cache overflow caused by too many to-be-processed commands cached in the slave module, the function of the large-scale digital chip is affected, and optionally, the command processing method further includes: and the host module receives the back pressure signal sent by the slave module, and responds to the back pressure signal, the host module stops sending the command to be processed. To regulate the pending command sent by the host module via the backpressure signal. In embodiments of the invention, the backpressure signal may be generated by the slave module. In particular, the backpressure signal may be generated by the slave module if the total number of target commands corresponding to the slave module reaches a preset number. Therefore, linkage between the host module and the slave module is realized, so that the host module can respond to the processing requirement of the host module in time, and overflow can be cached in an effective mode.

Example two

Fig. 2 is a schematic structural diagram of a command processing device according to a fourth embodiment of the present invention. As shown in fig. 2, the command processing device is configured in a host module. Specifically, the command processing apparatus includes: a credit value determining unit 210, a transmitting unit 220, a receiving unit 230, and a credit value updating unit 240.

Wherein, the credit value determining unit 210 is configured to determine that the credit value to be used currently satisfies the command sending condition; a sending unit 220, configured to send a command to be processed if the current credit value to be used meets a command sending condition; a receiving unit 230, configured to receive a first signal sent by the bus interconnection module and/or a second signal sent by the slave module; and a credit value updating unit 240, configured to update the currently-used credit value according to the first signal and/or the second signal, where the first signal is used to indicate that the bus interconnection module has responded to the pending command, and the second signal is used to indicate that the slave module has responded to a target command, where the target command is the pending command or another pending command buffered on a link between the master module and the slave module, and a time when the master module transmits the other pending command is earlier than a transmission time of the pending command.

Optionally, the credit value updating unit is specifically configured to:

Optionally, the command processing apparatus further includes:

and the back pressure signal response unit is used for receiving the back pressure signal sent by the slave module, and responding to the back pressure signal, the host module stops sending the command to be processed.

The command processing device provided by the embodiment of the invention can execute the command processing method provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of executing the command processing method.

Example III

Fig. 3 is a schematic diagram of a command processing system according to a fourth embodiment of the present invention. As shown in fig. 3, the system includes at least one host module 310, a bus interconnect module 320, and a slave module 330, the host module 310 being communicatively coupled to the bus interconnect module 320, the bus interconnect module 320 being communicatively coupled to the slave module 330; wherein, the host module 310 is configured to:

in the case that the current credit value to be used of the host module 310 satisfies the command transmission condition, the host module 310 transmits a command to be processed to the bus interconnection module 320 to transmit the command to be processed to the slave module 330 through the bus interconnection module 320;

the host module 310 receives and updates the current credit value to be used according to a first signal sent by the bus interconnection module 320 and/or a second signal sent by the slave module 330, where the first signal is used to indicate that the bus interconnection module 320 has responded to the pending command, and the second signal is used to indicate that the slave module 330 has responded to a target command, where the target command is the pending command or another pending command buffered on a link between the host module 310 and the slave module 330, and a time when the host module 310 sends the other pending command is earlier than a sending time of the pending command.

Optionally, the slave module 330 is configured to: in a case that the total number of the target commands that the slave module 330 does not respond to reaches a preset number, a back pressure signal is generated and sent to the host module 310 corresponding to the slave module 330, where the back pressure signal is used to instruct the host module 310 to stop sending the pending command to the bus interconnection module 320.

Wherein the total number of target commands that the slave module does not respond to includes the pending commands that the slave module has received but does not respond to and other pending commands that exist on the cache link.

The preset number may be a preset value for triggering generation and transmission of the back pressure signal. In the embodiment of the present invention, the preset number may be determined according to a difference between the command receiving upper limit of the slave module and the sum of the credit upper limits in all the corresponding host modules. Specifically, the preset number may be less than or equal to a difference value of the command reception upper limit of the slave module and a sum of credit value upper limits in all the corresponding master modules. The upper command receiving limit is understood to be the maximum number of commands to be processed that can be received by the slave module.

Illustratively, assume that the sum of the upper credit limits of all the host modules corresponding to the slave modules is 10. The maximum number of commands to be processed that can be received by the slave module is 100, and at this time, the preset number may take a value less than or equal to 90.

Specifically, when the total number of the target commands that are not responded by the slave module reaches the preset number, the slave module indicates that the received but not responded pending command and the buffered pending command on the link reach the upper limit of the reception of the slave module, and the slave module can generate a back pressure signal and send the back pressure signal to each host module in communication with the slave module, so that the host module stops sending the pending command to the bus interconnection module in response to the back pressure signal.

Optionally, the host module is specifically configured to:

Optionally, the host module is further configured to:

and receiving a back pressure signal sent by the slave module, and responding to the back pressure signal, stopping sending a command to be processed by the host module.

The command processing system provided by the embodiment of the invention can execute the command processing method provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of executing the command processing method.

Fig. 4 is a schematic structural diagram of an example architecture of a command processing system according to a third embodiment of the present invention. As shown in fig. 4, masterA, masterB and MasterC are both host modules, slave is a Slave module, and intersonenect 1 and intersonenect 2 are bus Interconnect modules. Pipe buffer represents a snapshot module command cache. Crodit_ctrl represents the Credit management module internally set by the Master module, crodit_ack represents the Credit response module added at the port of the Slave module. The perfbuffer represents a pending command.

Each Master module is pre-assigned a certain number of credits (i.e., an upper credit value limit) according to the demand of each Master module for command concurrency capability. For example: the Master module has less concurrency capability (e.g., less than 4), then one credit is allocated, otherwise two credits are allocated.

A credit management module may be disposed in each Master module, and the credit management module is configured to maintain a credit counter, where an initial value of the credit counter is the maximum credit value (upper credit limit) pre-allocated. Only when the credit value to be used at the current time of the Master meets the command sending condition (such as greater than 0), the Master module can send out the command to be processed, otherwise, the credit value to be used needs to be sent out after being updated to a value greater than 0.

After the Master module sends out the command to be processed, if the command to be processed is successfully responded by the intersonect module, the intersonect module generates a first signal and sends the first signal to the corresponding Master module, and at this time, the credit value to be used of the credit counter in the Master module is reduced by 1.

The to-be-processed command sent by the Master module can reach the Slave module through the multi-stage intersonect module, and each stage of intersonect module can carry the port number of the Master to the sent to-be-processed command when forwarding the to-be-processed command.

A credit response module can be added at the port of the Slave module and is used for monitoring the response condition of the Slave module to the command to be processed, when the command to be processed is responded, the Slave module can generate a second signal and send the second signal to the Interconnect module, the port number of the Master carried by the command to be processed can be used for identifying the Master module from which the command to be processed is responded, and then the second signal corresponding to the command to be processed is fed back to the corresponding Master.

Optionally, the credit response module may set an interface signal for transmitting a command response for each Master module, and when a to-be-processed command of a certain Master module is responded by the Slave module, the interface signal corresponding to the Master module is valid. When the credit_ctrl logic of the Master module sees that the corresponding interface signal is valid, the Credit value is increased by 1, which represents that the Master module has arrived at the Slave module and the pending command has responded, and is not cached in the snapshot module or the intersonenect on the link.

Further, the effective waterline configuration of the interface back pressure signal of the Slave module counts the maximum number of the cache commands, namely the sum of the received commands in the Slave module and the maximum number of the commands which can be cached on the link, and after the effective waterline configuration reaches the waterline, the back pressure signal logic is pulled up. For example: the sum of credits of all Master modules is 10, and the maximum number of pending commands that can be received by the Slave module is 100, then after 90 (100-10) commands have been received inside the Slave module, the Slave module pulls up the backpressure signal. Therefore, the number of commands sent to the Slave module by the Master module can be guaranteed, and the number of maximum commands receivable by the Slave is not exceeded, so that the functional correctness of the Slave is guaranteed.

According to the technical scheme, the logic and the interface of the bus interconnection module and the slave module are not required to be additionally changed, the credit management module is arranged in the host module, the credit response module is arranged in the slave module, the maximum number of commands which can be cached on a link from the host module to the slave module is accurately predicted, the counter-pressure waterline of the slave module is configured to avoid functional errors caused by command removal of the slave module, and the development cost of a large-scale digital chip is reduced.

Example five

Fig. 5 shows a schematic diagram of the structure of an electronic device 10 that may be used to implement an embodiment of the invention. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. Electronic equipment may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein.

As shown in fig. 5, the electronic device 10 includes at least one processor 11, and a memory, such as a Read Only Memory (ROM) 12, a Random Access Memory (RAM) 13, etc., communicatively connected to the at least one processor 11, in which the memory stores a computer program executable by the at least one processor, and the processor 11 may perform various appropriate actions and processes according to the computer program stored in the Read Only Memory (ROM) 12 or the computer program loaded from the storage unit 18 into the Random Access Memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 may also be stored. The processor 11, the ROM 12 and the RAM 13 are connected to each other via a bus 14. An input/output (I/O) interface 15 is also connected to bus 14.

Various components in the electronic device 10 are connected to the I/O interface 15, including: an input unit 16 such as a keyboard, a mouse, etc.; an output unit 17 such as various types of displays, speakers, and the like; a storage unit 18 such as a magnetic disk, an optical disk, or the like; and a communication unit 19 such as a network card, modem, wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunication networks.

The processor 11 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various processors running machine learning model algorithms, digital Signal Processors (DSPs), and any suitable processor, controller, microcontroller, etc. The processor 11 performs the respective methods and processes described above, for example, a command processing method.

In some embodiments, the command processing method may be implemented as a computer program tangibly embodied on a computer-readable storage medium, such as the storage unit 18. In some embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 10 via the ROM 12 and/or the communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the command processing method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to perform the command processing method in any other suitable way (e.g., by means of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.

A computer program for carrying out methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be implemented. The computer program may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) through which a user can provide input to the electronic device. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), blockchain networks, and the internet.

The computing system may include clients and servers. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical hosts and VPS service are overcome.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.

The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.

Claims

1. A method of command processing, comprising:

2. The method of claim 1, wherein the updating, by the host module, the current credit value to be used according to the first signal sent by the bus interconnect module specifically comprises:

3. The method according to claim 1, wherein the updating the current credit value to be used by the host module according to the second signal sent by the slave module specifically comprises:

4. The method of claim 1, wherein the updating, by the host module, the current credit value to be used according to the first signal sent by the bus interconnect module and the second signal sent by the slave module specifically includes:

5. The method as recited in claim 1, further comprising:

6. A command processing apparatus, configured in a host module, comprising:

7. The apparatus according to claim 6, wherein the credit value updating unit is specifically configured to:

8. The apparatus according to claim 6, wherein the credit value updating unit is specifically configured to:

9. The apparatus according to claim 6, wherein the credit value updating unit is specifically configured to:

10. A command processing system, comprising: the system comprises at least one host module, a bus interconnection module and a slave module, wherein the host module is in communication connection with the bus interconnection module, and the bus interconnection module is in communication connection with the slave module; wherein, the host module is used for:

11. The processing system of claim 10, wherein the slave module is configured to:

and generating a back pressure signal and sending the back pressure signal to a host module corresponding to the slave module under the condition that the total number of the target commands which are not responded by the slave module reaches a preset number, wherein the back pressure signal is used for indicating the host module to stop sending the commands to be processed to the bus interconnection module.