CN115168140A - Port state supervision method and device and port state supervision system - Google Patents

Abstract

The invention discloses a port state supervision method, a port state supervision device and a port state supervision system. The method is applied to a programmable logic device and comprises the following steps: and receiving a pin state signal sent by the PHY chip, and reporting an interrupt signal to the processing module when determining that the port state of at least one PHY chip changes according to the pin state signal so as to trigger the processing module to supervise the port state of each PHY chip through a mapping relation between a port state value stored in a preset register address and each PHY chip. According to the technical scheme, the port states of any number of PHY chips can be supervised through the programmable logic device, expansion of the number of the PHY chips is supported, and the programmable logic device triggers the processing module to supervise the port states of the PHY chips through reporting the interrupt signal, so that frequent polling of the processing module on the port states can be avoided, resource occupation is reduced, and port supervision efficiency is improved.

Description

Port state supervision method and device and port state supervision system

Technical Field

The embodiment of the invention relates to the technical field of network communication, in particular to a port state supervision method, a port state supervision device and a port state supervision system.

Background

With the rapid development of internet technology, the bandwidth requirement is higher and higher, and the number of ports in the ethernet switch is continuously increased, so that the occupation ratio is larger and larger. For the ethernet switch, it is necessary to quickly determine the port status to display in the print information of the management serial port or the management network port. The current method for determining the port status is that a Central Processing Unit (CPU) polls or a Physical layer (PHY) chip reports an interrupt to the CPU. As shown in fig. 1, for the polling method, the switch chip may query the port state of the PHY chip, and specifically, may query the port state through the switch chip. The CPU continuously performs polling detection to acquire the state of each port and prints through the serial port. For the interrupt mode, when the port state of the PHY chip changes, the port state can be actively reported to the CPU, and the CPU inquires the port state through the PHY chip after detecting the interrupt.

In practical application, one or more switching chips can be externally connected to one CPU, and a plurality of PHY chips can be externally connected to one switching chip. For the polling mode, if the frequency of the port state change is low, frequent polling is a great waste to the resources of the CPU; for the interrupt mode, the number of pins for receiving interrupt reports by the CPU is limited, so that the monitoring number of PHY chips is limited to a large extent.

Disclosure of Invention

The invention provides a port state supervision method, a port state supervision device and a port state supervision system, which are used for realizing the supervision of the port states of a plurality of PHY chips, supporting the expansion of the number of the PHY chips, reducing the resource occupation and improving the efficiency of the port supervision.

In a first aspect, an embodiment of the present invention provides a method for monitoring a port status, where the method is applied to a Programmable Logic Device (PLD), the PLD is connected to a processing module, and the PLD is further connected to at least one PHY chip; the method comprises the following steps:

and receiving a pin state signal sent by the PHY chip, and reporting an interrupt signal to the processing module when determining that the port state of at least one PHY chip changes according to the pin state signal so as to trigger the processing module to supervise the port state of each PHY chip through a mapping relation between a port state value stored in a preset register address and each PHY chip, wherein the port state value corresponding to each PHY chip is updated in real time according to the pin state signal.

In a second aspect, an embodiment of the present invention provides a method for monitoring a port state, where the method is applied to a processing module, the processing module is connected to a programmable logic device, and the programmable logic device is further connected to at least one PHY chip; the method comprises the following steps:

receiving an interrupt signal reported by a programmable logic device when determining that the port state of at least one PHY chip changes according to a received pin state signal sent by the PHY chip;

and in response to the interrupt signal, monitoring the port state of each PHY chip through the mapping relation between the port state value stored in the address of the preset register and each PHY chip.

In a third aspect, an embodiment of the present invention provides a port status monitoring apparatus, including:

the receiving module is used for receiving the pin state signal sent by the PHY chip;

and the reporting module is used for reporting an interrupt signal to the processing module when the port state of at least one PHY chip is determined to be changed according to the pin state signal so as to trigger the processing module to supervise the port state of each PHY chip through the mapping relation between the port state value stored in the address of a preset register and each PHY chip, wherein the port state value corresponding to each PHY chip is updated in real time according to the pin state signal.

In a fourth aspect, an embodiment of the present invention provides a port status monitoring apparatus, including:

the receiving module is used for receiving an interrupt signal reported by the programmable logic device when the port state of at least one PHY chip is determined to change according to the received pin state signal sent by the PHY chip;

the supervision module is used for responding to the interrupt signal and supervising the port state of each PHY chip through the mapping relation between the port state value stored in the preset register address and each PHY chip; and updating the port state value corresponding to each PHY chip in real time according to the pin state signal.

In a fifth aspect, an embodiment of the present invention provides a port status monitoring system, including:

the system comprises a programmable logic device, a processing module and at least one PHY chip; the processing module is connected with the programmable logic device; different ports of the programmable logic device are respectively connected with the PHY chips;

the port state policing system is configured to perform the port state policing method of the first aspect or the second aspect.

The embodiment of the invention provides a port state monitoring method, a port state monitoring device and a port state monitoring system. The method is applied to a programmable logic device, the programmable logic device is connected with a processing module, and the programmable logic device is also connected with at least one PHY chip, and the method comprises the following steps: and receiving a pin state signal sent by the PHY chip, and reporting an interrupt signal to the processing module when determining that the port state of at least one PHY chip changes according to the pin state signal so as to trigger the processing module to supervise the port state of each PHY chip through a mapping relation between a port state value stored in a preset register address and each PHY chip, wherein the port state value corresponding to each PHY chip is updated in real time according to the pin state signal. According to the technical scheme, the port states of any number of PHY chips can be supervised through the programmable logic device, the number of the PHY chips is not limited by the number of pins of the processing module, the expansion of the number of the PHY chips is supported, and the programmable logic device triggers the processing module to supervise the port states of the PHY chips through reporting the interrupt signals, so that the processing module can be prevented from polling the port states frequently, the resource occupation is reduced, and the port supervision efficiency is improved.

Drawings

The above and other features, advantages and aspects of various embodiments of the present disclosure will become more apparent by referring to the following detailed description when taken in conjunction with the accompanying drawings. Throughout the drawings, the same or similar reference numbers refer to the same or similar elements. It should be understood that the drawings are schematic and that elements and features are not necessarily drawn to scale.

FIG. 1 is a diagram illustrating a prior art query port status;

fig. 2 is a flowchart of a method for monitoring a port status according to an embodiment of the present invention;

fig. 3 is a flowchart of a port status monitoring method according to a second embodiment of the present invention;

fig. 4 is a schematic structural diagram of a port status monitoring apparatus according to a third embodiment of the present invention;

fig. 5 is a schematic structural diagram of a port status monitoring apparatus according to a fourth embodiment of the present invention;

fig. 6 is a schematic structural diagram of a programmable logic device according to a fifth embodiment of the present invention;

fig. 7 is a schematic structural diagram of a processing module according to a sixth embodiment of the present invention;

fig. 8 is a schematic structural diagram of a port status monitoring system according to a seventh embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. In addition, the embodiments and features of the embodiments in the present invention may be combined with each other without conflict. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the steps as a sequential process, many of the steps can be performed in parallel, concurrently, or simultaneously. In addition, the order of the steps may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figure. The processes may correspond to methods, functions, procedures, subroutines, and the like.

It should be noted that the terms "first", "second", and the like in the embodiments of the present invention are only used for distinguishing different apparatuses, modules, units, or other objects, and are not used for limiting the order or interdependence relationship of the functions performed by these apparatuses, modules, units, or other objects.

Example one

Fig. 2 is a flowchart of a method for monitoring port states according to an embodiment of the present invention, which is applicable to monitoring port states of any number of PHY chips. In particular, the port state supervision method may be executed by a port state supervision apparatus, which may be implemented in software and/or hardware and integrated in a programmable logic device.

In this embodiment, the programmable logic device is connected to the processing module and further connected to at least one PHY chip. The processing module may be a processor, such as a CPU, of the ethernet switch. The processing module 100 and the programmable logic device may be connected by a Serial Peripheral Interface (SPI) bus.

As shown in fig. 2, the method specifically includes the following steps:

and S110, receiving the pin state signal sent by the PHY chip.

In this embodiment, the Programmable Logic Device may be a Complex Programmable Logic Device (CPLD). In this embodiment, the ports of the programmable logic device, mainly Input/Output (I/O) ports, may be connected to any number of PHY chips. Each PHY chip may be connected to a port of the programmable logic device through one interrupt pin (pin). In an initial situation (for example, after the programmable logic device and each PHY chip are powered on, or when the port state of each PHY chip starts to be monitored), the pin state of the interrupt pin of the PHY chip is a default value, for example, 1, and it can also be understood that the pin state signal defaults to a high level signal; if the port state of the PHY chip changes, and the pin state of the interrupt pin changes accordingly, for example, to 0, it can also be understood that the pin state signal changes to a low level signal, in which case the PHY chip triggers an interrupt. The programmable logic device may receive pin status signals of each PHY chip through the port.

And S120, reporting an interrupt signal to the processing module when determining that the port state of at least one PHY chip changes according to the pin state signal so as to trigger the processing module to monitor the port state of each PHY chip through a mapping relation between a port state value stored in a preset register address and each PHY chip.

Specifically, if the port state of the PHY chip changes (i.e., changes from the initial operating state to the non-emergency operating state, which may be, for example, a normal state to an abnormal state, or an abnormal state to a normal state, or a connection state to a sleep state, etc.), the pin status signal of the PHY chip is no longer the default value. The programmable logic device receives the pin state signal of the PHY chip, and when the pin state signal of the PHY chip is found not to be a default value, the programmable logic device can determine that the port state of the PHY chip changes, and at the moment, the programmable logic device can report an interrupt signal to the processing module to indicate that the port state of the PHY chip changes, so that the processing module is triggered to supervise the port state of each PHY chip.

The preset register address can be used for storing port state values of each PHY chip, and the port states mainly comprise initial working states and non-initial working states. The port state of each PHY chip may be recorded by different port state values of different bits, and specifically, a first value may be used to indicate that the corresponding PHY chip is in an initial working state, and a second value may be used to indicate that the corresponding PHY chip is in a non-initial working state.

And updating the port state value corresponding to each PHY chip in real time according to the pin state signal. Specifically, when the programmable logic device receives the pin state signal and determines that the port state of the PHY chip changes, the programmable logic device updates the port state value of the corresponding PHY chip in the preset register address in real time, so that after the processing module receives the interrupt signal, the processing module can access the preset register address of the programmable logic device to query the latest port state value of each PHY chip, thereby determining which PHY chip has the port state change.

In the port state monitoring method provided in the embodiment of the present invention, port states of any number of PHY chips can be stored and updated through a programmable logic device, and the number of PHY chips is not limited by the number of pins of a processing module, so that the number of PHY chips is expanded; and the programmable logic device triggers the processing module to supervise the real-time port state of the PHY chip by reporting the interrupt signal, so that frequent polling of the processing module to the port state can be avoided, the resource occupation is reduced, and the port supervision efficiency is improved.

Optionally, reporting an interrupt signal to the processing module when it is determined that the port state of the at least one PHY chip changes according to the pin state signal, where the reporting an interrupt signal includes: carrying out logic AND operation on the received pin state signal to obtain an operation result; and determining whether the port state of the PHY chip changes according to the operation result, and reporting an interrupt signal to the processing module when the port state of any PHY chip changes.

In this embodiment, for a PHY chip whose port state is not changed, a pin state signal generated by a broken pin should be a default value in an initial condition, and may specifically be 1 (high level signal); for a PHY chip with a port status changing, the pin status signal generated by the broken pin is no longer a default value, and may specifically be 0 (low level signal). The programmable logic device can perform logic and operation on the pin state signals of each PHY chip, the operation result is a default value under the condition that the port state of each PHY chip is in an initial working state, and the logic and operation result of the pin state signals of each PHY chip is not the default value as long as the port state of one PHY chip is changed, so that whether the port state of the PHY chip is changed or not can be determined. On this basis, as long as the port state of one PHY chip changes, the programmable logic device reports an interrupt signal to the processing module to trigger the processing module to monitor the port state of the PHY chip.

By carrying out logic and operation on the received pin state signals, on one hand, whether PHY chips with changed port states exist can be determined in time, on the other hand, when a plurality of PHY chips with changed port states exist within a preset time, the pin state signals of the PHY chips with changed port states can be integrated into an interrupt signal and are uniformly reported to the processing module through an interrupt pin, and the processing module can rapidly inquire the port states of the PHY chips, so that the times of reporting the interrupt signal and inquiring the port states by the processing module are reduced, the resource occupation of the processing module is further reduced, and the supervision efficiency is improved.

Optionally, the mapping relationship includes: presetting a port state value of a single bit in a register address to correspond to a port state of a PHY chip; under the condition that the port state value of any bit is a first value, the port state of the PHY chip corresponding to the bit is an initial working state; and under the condition that the port state value of any bit is the second value, the port state of the PHY chip corresponding to the bit is in a non-initial working state.

In this embodiment, the programmable logic device stores the port state of each PHY chip in a preset register address, different bits in the preset register address correspond to each PHY chip one to one, and different port state values of each bit correspond to different port states of the corresponding PHY chip. The processing module is connected with the programmable logic device through an SPI bus, and the port state of each PHY chip is stored into a preset register address to be inquired by the processing module. The preset register address for storing the port state supports the SPI protocol, namely, the processing module is supported to access through an SPI bus.

The port state value of each bit in the preset register address and the port state of each PHY chip have a one-to-one correspondence, and the different port state values of each bit represent different port states of the corresponding PHY chip. For example, the preset register address is respectively corresponding to the first PHY chip to the last PHY chip from low order to high order. On this basis, when receiving the interrupt signal, the processing module may determine the port state of the corresponding PHY chip according to the port state value of each bit in the preset register address by accessing the preset register address. For example, the preset register address is 0x11, the default value is 0xff, that is, the corresponding eight bits are 11111111, respectively, which indicates that the corresponding eight PHY chips are all in the initial working state (where the first value is set to 1, which indicates that the port state of the corresponding PHY chip is in the initial working state, and the second value is set to 0, which indicates that the port state of the corresponding PHY chip is not in the initial working state); for another example, querying the 0x11 address to have a value of 0xfc, i.e. the corresponding eight bits are 11111100, respectively, indicates that the port states of the first and second PHY chips are not in the initial operating state, i.e. the port state is changed.

Optionally, the method further includes: and updating the port state value of a bit corresponding to the PHY chip with the changed port state in the preset register address according to the pin state signal.

Specifically, the programmable logic device determines the PHY chips with changed port states according to the pin state signals of the PHY chips, and updates the port state values of the bits corresponding to the PHY chips with changed port states in real time according to the mapping relationship between the port state values stored in the preset register addresses and the PHY chips.

Optionally, updating, according to the pin status signal, a port status value of a bit corresponding to the PHY chip whose port status changes in the preset register address, includes: when the pin state signal of any PHY chip is not a default value, determining that the PHY chip is the PHY chip with the changed port state; and updating the port state value of the bit corresponding to the PHY chip with the changed port state from a first value to a second value, wherein the default value is the value corresponding to the pin state signal under the condition that the port state of each PHY chip is in the initial working state.

Specifically, the programmable logic device updates the port state value of the bit of the corresponding PHY chip in the preset register address according to whether the pin state signal of each PHY chip is a default value or a non-default value. It should be noted that the default value refers to a value corresponding to the pin status signal when the port status of each PHY chip is in the initial operating state, that is, when the method is executed, no matter what the port status of each PHY chip is (such as a connection status, a disconnection status, a normal status, an abnormal status, a sleep status, or the like), the port status of each PHY chip is considered to be in the initial operating state, and the pin status signal of each PHY chip is the default value. When a pin state signal of a PHY chip is changed into a non-default value, the port state of the PHY chip is changed, and the programmable logic device updates the port state value of a corresponding bit of the PHY chip from a first value to a second value; if the pin state signal of one PHY chip is always the default value, it indicates that the port state of the PHY chip has not changed, and the programmable logic device does not need to update the port state value of the corresponding bit of the PHY chip. On the basis, the programmable logic device can accurately record the real-time port state according to the pin state signal for the monitoring of the processing module.

Optionally, the address of the preset register is determined according to the number of the PHY chips; wherein a single register address is used to store the port status of up to eight PHY chips.

In this embodiment, when the number of PHY chips does not exceed eight, the port state of each PHY chip may be recorded by using a single register address; when the number of PHY chips exceeds eight, the register addresses can be increased appropriately until the register addresses can satisfy the number of PHY chips, wherein each register address has eight bits and can be used for recording the port states of 1-8 PHY chips. The bits used for different register addresses may be the same or different. For example, when there are 20 PHY chips, register address 1 may be used to record the port status of PHY chips 1-8, register address 2 may be used to record the port status of PHY chips 9-16, and register address 3 may be used to record the port status of PHY chips 17-20. On the basis, the number of the PHY chips can be expanded arbitrarily by flexibly increasing and deleting the number of the register addresses and configuring the mapping relation between the bits in each register address and the PHY chips.

According to the port state monitoring method, the pin state signals of all the PHY chips are subjected to logic and operation, so that an interrupt signal can be integrated and reported to the processing module when the port state of at least one PHY chip is changed, the frequency of inquiring the port state by the processing module can be reduced, the resource occupation of the processing module is further reduced, and the monitoring efficiency is improved; the port state of each PHY chip is stored into a preset register address, and the support processing module inquires the port state of each PHY chip based on the SPI bus, so that the comprehensive supervision of each PHY chip is realized; in addition, the address of the memory can be expanded according to the number of the PHY chips, so that the problem of inflexible use caused by insufficient interrupt pins of the processing module is solved, and the problem of resource waste of the processing module is also solved.

Example two

Fig. 3 is a flowchart of a port status monitoring method according to a second embodiment of the present invention, which is applicable to monitoring port statuses of multiple PHY chips. In particular, the port status supervision method may be performed by a port status supervision apparatus, which may be implemented in software and/or hardware and integrated in the processing module. The processing module is connected with the programmable logic device, and the programmable logic device is also connected with at least one PHY chip. It should be noted that technical details that are not described in detail in the present embodiment may be referred to any of the above embodiments.

As shown in fig. 3, the method specifically includes the following steps:

s210, receiving an interrupt signal reported by the programmable logic device when determining that the port state of at least one PHY chip changes according to the received pin state signal sent by the PHY chip.

The programmable logic device can determine whether the port state of the PHY chip changes or not according to the pin state signals of the PHY chips, and reports the interrupt signal to the processing module when the port state of any one or more PHY chips changes.

S220, responding to the interrupt signal, and monitoring the port state of each PHY chip through the mapping relation between the port state value stored in the address of the preset register and each PHY chip.

In this embodiment, after receiving the interrupt signal reported by the programmable logic device, the processing module may query the port state value of the bit corresponding to each PHY chip stored in the preset register address of the programmable logic device, so as to determine whether the port state of each PHY chip is an initial working state or a non-initial working state, thereby implementing supervision on the port state of each PHY chip.

In the method for supervising the port state provided in the second embodiment of the present invention, by adding the programmable logic device between the processing module and the PHY chip, the port states of any number of PHY chips can be supervised, the number of PHY chips is supported to be expanded, and the processing module only needs to query the port state of the PHY chip when receiving an interrupt signal, so that the CPU resource occupation is reduced, and the port supervision efficiency is improved.

Optionally, the monitoring the port state of each PHY chip according to a mapping relationship between a port state value stored in a preset register address and each PHY chip includes:

inquiring the address of the preset register through an SPI bus;

if the port state value stored by a single bit in the preset register address is a first value, determining that the port state of the PHY chip corresponding to the bit is an initial working state;

and if the port state value stored by a single bit in the preset register address is a second value, determining that the port state of the PHY chip corresponding to the bit is changed from the initial working state to a non-initial working state.

The second embodiment of the present invention provides a method for monitoring a port state applied to a processing module, which belongs to the same inventive concept as the method for monitoring a port state applied to a programmable logic device provided in the foregoing embodiments, and has the same beneficial effects, and details of the technology that are not described in detail in this embodiment may be referred to any of the foregoing embodiments.

EXAMPLE III

Fig. 4 is a schematic structural diagram of a port status monitoring apparatus according to a second embodiment of the present invention. As shown in fig. 4, the port status monitoring apparatus includes:

a status signal receiving module 310, configured to receive a pin status signal sent by the PHY chip;

a reporting module 320, configured to report an interrupt signal to the processing module when it is determined that the port state of at least one PHY chip changes according to the pin state signal, so as to trigger the processing module to supervise the port state of each PHY chip through a mapping relationship between a port state value stored in a preset register address and each PHY chip, where the port state value corresponding to each PHY chip is updated in real time according to the pin state signal.

The port state monitoring device provided by the second embodiment of the invention can monitor the port states of a plurality of PHY chips, supports the expansion of the number of the PHY chips, and can avoid the frequent polling of the port states by the processing module, reduce the resource occupation and improve the port monitoring efficiency by triggering the processing module to monitor the port states of the PHY chips through reporting the interrupt signal by the programmable logic device.

On the basis of the above embodiment, the reporting module 320 includes:

the arithmetic unit is used for carrying out logic AND operation on the received pin state signal to obtain an operation result;

and the reporting unit is used for determining whether the port state of the PHY chip changes according to the operation result and reporting an interrupt signal to the processing module when the port state of any PHY chip changes.

On the basis of the above embodiment, the mapping relationship includes:

the port state value of a single bit in the preset register address corresponds to the port state of one PHY chip;

under the condition that the port state value of any bit is a first value, the port state of the PHY chip corresponding to the bit is an initial working state;

and under the condition that the port state value of any bit is the second value, the port state of the PHY chip corresponding to the bit is in a non-initial working state.

On the basis of the above embodiment, the apparatus further includes: and the updating module is used for updating the port state value of a bit corresponding to the PHY chip with the changed port state in the preset register address according to the pin state signal.

On the basis of the above embodiment, the update module is specifically configured to:

when a pin state signal of any PHY chip is a non-default value, determining that the PHY chip is a PHY chip with a changed port state; and updating the port state value of the bit corresponding to the PHY chip with the changed port state from a first value to a second value, wherein the default value is the value corresponding to the pin state signal when the port state of each PHY chip is in the initial working state.

The port state monitoring device provided by the third embodiment of the invention can be used for executing the port state monitoring method provided by any of the above embodiments, and has corresponding functions and beneficial effects. Technical details that are not elaborated in this embodiment may be referred to any of the embodiments described above.

Example four

Fig. 5 is a schematic structural diagram of a port status monitoring apparatus according to a fourth embodiment of the present invention. As shown in fig. 5, the port status supervision apparatus includes:

an interrupt signal receiving module 410, configured to receive an interrupt signal that is reported by a programmable logic device when determining that a port state of at least one PHY chip changes according to a received pin state signal sent by the PHY chip;

a supervision module 420, configured to supervise, in response to the interrupt signal, a port state of each PHY chip through a mapping relationship between a port state value stored in a preset register address and each PHY chip; and updating the port state value corresponding to each PHY chip in real time according to the pin state signal.

The port state monitoring device provided by the fourth embodiment of the invention can monitor the port states of any number of PHY chips, support the expansion of the number of PHY chips, and inquire the port state of the PHY chip when an interrupt signal is received, thereby reducing the occupation of CPU resources and improving the port monitoring efficiency.

On the basis of the above embodiment, the supervision module 420 includes:

the query unit is used for querying the address of the preset register through the SPI bus;

a state determination unit for

If the port state value stored by a single bit in the preset register address is a first value, determining that the port state of the PHY chip corresponding to the bit is an initial working state;

and if the port state value stored by a single bit in the preset register address is a second value, determining that the port state of the PHY chip corresponding to the bit is changed from an initial working state to a non-initial working state.

The port state monitoring device provided by the fourth embodiment of the present invention can be used for executing the port state monitoring method provided by any of the above embodiments, and has corresponding functions and beneficial effects.

EXAMPLE five

Fig. 6 is a schematic diagram of a hardware structure of a programmable logic device according to a fifth embodiment of the present invention. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein.

As shown in fig. 6, the programmable logic device 10 includes at least one processor 11, and a memory communicatively connected to the at least one processor 11, such as a Read Only Memory (ROM) 12, a Random Access Memory (RAM) 13, and the like, wherein the memory stores a computer program executable by the at least one processor, and the processor 11 can perform various suitable actions and processes according to the computer program stored in the Read Only Memory (ROM) 12 or the computer program loaded from a storage unit 18 into the Random Access Memory (RAM) 13. In the RAM 13, various programs and data necessary for the operation of the programmable logic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other via a bus 14. An input/output (I/O) interface 15 is also connected to bus 14.

A number of components in programmable logic device 10 are connected to I/O interface 15, including: an input unit 16 such as a keyboard, a mouse, or the like; an output unit 17 such as various types of displays, speakers, and the like; a storage unit 18 such as a magnetic disk, optical disk, or the like; and a communication unit 19 such as a network card, modem, wireless communication transceiver, etc. The communication unit 19 allows the programmable logic device 10 to exchange information/data with other devices via a computer network such as the internet and/or various telecommunication networks, wireless networks.

The processor 11 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various processors running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, or the like. The processor 11 performs the various methods and processes described above, such as the port state policing method.

In some embodiments, the port state policing method may be implemented as a computer program tangibly embodied in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and/or installed onto programmable logic device 10 via ROM 12 and/or communications unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to perform the port status policing method by any other suitable means (e.g., by means of firmware).

The programmable logic device provided by the fifth embodiment of the present invention and the method for supervising the port state provided by the foregoing embodiments belong to the same inventive concept, and have the same beneficial effects, and the technical details that are not described in detail in this embodiment may be referred to any of the foregoing embodiments.

EXAMPLE six

Fig. 7 is a schematic diagram of a hardware structure of a processing module according to a sixth embodiment of the present invention. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein.

As shown in fig. 7, the processing module 20 includes at least one processor 21, and a memory communicatively connected to the at least one processor 21, such as a Read Only Memory (ROM) 22, a Random Access Memory (RAM) 23, and the like, wherein the memory stores a computer program executable by the at least one processor, and the processor 21 can perform various suitable actions and processes according to the computer program stored in the Read Only Memory (ROM) 22 or the computer program loaded from the storage unit 28 into the Random Access Memory (RAM) 23. In the RAM 23, various programs and data necessary for the operation of the processing module 20 can also be stored. The processor 21, the ROM 22, and the RAM 23 are connected to each other via a bus 24. An input/output (I/O) interface 25 is also connected to bus 24.

A number of components in the processing module 20 are connected to the I/O interface 25, including: an input unit 26 such as a keyboard, a mouse, etc.; an output unit 27 such as various types of displays, speakers, and the like; a storage unit 28 such as a magnetic disk, optical disk, or the like; and a communication unit 29 such as a network card, modem, wireless communication transceiver, etc. The communication unit 29 allows the processing module 20 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunication, wireless networks.

The processor 21 may be any of various general purpose and/or special purpose processing components having processing and computing capabilities. Some examples of the processor 21 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various dedicated Artificial Intelligence (AI) computing chips, various processors running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, or the like. The processor 21 performs the various methods and processes described above, such as the port status policing method.

In some embodiments, the port state policing method may be implemented as a computer program tangibly embodied in a computer-readable storage medium, such as storage unit 28. In some embodiments, part or all of the computer program may be loaded and/or installed onto the processing module 20 via the ROM 22 and/or the communication unit 29. When the computer program is loaded into the RAM 23 and executed by the processor 21, one or more steps of the method described above may be performed. Alternatively, in other embodiments, the processor 21 may be configured to perform the port status policing method by any other suitable means (e.g., by means of firmware).

EXAMPLE seven

Fig. 8 is a schematic structural diagram of a port status monitoring system according to a seventh embodiment of the present invention. The present embodiment is applicable to the case of monitoring the port states of any number of PHY chips. As shown in fig. 8, the system includes: a processing module 100, a programmable logic device 200, and at least one PHY chip 300; the processing module 100 is connected with the programmable logic device 200; different ports of the programmable logic device 200 are respectively connected to each PHY chip 300, and the programmable logic device 200 is configured to receive a pin status signal sent by the PHY chips 300, and report an interrupt signal to the processing module 100 when it is determined that a port status of at least one PHY chip 300 changes according to the pin status signal, so as to trigger the processing module 100 to supervise the port status of each PHY chip 300 through a mapping relationship between a port status value stored in a preset register address and each PHY chip, where the port status value corresponding to each PHY chip is updated in real time according to the pin status signal.

The programmable logic device 200 is connected to one or more PHY chips, and the register of the programmable logic device 200 may be used to monitor and store the port state of each PHY chip 300, so as to record whether the port state of each PHY chip 300 changes. An interrupt may be triggered if there is a change in the port status of PHY chip 300.

The programmable logic device 200 may report an interrupt signal to the processing module 100 according to the port state of each PHY chip 300, and after receiving the interrupt signal, the processing module 100 may access the register of the programmable logic device 200 to query which PHY chip 300 has a port state that changes, thereby implementing supervision of the port state of each port.

The port state monitoring system of the embodiment can be connected with any number of PHY chips by additionally arranging the programmable logic device, and the number of the PHY chips is not limited by the number of pins of a CPU (central processing unit), so that the port states of any number of PHY chips are monitored, and the expansion of the number of the PHY chips is supported; in addition, the programmable logic device can report an interrupt signal to the processing module according to the monitored port state change of the PHY chip, and the processing module can inquire the port state of the PHY chip according to the interrupt signal without real-time inquiry and active polling, so that frequent or meaningless inquiry is avoided, the resource occupation is reduced, and the port supervision efficiency is improved.

The port state monitoring system provided by the seventh embodiment of the invention can be used for realizing the port state monitoring method provided by any embodiment, and has corresponding functions and beneficial effects. Technical details that are not elaborated in this embodiment may be referred to any of the embodiments described above.

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuitry, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), system on a chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, receiving data and instructions from, and transmitting data and instructions to, a storage system, at least one input device, and at least one output device.

A computer program for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be performed. A computer program can execute entirely on a machine, partly on a machine, as a stand-alone software package partly on a machine and partly on a remote machine or entirely on a remote machine or server.

In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. A computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on a programmable logic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which a user can provide input to the programmable logic device. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic, speech, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a back-end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), blockchain networks, and the internet.

The computing system may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical host and VPS service are overcome.

It should be understood that various forms of the flows shown above, reordering, adding or deleting steps, may be used. For example, the steps described in the present invention may be executed in parallel, sequentially, or in different orders, and are not limited herein as long as the desired results of the technical solution of the present invention can be achieved.

The above-described embodiments should not be construed as limiting the scope of the invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A port state supervision method is characterized by being applied to a programmable logic device, wherein the programmable logic device is connected with a processing module and is also connected with at least one PHY chip; the method comprises the following steps:

and receiving a pin state signal sent by the PHY chip, and reporting an interrupt signal to the processing module when determining that the port state of at least one PHY chip changes according to the pin state signal so as to trigger the processing module to supervise the port state of each PHY chip through a mapping relation between a port state value stored in a preset register address and each PHY chip, wherein the port state value corresponding to each PHY chip is updated in real time according to the pin state signal.

2. The method of claim 1, wherein reporting an interrupt signal to the processing module when it is determined that a port status of at least one of the PHY chips changes according to the pin status signal comprises:

carrying out logic AND operation on the received pin state signal to obtain an operation result;

and determining whether the port state of the PHY chip changes according to the operation result, and reporting an interrupt signal to the processing module when the port state of any PHY chip changes.

3. The method of claim 1, wherein the mapping comprises:

the port state value of a single bit in the preset register address corresponds to the port state of one PHY chip;

under the condition that the port state value of any bit is a first value, the port state of the PHY chip corresponding to the bit is an initial working state;

and under the condition that the port state value of any bit is the second value, the port state of the PHY chip corresponding to the bit is in a non-initial working state.

4. The method of claim 3, wherein before reporting an interrupt signal to the processing module when it is determined that the port status of at least one of the PHY chips changes according to the pin status signal, the method further comprises:

and updating the port state value of a bit corresponding to the PHY chip with the changed port state in the preset register address according to the pin state signal.

5. The method of claim 4, wherein updating the port state value of the bit corresponding to the PHY chip having the changed port state in the preset register address according to the pin state signal comprises:

when the pin state signal of any PHY chip is a non-default value, determining that the PHY chip is the PHY chip with a changed port state;

updating the port state value of the bit corresponding to the PHY chip with the changed port state from a first value to a second value;

the default value is a value corresponding to the pin status signal when the port status of each PHY chip is in an initial working state.

6. A port state supervision method is characterized by being applied to a processing module, wherein the processing module is connected with a programmable logic device, and the programmable logic device is also connected with at least one PHY chip; the method comprises the following steps:

receiving an interrupt signal reported by a programmable logic device when determining that the port state of at least one PHY chip changes according to a received pin state signal sent by the PHY chip;

and in response to the interrupt signal, monitoring the port state of each PHY chip through the mapping relation between the port state value stored in the address of the preset register and each PHY chip.

7. The method of claim 6, wherein monitoring the port status of each PHY chip according to a mapping relationship between port status values stored in a predetermined register address and each PHY chip comprises:

inquiring the address of the preset register through an SPI bus;

if the port state value stored by a single bit in the preset register address is a first value, determining that the port state of the PHY chip corresponding to the bit is an initial working state;

and if the port state value stored by a single bit in the preset register address is a second value, determining that the port state of the PHY chip corresponding to the bit is changed from an initial working state to a non-initial working state.

8. A port state policing apparatus, comprising:

the state signal receiving module is used for receiving the pin state signal sent by the PHY chip;

and the reporting module is used for reporting an interrupt signal to the processing module when determining that the port state of at least one PHY chip changes according to the pin state signal so as to trigger the processing module to supervise the port state of each PHY chip through a mapping relation between port state values stored in a preset register address and each PHY chip, wherein the port state values corresponding to each PHY chip are updated in real time according to the pin state signal.

9. A port state policing apparatus, comprising:

the interrupt signal receiving module is used for receiving an interrupt signal reported by the programmable logic device when the port state of at least one PHY chip is determined to change according to the received pin state signal sent by the PHY chip;

the supervision module is used for responding to the interrupt signal and supervising the port state of each PHY chip through the mapping relation between the port state value stored in the preset register address and each PHY chip; and updating the port state value corresponding to each PHY chip in real time according to the pin state signal.

10. A port state policing system, comprising: the system comprises a programmable logic device, a processing module and at least one PHY chip; the processing module is connected with the programmable logic device; different ports of the programmable logic device are respectively connected with the PHY chips;

the port status policing system is for performing the port status policing method of any of claims 1-7.

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