CN101051828A

CN101051828A - Surge separate circuit

Info

Publication number: CN101051828A
Application number: CN 200610067136
Authority: CN
Inventors: 蔡仁杰; 刘育箕
Original assignee: Sunplus Technology Co Ltd
Current assignee: Sunplus Technology Co Ltd
Priority date: 2006-04-03
Filing date: 2006-04-03
Publication date: 2007-10-10
Anticipated expiration: 2026-04-03
Also published as: CN100495917C

Abstract

Using clock signal inside IC, surge separation circuit separates surge appeared on the input signal at edge of clock signal. The surge separation circuit includes edge signal generation unit, OR gate, AND gate, selection unit, first trigger, and second trigger. Using specific connection relation and function of the above said each component; the surge separation circuit can filter out surge with cycle being equivalent to a half cycle of inner clock signal.

Description

A kind of surge separate circuit

Technical field

The present invention relates to a kind of signal processing circuit, relate in particular to a kind of surge separate circuit that can both separate surging at any time.

Background technology

At integrated circuit (IC; Integrated Circuit) in the design; some surgings that can't predict (glitch) can appear usually by designed circuit; thereby cause circuit wrong logic output to occur; especially from the signal (for example number control signal) of the outside input of integrated circuit when surging occurring, all the more so.Therefore, how eliminating surging in designed circuit, make circuit that correct logic output can be arranged, then is a very important problem.

A kind of known technology is an employing internal clock signal external signal synchronously,, export and cause designed circuit wrong logic to occur, yet this known technology exists following shortcoming: the disorder of chip controls logic because surging appears in external signal to avoid; Influence the stability of chip performance; And when surging appears at the edge of internal clock signal, still can cause designed circuit wrong logic output to occur; As shown in Figure 1.

Fig. 1 is the sequential chart of internal clock signal, external signal and the synchronization output signal of known technology, Fig. 1 demonstrates external signal when surging (shown in 102) appears in the rising edge of internal clock signal, still can't eliminate this surging via the synchronization output signal that internal clock signal produces the synchronous back of external signal, and this surging can be amplified (shown in 104).

In addition, also has a kind of known technology, it is exactly the disclosed digital filter of U.S. Patent number US20030091135, this digital filter is used to receive the digital input signals that has surging, this digital filter comprises: delay line is to be used for that digital input signals is done time delay to postpone digital input signals to produce; The rising edge detector is to be used to make described delay digital input signals to produce the rising edge id signal; The trailing edge detector is to be used to make described delay digital input signals to produce the trailing edge id signal; First mixing arrangement is the mixed signal that is used to produce rising edge filtering id signal and digital input signals; Second mixing arrangement is the mixed signal that is used to produce trailing edge filtering id signal and digital input signals; The 3rd mixing arrangement, be to be used to receive the mixed signal that first mixing arrangement and second mixing arrangement are exported, being created in the digital output signal of rising edge of clock signal and trailing edge non-surge, thereby make digital filter can export the digital output signal of non-surge.

Though this digital filter has overcome employing internal clock signal caused 3 shortcomings of external signal synchronously, this digital filter also still has shortcoming, be exactly its can't the filtering cycle greater than the surging that postpones digital input signals.

Summary of the invention

Purpose of the present invention just provides a kind of surge separate circuit, makes surging to be separated at any time.

Based on foregoing and other purposes, the present invention proposes a kind of surge separate circuit, this surge separate circuit comprise margin signal generation device or door, with door, choice device, first trigger and second trigger.Wherein, the margin signal generation device produces rising edge signal and trailing edge signal by input signal, first clock signal and second clock signal, and the rising edge signal is to fasten the lock input signal to obtain when first state of first clock signal, and the trailing edge signal is to fasten the lock input signal to obtain when first state of second clock signal, and the second clock signal is the inversion signal of first clock signal.

Or door be input as rising edge signal and trailing edge signal, and or be output as or logical signal.With door be input as rising edge signal and trailing edge signal, and be output as and logical signal with door.Choice device reception or logical signal and and logical signal, and according to selecting signal output or logical signal or and logical signal.First trigger produces the selection signal by the output of the 3rd clock signal and choice device, wherein selecting signal is that the output of fastening the lock choice device when first state of the 3rd clock signal obtains, and the 3rd clock signal is the second clock signal to be done time delay and the signal that produces.Second trigger produces surging by first clock signal and separates output signal with the output of choice device, it is that the output of fastening the lock choice device when first state of first clock signal obtains that surging separates output signal.

The present invention is exactly the clock signal that adopts IC interior, edge in clock signal, the surging that appears on the input signal is separated, surge separate circuit of the present invention comprise margin signal generation device or door, with door, choice device, first trigger and second trigger.Utilize above-mentioned each element specific annexation and function, the present invention can be equivalent to half surging of internal clock signal by the filtering cycle, and make no matter external input signal is surging to occur at the rising edge of internal clock signal or at trailing edge, surging separates output signal output any surging can not occur, thereby overcomes the shortcoming that prior art exists.

For foregoing of the present invention and other purposes, feature and advantage more can be become apparent, provide an embodiment below, and in conjunction with the accompanying drawings, be described in detail below.

Description of drawings

Fig. 1 is the sequential chart of internal clock signal, external input signal and the synchronization output signal of known technology;

Fig. 2 is according to the described surge separate circuit schematic diagram of the embodiment of the invention;

Fig. 3, Fig. 4, Fig. 5 and Fig. 6 are the sequential charts according to each signal in the described surge separate circuit of the embodiment of the invention.

Embodiment

As shown in Figure 2, be the schematic diagram of surge separate circuit, by margin signal generation device 210 or door 220, form with door 230, choice device 240, first trigger 250 and second trigger 260.Wherein, margin signal generation device 210 is according to input signal input, the first clock signal clk1 and second clock signal clk2 and produce rising edge signal rs and trailing edge signal fs, and rising edge signal rs is that (at this embodiment is the just edge end of the first clock signal clk1 at first state of the first clock signal clk1, below with just representing first state along end) time fastens lock input signal input and obtains, and trailing edge signal fs fastens lock input signal input to obtain when the end of the just edge of second clock signal clk2, and wherein second clock signal clk2 is the inversion signal of the first clock signal clk1.

Or door 220 be input as rising edge signal rs and trailing edge signal fs, and or 220 be output as or logical signal os.With door 230 be input as rising edge signal rs and trailing edge signal fs, and be output as and logical signal as with door 230.Choice device 240 receive or logical signal os and with logical signal as, and according to select signal cs output or logical signal os or with logical signal as.First trigger 250 produces according to the output es of the 3rd clock signal clk3 and choice device 240 selects signal cs, select signal cs be the 3rd clock signal clk3 just along end the time fasten the output es of lock choice device 240 and obtain, wherein the 3rd clock signal clk3 does time delay with second clock signal clk2 and the signal that produces.Second trigger 260 produces surging according to the first clock signal clk1 with the output es of choice device 240 and separates output signal output, and it is that the output es that fastens lock choice device 240 when the end of the just edge of the first clock signal clk1 obtains that surging separates output signal output.

Margin signal generation device 210 among Fig. 2 comprises first D flip-flop 211 and second D flip-flop 212.Wherein, the input receiving inputted signal input of first D flip-flop 211, and the input end of clock of first D flip-flop 211 receives the first clock signal clk1, the output output rising edge signal rs of first D flip-flop 211.The input receiving inputted signal input of second D flip-flop 212, and the input end of clock of second D flip-flop 212 receives second clock signal clk2, the output output trailing edge signal fs of second D flip-flop 212.

In addition, the choice device 240 among Fig. 2 can adopt the alternative multiplexer, and first trigger 250 and second trigger 260 can adopt D flip-flop.In other embodiment, surge separate circuit also comprises anti-phase device 270 and deferred mount 280, wherein anti-phase device 270 is that the first clock signal clk1 is anti-phase and produce second clock signal clk2, and deferred mount 280 is that second clock signal clk2 is done time delay and produces the 3rd clock signal clk3.

Fig. 3 is the sequential chart of each signal in the surge separate circuit.In this embodiment, when selecting signal cs=0, the output es of choice device 240 is and logical signal as; When selecting signal cs=1, the output es of choice device 240 is or logical signal os.

As shown in Figure 3, when input is normality high potential (normal high), when being the normality logical one, under normal circumstances, rising edge signal rs=1, trailing edge signal fs=1 or logical signal os=1, the output es=1 with logical signal as=1, choice device 240, selection signal cs=1 and surging separate output signal output=1.

If when the rising edge of the first clock signal clk1, occur among the input signal input one be 0 surging (as Fig. 3 302 shown in), rising edge signal rs=0 then, trailing edge signal fs=1, or logical signal os=1, with logical signal as=0, at this moment, owing to select signal cs=1, then the output es=of choice device 240 or logical signal os=1, after next trailing edge after surging is come, when first trigger 250 triggers according to the 3rd clock signal clk3, select the output es=0 of signal cs=choice device 240, at this moment, the output es=of choice device 240 and logical signal as=0, and after the next rising edge after surging came, when second trigger 260 triggered according to the first clock signal clk1, surging separated the output es=1 of output signal output=choice device 240.

Fig. 4, Fig. 5 and Fig. 6 equally also are the sequential charts of each signal of surge separate circuit.In this embodiment, when signal cs=0 was selected in order, the output es of choice device 240 was and logical signal as; When signal cs=1 was selected in order, the output es of choice device 240 was or logical signal os.Wherein, shown in Figure 4 is to be normality high potential (normal high) at input, be under the situation of normality logical one, and when the trailing edge of the first clock signal clk1, occur among the input signal input one be 0 surging (as Fig. 4 402 shown in) the sequential chart of each signal.Shown in Figure 5 then is to be normality electronegative potential (normal low) at input, be under the situation of normality logical zero, and when the rising edge of the first clock signal clk1, occur among the input signal input one be 1 surging (as Fig. 5 502 shown in) the sequential chart of each signal.Shown in Figure 6 is to be normality electronegative potential (normal low) at input, be under the situation of normality logical zero, and when the trailing edge of the first clock signal clk1, occur among the input signal input one be 1 surging (as Fig. 6 602 shown in) the sequential chart of each signal, and the manner of execution of each signal can be described according to the manner of execution of described each signal of Fig. 3 among Fig. 4, Fig. 5 and Fig. 6, does not repeat them here.

By Fig. 3, Fig. 4, Fig. 5 and Fig. 6 as can be known, no matter external input signal is surging to occur at the rising edge of internal clock signal or at trailing edge, and surging separates output signal output any surging can not occur.

In sum, the present invention is the clock signal that adopts IC interior, in the edge of clock signal, the surging that appears on the input signal is separated, so the present invention can filtering be equivalent to the surging of internal clock signal half period.Therefore, use integrated circuit of the present invention can not occur following shortcoming again: to use the chip controls logic disorder that known technology took place; Influence the stability of chip performance; And when surging appears at the edge of internal clock signal, still can cause designed circuit wrong logic output to occur.

Though the present invention with preferred embodiment openly as above, yet be not in order to limit the present invention, for those of ordinary skill in the art, can be easy to realize additional advantage and make amendment, therefore under the situation of the spirit and scope of the universal that does not deviate from claim and equivalency range and limited, the examples shown that the present invention is not limited to specific details, representational equipment and illustrates here and describe.

Claims

1. a surge separate circuit is characterized in that, this surge separate circuit comprises:

One edge signal generation device, produce a rising edge signal and a trailing edge signal according to an input signal, one first clock signal and a second clock signal, this rising edge signal is to fasten this input signal of lock to obtain when one first state of this first clock signal, this trailing edge signal is to fasten this input signal of lock to obtain when this first state of this second clock signal, wherein this second clock signal inversion signal that is this first clock signal;

One or door, should or this rising edge signal of door input and this trailing edge signal, and should or door export one or logical signal;

One with door, should import this rising edge signal and this trailing edge signal with door, and should and door export one and logical signal;

One choice device, receive should or logical signal with should and logical signal, and select signal and export this or logical signal and be somebody's turn to do and one of them signal of logical signal according to one;

One first trigger, be to produce this selection signal according to the output signal of one the 3rd clock signal and this choice device, this selection signal is that the output signal of fastening this choice device of lock when this first state of the 3rd clock signal obtains, and wherein the 3rd clock signal is this second clock signal to be done time delay and the signal that produces; And

One second trigger, be to produce a surging with the output signal of this choice device according to this first clock signal to separate output signal, it is that the output signal of fastening this choice device of lock when this first state of this first clock signal obtains that this surging separates output signal.

2. surge separate circuit as claimed in claim 1 is characterized in that, described edge signal generation device comprises:

One first edge triggered flip flop, its input receives this input signal, and input end of clock receives this first clock signal, and output is exported this rising edge signal;

One second edge triggered flip flop, its input receives this input signal, and input end of clock receives this second clock signal, and output is exported this trailing edge signal.

3. surge separate circuit as claimed in claim 2 is characterized in that, described first edge triggered flip flop and second edge triggered flip flop are d type flip flop.

4. surge separate circuit as claimed in claim 1 is characterized in that, described choice device is an alternative multiplexer.

5. surge separate circuit as claimed in claim 1 is characterized in that, described first trigger and second trigger are d type flip flop.

6. surge separate circuit as claimed in claim 1 is characterized in that, this surge separate circuit also comprises an anti-phase device, and this anti-phase device is that this first clock signal is anti-phase and produce this second clock signal.

7. surge separate circuit as claimed in claim 1 is characterized in that this surge separate circuit also comprises a deferred mount, and this deferred mount is that this second clock signal is done time delay and produced the 3rd clock signal.