CN101051432A - Method for correcting display data enable signal - Google Patents
Method for correcting display data enable signal Download PDFInfo
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- CN101051432A CN101051432A CN 200710095807 CN200710095807A CN101051432A CN 101051432 A CN101051432 A CN 101051432A CN 200710095807 CN200710095807 CN 200710095807 CN 200710095807 A CN200710095807 A CN 200710095807A CN 101051432 A CN101051432 A CN 101051432A
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- enabling pulse
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Abstract
The present invention provides a method for modifying data enable signal of display. Said method includes the following several steps: receiving data enable signal of first picture; according to the input enable pulse of vertical effective cycle of first picture producing complex analog enable pulse in vertical blanking cycle; delaying vertical blanking cycle; and according to the time for delaying vertical blanking cycle reducing the cycle of complex input enable pulse of vertical effective cycle of data enable signal of second picture.
Description
Technical field
The invention relates to the data enable signal of display, be meant a kind of method of revising the data enable signal of display especially.
Background technology
Technology fast development, especially LCD (LCD), plasma display (PDP) and Organic Light Emitting Diode (OLED) display etc. along with display make the image quality of display promote day by day.See also Fig. 1, it is the calcspar of prior art display.As shown in the figure, display includes a scaler (scaler) 10, it is used for the image data that the convergent-divergent main frame is transmitted, for example the resolution of image data is 640 * 480, and the display resolution of display is 800 * 600, scaler 10 can be amplified the resolution of (up-scaling) image data, makes the resolution of image data meet the display resolution of display (800 * 600).In addition, scaler 10 can produce a data enable signal (Data Enable DE), and is sent to time schedule controller 15 together with the image data behind the convergent-divergent.
See also Fig. 2, be the sequential chart of the data enable signal of prior art.As shown in the figure, data enable signal DE, its include one vertical effective period (Vertical Active Period) T1 and vertical blanking cycle (Vertical Blanking Period) T2, vertical effective period, T1 added that vertical blanking period T 2 is the time that shows a picture.Vertically effective period, T1 included plural number input enabling pulse 40, if the resolution of image data is 800 * 600, promptly including 600 input enabling pulses 40 vertical effective period, also is that the N in graphic is 600, each input enabling pulse 40 each corresponding 800 pixel.The signal of vertical blanking period T 2 is the low level signal.
Explanation by above-mentioned Fig. 1 can learn that time schedule controller 15 produces first control signal and second control signal, must can produce two control signals according to the input enabling pulse 40 of data enable signal DE.State and ask in order to reach other design now, many pictures scan mechanism (multi-frame scan) for example, time schedule controller 15 must produce more first control signal and second control signal of more number, and producing method is to utilize vertical blanking period T 2 to produce requisite number purpose first control signal and second control signal.
See also Fig. 3 A, be the sequential chart of prior art input data enable signal, internal data enable signal, first control signal and second control signal.As shown in the figure, the input data enable signal DE1 that time schedule controller 15 is exported according to scaler 10 produces the first control signal XDIO and the second control signal XSTB, and shown in the dotted line of icon, the first control signal XDIO is corresponding with the second control signal XSTB.When data drive circuit 20 receives the first control signal XDIO, promptly begin to receive image data till receiving the second control signal XSTB, and transmit image data to display panel 30 and show image.Prior art is in order to produce more control signal XDIO, XSTB, time schedule controller 15 can produce an internal data enable signal DE2, the internal data enable signal DE2 that time schedule controller 15 is produced is with respect to the vertical blanking period T 2 of input data enable signal DE1, and have a plural number simulation enabling pulse 50, described simulation enabling pulse 50 be according to input data enable signal DE1 vertical effective period T1 input enabling pulse 40 and produce.So, time schedule controller 15 can produce control signal XDIO, XSTB according to simulation enabling pulse 50 during vertical blanking period T 2.
Yet the vertical blanking period T 2 of input data traffic energy signal DE1 differs and is decided to be the integral multiple in the cycle of importing enabling pulse 40.If vertical blanking period T 2 is the integral multiple in the cycle of input enabling pulse 40, then can be shown in Fig. 3 B, last simulation enabling pulse 50 of internal data enable signal DE2 can be connected first input enabling pulse 40 of the input data enable signal DE1 of next picture smoothly; If vertical blanking period T 2 is not the integral multiple in the cycle of input enabling pulse 40, then can be shown in Fig. 3 C, the pulsewidth of last simulation enabling pulse 50 of internal data enable signal DE2 must be reduced first input enabling pulse 40 of the input data enable signal DE1 that can be connected next picture.So promptly can cause the sequential of last simulation enabling pulse 50 is produced according to this control signal XDIO, XSTB quite approaching, that is to say that data drive circuit 20 does not have enough time reception image datas, so data drive circuit 20 will receive partly image data, and can't be shown in display panel 30.
Summary of the invention
Because the problems referred to above, the present invention proposes a kind of method of revising the data enable signal of display, and it can allow the cycle of the plural number simulation enabling pulse (simulation enable pulse) that produced in the vertical blanking cycle all roughly be same as the cycle of the input enabling pulse of vertical effective period.
The object of the present invention is to provide a kind of method of revising the data enable signal of display, it is by prolonging the vertical blanking cycle of data enable signal, and allow cycle of last simulation enabling pulse of being produced in the vertical blanking cycle can roughly be same as cycle of input enabling pulse of the vertical effective period of data enable signal, and reduce cycle of input enabling pulse of vertical effective period of the data enable signal of next picture according to time of being prolonged, the time that is prolonged with compensation.
According to the present invention, the method for revising the data enable signal of display is a data enable signal that receives a picture earlier; Afterwards, the input enabling pulse according to a vertical effective period of data enable signal produces plural number simulation enabling pulse in a vertical blanking cycle of data enable signal, and the cycle of described simulation enabling pulse roughly is same as the cycle of input enabling pulse.If the vertical blanking cycle is not the integral multiple in input enabling pulse cycle, then postpone the vertical blanking cycle so that the cycle of last the simulation enabling pulse that is produced in the vertical blanking cycle is substantially equal to the cycle of input enabling pulse, and, reduce cycle of plural number input enabling pulse of vertical effective period of the data enable signal of next picture according to the time that postpones the vertical blanking cycle.
By modification method of the present invention, the data drive circuit that can avoid display (for example LCD) can't complete reception image data and can't be shown in display panel, so can improve the demonstration usefulness of display, and then the user is provided higher visual enjoyment.Method of the present invention can apply to the scaler of display, and transmitting data enable signal to the time schedule controller, utilize method of the present invention to revise data enable signal earlier, again revised data enable signal is sent to time schedule controller afterwards, perhaps can apply to time schedule controller, it is behind the data enable signal that receives the scaler transmission, and the data enable signal that promptly utilizes this modification method correction to be received is to solve the shortcoming of prior art.
Description of drawings
Fig. 1 is the calcspar of prior art display;
Fig. 2 is the sequential chart of prior art data enable signal;
Fig. 3 A is the sequential chart of prior art input data enable signal, internal data enable signal, first control signal and second control signal;
Fig. 3 B is another sequential chart of prior art input data enable signal, internal data enable signal, first control signal and second control signal;
Fig. 3 C is the another sequential chart of prior art input data enable signal, internal data enable signal, first control signal and second control signal;
Fig. 4 is the sequential chart of input data enable signal, image data, storage data and the internal data enable signal of a preferred embodiment of the present invention;
Fig. 5 A is the input data enable signal of a preferred embodiment of the present invention and the sequential chart of internal data enable signal;
Fig. 5 B is the input data enable signal of another preferred embodiment of the present invention and the sequential chart of internal data enable signal; And
Fig. 6 is the process flow diagram of a preferred embodiment of the present invention.
Drawing reference numeral:
10 scaler, 15 time schedule controllers
20 data drive circuits, 25 gate driver circuits
30 display panels, 40 input enabling pulses
45 input enabling pulses, 50 simulation enabling pulses
D image data DE1 imports data enable signal
DE2 internal data enable signal SD storage data
T1 vertical effective period of T1 ' is effective period vertically
2 ' the vertical blanking cycle of T2 vertical blanking period T
3 ' the horizontal blanking cycle of T3 horizontal blanking period T
T4 level T5 effective period time delay
The XDIO first control signal XSTB second control signal
Embodiment
See also Fig. 4, be the sequential chart of input data enable signal, image data, storage data and the internal data enable signal of a preferred embodiment of the present invention.The input data enable signal DE1 that this sequential chart is shown, corresponding one first picture and one second picture.Because the icon space is limited, so the input data enable signal DE1 of Fig. 4 only illustrates corresponding to the vertical blanking period T 2 of the back segment of first picture and vertical effective period of T1 corresponding to the leading portion of second picture.Below modification method of the present invention is described for the sequential chart that cooperates Fig. 4.
When the vertical blanking period T 2 of input data enable signal DE1 be not input data enable signal DE1 vertical effective period T1 the integral multiple in cycle of input enabling pulse 40 time, if produce simulation enabling pulses 50 according to the method for prior art in vertical blanking period T 2, so the cycle of last the simulation enabling pulse 50 that is produced in vertical blanking period T 2 can be different from the cycle of importing enabling pulse 40.The present invention is not under the situation of integral multiple in cycle of input enabling pulse 40 in vertical blanking period T 2, when producing simulation enabling pulse 50, at first shown in the sequential of the internal data enable signal DE2 of Fig. 4, postponing vertical blanking period T 2 is T2 ', make the cycle of last simulation enabling pulse 50 roughly be same as the cycle of input enabling pulse 40, so can completely receive the image data (figure does not paint) of corresponding last simulation enabling pulse 50.Above-mentioned delay vertical blanking period T 2 is the time of T2 ', is last gap time of simulating the cycle of enabling pulse 50 (figure does not paint) and importing the cycle of enabling pulse 40 of vertical blanking period T 2.
In addition, when delay vertical blanking period T 2 is T2 ', shown in the sequential of the storage data SD of Fig. 4, the present invention can receive and store in real time follow-up input data enable signal DE1 and image data D corresponding to second picture, just store in regular turn immediately corresponding second picture input data enable signal DE1 vertical effective period T1 first input enabling pulse 40 import enabling pulse 40 with second, the rest may be inferred.Above-mentioned storage input data enable signal DE1 and image data D can pass through line buffer (line buffer) and store.After delay vertical blanking period T 2 was T2 ', promptly with the input enable signal DE1 and the image data D that read corresponding to second picture also exported.
According to preferred embodiment of the present invention, exporting the preceding of stored input enable signal DE1 can be the time of T2 ' according to postponing vertical blanking period T 2 earlier, the cycle of the plural number input enabling pulse 40 of the input data enable signal DE1 of reduction desire output, and the plural number that is output as internal data enable signal DE2 is again imported enabling pulse 45, is the time of T2 ' to postpone vertical blanking period T 2 before the compensation.Owing to also can postpone vertical blanking period T 2 after this data enable signal DE2 that is reduced for T2 ', so this mode can keep the display cycle of each picture identical.The cycle of the above-mentioned described input enabling pulse 45 that is reduced is reduction horizontal blanking cycle (Horizontal Blanking Period) T3, the low level pulse width of i.e. reduction input enabling pulse 40, the input enabling pulse 40 that is reduced promptly becomes the input enabling pulse 45 of internal data enable signal DE2.As shown in the figure, internal data enable signal DE2 vertical effective period T1 ' input enabling pulse 45 horizontal blanking period T 3 ' can less than input data enable signal DE1 vertical effective period T1 the horizontal blanking period T 3 of input enabling pulse 40.
For instance, if be 30 clocks (clock) time delay, the horizontal blanking period T 3 that then can pass through each input enabling pulse 40 of a small amount of reduction vertical effective period of T1 is horizontal blanking period T 3 ', up to total reduction is 30 clocks, time so that compensation is postponed, for example can once reduce 3 clocks, 5 clocks or 10 clocks.The present invention reduces the mode of the horizontal blanking period T 3 of input enabling pulse 40, except fixing reduction cycle of above-mentioned foundation one, outside the horizontal blanking period T 3 of reduction input enabling pulse 40, also can import the quantity of enabling pulses 40 according to all of the input data enable signal DE1 that postpones the time that vertical blanking period T 2 be T2 ' and second picture, try to achieve an average reduction cycle, be T3 ' and reduce all horizontal blanking period T of importing enabling pulses 40 3 according to this average reduction cycle.
See also Fig. 5 A, be the input data enable signal of a preferred embodiment of the present invention and the sequential chart of internal data enable signal.The level effective period of the input enabling pulse 40 of the input data enable signal DE1 of this embodiment, (Horizontal Active Period) T4 was 640 clocks, and horizontal blanking period T 3 is 60 clocks, and the cycle of promptly importing enabling pulse 40 is 700 clocks.20 clocks of vertical blanking cycle less than of the input data enable signal DE1 of first picture of this embodiment, and not for importing the integral multiple of enabling pulse 40.So this embodiment shown in the sequential of the internal data enable signal DE2 of Fig. 5 A, is the time T 5 that postpones 20 clocks.Afterwards, according to the fixedly reduction cycle of 10 clocks, reduction input data enable signal DE1 is that first of internal data enable signal DE2 imported enabling pulse 45 with second with the horizontal blanking period T 3 of second input enabling pulse 40 with respect to first of the vertical effective period of second picture, so can compensate the time that is postponed before.And the cycle of input enabling pulse 40 does not afterwards promptly need to reduce again.Can know from icon and to find out that the horizontal blanking cycle of the 3rd the input enabling pulse 40 of internal data enable signal DE2 is promptly recovered original cycle, just be same as the 3rd the input enabling pulse 40 of the input data enable signal DE1 of second picture.
See also Fig. 5 B, be the input data enable signal of another preferred embodiment of the present invention and the sequential chart of internal data enable signal.This embodiment is different from an embodiment and is that embodiment T5 time delay is 20 clocks, and be the integral multiple in fixedly reduction cycle, and 25 clocks of vertical blanking cycle less than of the input data enable signal DE1 of first picture of this embodiment, so the time T 5 that the internal data enable signal DE2 of this embodiment is postponed is 25 clocks, and be not the fixing integral multiple in reduction cycle.So, this embodiment only can be according to first and second horizontal blanking cycle of importing enabling pulse 40 of the vertical effective period of relative second picture of fixing reduction cycle reduction input data enable signal DE1, and become first and second the input enabling pulse 45 of internal data enable signal DE2, then during the 3rd input enabling pulse 40 of reduction input data enable signal DE1, then not according to fixing reduction cycle but become the 3rd of internal data enable signal DE2 according to horizontal blanking cycle of the 3rd the input enabling pulse 40 of remaining reduction reduction input data enable signal DE1 and import enabling pulse 45.
In sum, the method for the data enable signal of correction display of the present invention shown in the process flow diagram of Fig. 6, at first shown in step S1, receives a data enable signal of first picture; Afterwards, shown in step S2, the input enabling pulse of the vertical effective period of foundation first picture, produce plural number simulation enabling pulse in the vertical blanking cycle, if this vertical blanking cycle is not when being the integral multiple of input enabling pulse, promptly then carry out step S3, postpone this vertical blanking cycle, allow the cycle of last simulation enabling pulse can be substantially equal to the cycle of importing enabling pulse.
At last, promptly shown in step S4, according to the time that postpones the vertical blanking cycle, reduce cycle of plural number input enabling pulse of vertical effective period of the data enable signal of second picture, this step is the horizontal blanking cycle of reduction input enabling pulse, the reduction mode can be reduced the cycle of described input enabling pulse according to fixing reduction cycle, perhaps according to the quantity of the described input enabling pulse of the vertical effective period of the time that postpones the vertical blanking cycle and second picture, try to achieve the average reduction cycle, and on average reduce the cycle of described input enabling pulse according to this average reduction cycle.
Above-mentioned steps S3 postpones vertical blanking in the time of the cycle, is data enable signal and the image data that stores second picture in real time, and is postponing vertical blanking week after date, reads stored data enable signal and image data and exports.In addition, before exporting stored data enable signal, be according to the time that postpones before the vertical blanking cycle, the plural number that reduces the data enable signal of this desire output is imported the cycle of enabling pulse, to compensate the time that is postponed.
By modification method of the present invention, the data drive circuit that can avoid display (for example LCD) can't complete reception image data and can't be shown in display panel, so can improve the demonstration usefulness of display, and then the user is provided higher visual enjoyment.Method of the present invention can apply to the scaler of display, and transmitting data enable signal to the time schedule controller, utilize method of the present invention to revise data enable signal earlier, again revised data enable signal is sent to time schedule controller afterwards, perhaps can apply to time schedule controller, it is behind the data enable signal that receives the scaler transmission, and the data enable signal that promptly utilizes this modification method correction to be received is to solve the shortcoming of prior art.
The above person, it only is preferred embodiment of the present invention, be not to be used for limiting scope of the present invention,, all should be included in the claim of the present invention so the equalization of doing according to the described shape of claim of the present invention, structure, feature and principle changes and modifies such as.
Claims (12)
1. a method of revising the data enable signal of display is characterized in that, this method comprises:
Receive a data enable signal of one first picture, this data enable signal includes a vertical effective period and the vertical blanking cycle, includes plural number input enabling pulse this vertical effective period;
According to the input enabling pulse of this vertical effective period, produce plural number simulation enabling pulse in this vertical blanking cycle, the cycle of this simulation enabling pulse is substantially equal to the cycle of input enabling pulse;
Postpone the described vertical blanking cycle, allow cycle of last simulation enabling pulse be substantially equal to the cycle of described input enabling pulse; And
According to the time that postpones the described vertical blanking cycle, reduce cycle of plural number input enabling pulse of vertical effective period of the data enable signal of one second picture.
2. the method for claim 1 is characterized in that, the step that postpones the described vertical blanking cycle comprises:
Store the data enable signal of described second picture; And
In postponing described vertical blanking week after date, the cycle and the output of described input enabling pulse of reading the data enable signal of the second stored picture and reducing the vertical effective period of this data enable signal.
3. method as claimed in claim 2 is characterized in that, the step that stores the data enable signal of described second picture comprises utilizes an impact damper to store this data enable signal.
4. method as claimed in claim 2 is characterized in that, this method also comprises:
Store an image data of described second picture; And
In postponing all after dates of described vertical blanking, read the image data and the output of the second stored picture.
5. method as claimed in claim 4 is characterized in that, the step that stores the image data of described second picture comprises utilizes an impact damper to store described image data.
6. the method for claim 1 is characterized in that, according to the time that postpones the described vertical blanking cycle, the step in the cycle of reduction plural number input enabling pulse comprises:
Foundation one is the reduction cycle fixedly, reduces the cycle of described input enabling pulse.
7. the method for claim 1 is characterized in that, according to the time that postpones the described vertical blanking cycle, the step in the cycle of reduction plural number input enabling pulse comprises:
The quantity of the described input enabling pulse of the vertical effective period of the time in foundation described vertical blanking cycle of delay and the data enable signal of described second picture, try to achieve an average reduction cycle, and reduce the cycle of described input enabling pulse according to this average reduction cycle.
8. the method for claim 1 is characterized in that, according to the time that postpones the described vertical blanking cycle, the step in the cycle of reduction plural number input enabling pulse comprises a horizontal blanking cycle that reduces described input enabling pulse.
9. the method for claim 1 is characterized in that, this method is a scaler that applies to a display.
10. a scaler is characterized in that, this scaler is used the method for claim 1.
11. the method for claim 1 is characterized in that, this method is the time schedule controller that applies to a display.
12. a time schedule controller is characterized in that, this time schedule controller uses the method for claim 1.
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| CNB2007100958078A CN100468492C (en) | 2007-04-04 | 2007-04-04 | Method for correcting display data enable signal |
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| CNB2007100958078A CN100468492C (en) | 2007-04-04 | 2007-04-04 | Method for correcting display data enable signal |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102231267A (en) * | 2011-04-18 | 2011-11-02 | 友达光电股份有限公司 | Method for synchronizing horizontal synchronizing signal and display |
| CN102446500A (en) * | 2010-10-04 | 2012-05-09 | 宏碁股份有限公司 | Image display method and image display system |
| CN101789222B (en) * | 2009-01-22 | 2012-05-23 | 联咏科技股份有限公司 | Method utilizing data enable signal to control time sequence of display device and time sequence control circuit |
| CN103971652A (en) * | 2013-01-24 | 2014-08-06 | 晨星半导体股份有限公司 | Image processing method and image processing device |
| CN107437395A (en) * | 2016-05-25 | 2017-12-05 | 三星显示有限公司 | Operate the method for display device and perform the display device of this method |
| CN108074528A (en) * | 2016-11-17 | 2018-05-25 | 乐金显示有限公司 | Display device and its controller |
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2007
- 2007-04-04 CN CNB2007100958078A patent/CN100468492C/en active Active
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101789222B (en) * | 2009-01-22 | 2012-05-23 | 联咏科技股份有限公司 | Method utilizing data enable signal to control time sequence of display device and time sequence control circuit |
| CN102446500A (en) * | 2010-10-04 | 2012-05-09 | 宏碁股份有限公司 | Image display method and image display system |
| CN102446500B (en) * | 2010-10-04 | 2014-03-05 | 宏碁股份有限公司 | Image display method and image display system |
| CN102231267A (en) * | 2011-04-18 | 2011-11-02 | 友达光电股份有限公司 | Method for synchronizing horizontal synchronizing signal and display |
| CN102231267B (en) * | 2011-04-18 | 2014-06-04 | 友达光电股份有限公司 | Method for synchronizing horizontal synchronizing signal and display |
| US9236031B2 (en) | 2011-04-18 | 2016-01-12 | Au Optronics Corp. | Method for synchronizing a display horizontal synchronization signal with an external horizontal synchronization signal |
| CN103971652A (en) * | 2013-01-24 | 2014-08-06 | 晨星半导体股份有限公司 | Image processing method and image processing device |
| CN103971652B (en) * | 2013-01-24 | 2016-12-28 | 晨星半导体股份有限公司 | Image treatment method and image processor |
| CN107437395A (en) * | 2016-05-25 | 2017-12-05 | 三星显示有限公司 | Operate the method for display device and perform the display device of this method |
| CN107437395B (en) * | 2016-05-25 | 2022-04-29 | 三星显示有限公司 | Method of operating display device and display device performing the method |
| CN108074528A (en) * | 2016-11-17 | 2018-05-25 | 乐金显示有限公司 | Display device and its controller |
| CN108074528B (en) * | 2016-11-17 | 2020-11-20 | 乐金显示有限公司 | Display device and controller thereof |
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| CN100468492C (en) | 2009-03-11 |
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