CN101043437B

CN101043437B - Method and apparatus for transmitting quickly operation, management and maintenance cell

Info

Publication number: CN101043437B
Application number: CN2006100656891A
Authority: CN
Inventors: 郑斌儒; 周广水; 刘嵘; 高峻
Original assignee: ZTE Corp
Current assignee: ZTE Corp
Priority date: 2006-03-21
Filing date: 2006-03-21
Publication date: 2010-07-07
Anticipated expiration: 2026-03-21
Also published as: CN101043437A

Abstract

The disclosed method for fast transmitting OAM cell comprises: after the system receives at least one full cell, the ATM cell buffer control module reads the cell head message to obtain its permanent PVC channel number and attribution message; different to common cell, for OAM cell, when there is idle storage block in special room of RAM, extracting an idle storage block pointer from the OAM cell management module, storing the cell in the storage block, and building relation between the attributed PVC channel and the pointer; when it comes the transmission time slot, the ATM cell transmission control module obtains the PVC channel number, and reads the cell for transmitting when querying there is cell in the channel. There invention guarantees the transmission PRI for OAM cell.

Description

The method and apparatus of a kind of transmitting quickly operation, OAM cell

Technical field

The present invention relates to ATM (Asynchronous Transfer Mode, asynchronous transfer mode) network OA M (Operations Administration and Maintenance, Operations, Administration and Maintenance) cell transmission technology relates in particular to the method and apparatus of a kind of transmitting quickly operation, OAM cell.

Background technology

Along with the development of computing technique, various data transmission networks have appearred, two kinds of networks of main at present existence, a kind of is to be the transmission IP (Internet Protocol) of unit packet network with the bag, a kind of is to be unit transmission atm network with the cell.In atm network, the oam cell that is used for Operations, Administration and Maintenance has higher priority, needs preferential transmission in sending scheduling process.

At present oam cell being handled main method is that oam cell and common ATM cell leave same FIFO (First-In and First-Out in, first in first out) formation, this method advantage is to have saved memory space, simple to operate, but after enter the oam cell of fifo queue, after the common ATM cell of having only wait to be introduced into formation has been transmitted, just can send, increase the oam cell delay.

Summary of the invention

The technical problem to be solved in the present invention provides the method and apparatus of a kind of transmitting quickly operation, OAM cell, can guarantee the transmission priority of oam cell.

In order to solve the problems of the technologies described above, the invention provides a kind of transmitting quickly operation, administer and maintain the method for oam cell, comprise the handling process of the asynchronous transfer mode ATM cell that receives, may further comprise the steps:

(a) after system receives at least one complete cell, read the header information of this cell, the permanent virtual of obtaining this cell connects PVC channel number and cell attribute information, and common cell and oam cell are handled respectively, as this cell is oam cell, carries out step (b);

(b) when the memory space that uses for oam cell in the random access memory ram has free memory blocks, take out a free memory blocks pointer, this cell is saved in this memory block, and set up the affiliated PVC passage of this cell and this pointer association relation;

This method also comprises the transmission handling process to the ATM cell that receives, and may further comprise the steps:

When (d) sending time slots arrives, obtain the PVC channel number that need send cell at this time slot; When inquiring the cell of this PVC passage, read oam cell and send according to the pointer of this PVC passage association.

Further, said method also can have following characteristics: for each PVC passage is provided with a mode bit, in the described step (b), after the oam cell preservation that receives, the mode bit that also upgrades its affiliated PVC passage is " cell is arranged " sign; After sending oam cell in the step (d), do not had the oam cell of this PVC passage as memory, the mode bit that also upgrades this passage is " no cell " sign.

Further, said method also can have following characteristics: the oam cell of all PVC passages uses the memory space of sharing, this memory space is divided into the memory block of a plurality of oam cell sizes, and safeguards the pointer alignment that free memory blocks in this memory space is arranged.

Further, said method also can have following characteristics: in the described step (b), the pointer alignment of described free memory blocks is the fifo queue of a high bit pointer.

Further, said method also can have following characteristics: in the described step (b), when the memory space of oam cell in the random access memory does not have free memory blocks, wait for and inquire about this RAM once more whether have free space to store this oam cell with the default time cycle, up to overtime this oam cell that abandons.

Further, said method also can have following characteristics: in the described step (a), be common ATM cell as this cell, deposit this cell in the fifo fifo formation according to the PVC channel number; In the described step (d), when inquiring the oam cell of this PVC passage not, whether inquiry has the common ATM cell of this PVC passage again, if having, reads the common ATM cell of this PVC passage and sends.

The present invention also provides the device of a kind of transmitting quickly operation, OAM cell OAM, comprise that asynchronous transfer mode ATM cell buffer memory control module, oam cell administration module, ATM cell send control module, and the random access memory ram memory module, wherein:

Described ATM cell buffer memory control module, be used for after system receives at least one complete cell, read the header information of this cell, the permanent virtual of obtaining this cell connects PVC channel number and cell attribute information, common cell and oam cell are handled respectively, are oam cells as this cell, when the memory space of oam cell in the described RAM memory module has free memory blocks, take out a free memory blocks pointer from described oam cell administration module, this cell is saved in this memory block;

Described oam cell administration module, be used for described RAM memory module is managed for the memory space that oam cell uses, safeguard the pointer of free memory blocks, control the read-write of RAM memory module, and set up the incidence relation of the affiliated PVC passage of this oam cell and its pointer;

Described RAM memory module is used to store oam cell;

Described ATM cell sends control module, is used for when sending time slots arrives, and obtains the PVC channel number that need send cell at this time slot; When inquiring the cell of this PVC passage, read oam cell and send according to the pointer of this PVC passage association.

Further, said apparatus also can have following characteristics: also comprise common ATM cell administration module and memory, described common ATM cell administration module is used for described memory is invented a plurality of fifo queues, manage the state of described formation, provide Query Information for described ATM cell buffer memory control module and described ATM cell send control module; Described memory is used for the common ATM cell of buffer memory.

Further, said apparatus also can have following characteristics: described oam cell administration module comprises cell pointer management module, RAM block controller and status register, wherein:

Described cell pointer management module is used to safeguard a fifo queue of depositing the RAM memory module for the free memory blocks high address of oam cell use;

Described RAM block controller is used to control the read-write of RAM memory module, and produces the low address of described RAM memory module automatically;

Described status register is used to deposit the oam cell state of each PVC passage and the pointer of oam cell.

Further, said apparatus also can have following characteristics: described ATM cell sends control module and comprises that also time slot generation module, time slot packing module and cell send control module, wherein:

Described time slot generation module is used to system constantly to generate the standard sequence of time slots, and each time slot allows to send an ATM cell;

Described time slot packing module is used for the bandwidth for each PVC channel arrangement according to system, and which bar PVC passage certain time slot that determines described time slot generation module to generate should be sent by;

Described cell sends control module, is used for the PVC passage according to described time slot packing module decision, inquiry oam cell formation and common ATM cell formation, if oam cell is arranged, then the reading and sending oam cell is to the next stage module; Otherwise when not having oam cell, the common ATM cell of reading and sending is to the next stage module; If there is not common ATM cell, then directly finish.

Adopt the method for the invention and device, overcome the oam cell transmission priority of failing to resolve that exists in the prior art, and cause oam cell to postpone bigger problem and defective, obtained and used a plurality of PVC channels share RAM, and utilize the RAM pointer to store the technological progress of oam cell, reach the effect of preferential transmission oam cell, saved system cost, improved the system reliability and the market competitiveness.

Description of drawings

Fig. 1 is the structure drawing of device in the embodiment of the invention;

Fig. 2 is an ATM cell header schematic diagram in the embodiment of the invention;

Fig. 3 is the process chart that the device of the embodiment of the invention receives ATM cell;

Fig. 4 is the process chart that the device of the embodiment of the invention sends ATM cell.

Embodiment

Below in conjunction with accompanying drawing the enforcement that sends the oam cell technical scheme based on RAM (random access memory) fast is described in further detail:

Present embodiment utilizes the method for the little RAM communal space to realize a plurality of PVC (PermanentVirtual Connection, permanent virtual connects) forwarding of passage oam cell, this is because system can handle several thousand (maximum can be handled several ten thousand) PVC passages, if as handling common cell, deposit oam cell for fixing FIFO of each PVC channel allocation, need very big memory space, this just needs big external memory storage, has increased system cost; According to the characteristic of oam cell, oam cell is considerably less in general, and in one of several second, it is very little to also have all PVC to send the probability of oam cell simultaneously, can realize so utilize the method for the little RAM communal space to realize that a plurality of PVC passage oam cells are transmitted.So suitable as long as the RAM size is provided with, just the situation appearance that oam cell abandons because there not being memory space can not appear.

As shown in Figure 1, the device of present embodiment comprises with lower module:

ATM cell receives fifo queue 100, is used for receiving and all ATM cell of buffer memory, treats the 101 inquiry uses of ATM cell buffer memory control module, and in the present embodiment, it is the fifo queue memories that all PVC passages are shared that this ATM cell receives fifo queue 100.

ATM cell buffer memory control module 101, be used to determine the direction of transfer of cell and whether abandon, concrete function comprises: whether the inquiry ATM cell receives fifo queue 100 has cell to handle, if cell arranged then from ATM cell receives fifo queue 100, read the header (as shown in Figure 2) of cell, then according to the ATM cell header with this cell of cell determined property oam cell whether, if oam cell, the free memory blocks pointer fifo queue of inquiry cell pointer management module 106, judge whether RAM memory module 110 has free space to store this oam cell, if free space is arranged, from the fifo queue of cell pointer management module 106, read a pointer, and the pointer that returns passed to RAM block controller 107 as the high address of writing RAM memory module 110, deposit in the status register 108 reading the pointer that cell pointer management module 106 returns, and the oam cell mode bit in the update mode register 108, after receiving complete oam cell, deposit it in RAM memory module 110 by RAM block controller 107; Whether if there is not free space, it is overtime constantly to inquire about oam cell administration module 109, up to the overtime oam cell that abandons;

If not oam cell, inquire about PVC channel status corresponding in the common ATM cell administration module 105, whether can receive an ATM cell, if can receive a complete ATM cell, then cell is deposited in the corresponding PVC passage corresponding virtual fifo queue, and upgrade PVC queue management module 104; Otherwise, abandon ATM cell up to finishing storage ATM cell or query timeout with the common ATM cell administration module of setting 105 of cyclic polling; In the present embodiment, this ATM cell buffer memory control module 101 is cell storage resolvers.

Memory 102, be used for the common ATM cell of buffer memory, in the present embodiment, this memory 102 is external memory storages, can be the less SRAM of capacity (static random access memory), also can be the bigger DRAM of low price memory capacity (dynamic random access memory).

Common ATM cell administration module 105 is used for control storage 102, and memory 102 is invented a plurality of fifo queues, manages the state of these formations, provides Query Information for ATM cell buffer memory control module 101 and ATM cell send control module 114.Described common ATM cell administration module 105 also comprises with lower module:

Memory control module 103 is used for the read-write of control storage 102, and by the address administration to memory 102, memory 102 is invented a plurality of fifo queues, stores the cell of different PVC channel numbers respectively;

PVC queue management module 104 is used for memory control module 103 virtual a plurality of fifo queue states are managed, and whether described state promptly has ATM cell among this FIFO.

Oam cell administration module 109 is used for RAM memory module 110 memory spaces are safeguarded, makes the oam cell of all PVC passages can both share these spaces, improves the efficient utilization of memory space, and the read-write of control RAM memory module.Described oam cell administration module 109 also comprises with lower module:

Cell pointer management module 106 is used to safeguard a fifo queue of depositing RAM memory module 110 free memory blocks high addresses, and the memory space that reaches RAM memory module 110 by this fifo queue takies and releasing operation; Because each oam cell all is 54 bytes of fixed size, so the space of distributing for each OAM in system all is 64 bytes, such benefit is the memory space that low 5 (if by word storages) of address bus have just determined an oam cell, and other data/address bus high address has just become the pointer of each cell.

RAM block controller 107 is RAM interface modules, is used to control the read-write of RAM memory module 110, and produces the low address of RAM memory module 110 automatically.

Status register 108 is used to deposit the oam cell state of each PVC passage and the pointer of oam cell.

RAM memory module 110, be used to deposit oam cell, size (as 64 bytes) by cell is divided into a plurality of memory blocks, the read-write of the low address control cell of address bus, high address is used for the selection of memory space, in the present embodiment, RAM memory module 110 is RAM memories of a less memory space, but also can adopt the continuous memory space of certain section in the memory to store oam cell.

ATM cell sends control module 114, is used to send ATM cell.Described ATM cell sends control module 114 and also comprises with lower module:

Time slot generation module 111 is used to system constantly to generate the standard sequence of time slots, and each time slot allows to send an ATM cell;

Time slot packing module 112 is used for the bandwidth for each PVC channel arrangement according to system, and which bar PVC passage certain time slot that decision time slot generation module 111 generates should be sent by;

Cell sends control module 113, obtain to send the PVC channel number of cell at this time slot from time slot packing module 112, difference query State register 108 and PVC queue management module 104, the state information of returning according to status register 108, judge whether RAM memory module 110 exists the oam cell of this PVC passage, if exist, the oam cell pointer that returns according to status register 108, by RAM block controller 107, from RAM memory module 110, read cell, and send to the next stage module, then the oam cell pointer is write cell pointer management module 106, discharge the RAM memory space, and update mode register 108; The if there is no oam cell of this PVC passage, judge according to the state information that PVC queue management module 104 is returned whether common ATM cell transmission is arranged in this PVC passage, if have, from memory 102, read a cell and send to the next stage module by control storage 102, upgrade the state information of corresponding PVC passage in the PVC queue management module 104 simultaneously, otherwise directly finish.

As shown in Figure 3, to the processing of the ATM cell that receives, comprise step down in the present embodiment:

Step 310, ATM cell deposit a public fifo queue in after receiving the ATM cell of fifo queue 100 reception inputs, wait for that ATM cell buffer memory control module 101 reads;

Step 320, whether ATM cell buffer memory control module 101 constantly inquiry ATM cell reception fifo queue 100 exists at least one complete cell, if there is a complete cell, the header information (as shown in Figure 2) of this cell is read back, with PVC channel number and the cell attribute information that obtains this cell, judge whether oam cell of this cell, if this cell is an oam cell, carry out step 330, otherwise carry out step 370;

Step 330, the free block pointer fifo queue of ATM cell buffer memory control module 101 inquiry cell pointer management modules 106 judges whether RAM memory module 110 has free space to store this oam cell, if having, carry out step 340, otherwise carry out step 380;

Step 340, ATM cell buffer memory control module 101 reads a pointer from the pointer fifo queue of cell pointer management module 106 management, and the pointer that returns is passed to RAM block controller 107 as the high address of writing RAM memory module 110;

Step 350, ATM cell buffer memory control module 101 will read pointer that cell pointer management module 106 returns and deposit in the status register 108 and set up incidence relation with corresponding PVC passage, and the oam cell mode bit of this PVC passage is " cell is arranged " sign in the update mode register 108;

Step 360, ATM cell buffer memory control module 101 continue to read ATM cell and receive fifo queue 100, finish up to a cell, and deposit complete oam cell in RAM memory module 110 by RAM block controller 107, finish;

Step 370, storing common ATM cell handles, when ATM cell buffer memory control module 101 inquires after cell is not an oam cell, inquire about the channel status of the corresponding PVC of record in the common ATM cell administration module 105, whether can receive an ATM cell, if can receive a complete ATM cell, then ATM cell buffer memory control module 101 has inquired after memory 102 can receive a cell, notice memory control module 103, memory control module 103 deposits this cell in the fifo queue of memory 102, and upgrade PVC queue management module 104, finish; Otherwise with the common ATM cell administration module of setting 105 of cyclic polling, abandon ATM cell, finish up to finishing storage ATM cell or query timeout.

Step 380, whether ATM cell buffer memory control module 101 inquiry oam cell administration modules 109 are overtime, if overtime, abandon oam cell, finish; Otherwise carry out step 390;

Step 390, ATM cell buffer memory control module 101 is waited for the default time cycle, and then is returned step 330.

As shown in Figure 4, the transmission to the ATM cell that receives in the present embodiment is handled, and comprises step down:

Step 410, cell send control module 113 obtains need send at this time slot cell from time slot packing module 112 PVC channel number;

Step 420, inquiry oam cell manager, cell sends control module 113 and goes query State register 108 and PVC queue management module 104 according to above-mentioned PVC channel number, the state information that PVC queue management module 104 is returned, status register 108 not only returns the state information of the oam cell that has or not this PVC passage, also returns the pointer of oam cell simultaneously;

Step 430 according to above-mentioned state information, judges whether RAM memory module 110 exists the oam cell of this PVC passage, if, execution in step 440, otherwise execution in step 460;

Step 440, cell send control module 113 according to above-mentioned oam cell pointer, by RAM block controller 107, read cell from RAM memory module 110, and send to the next stage module, finish oam cell and send;

Step 450, cell sends control module 113 the oam cell pointer is write cell pointer management module 106, discharge the RAM memory space, and the mode bit of this PVC passage correspondence in the update mode register 108, promptly this PVC passage do not had oam cell the time, mode bit is updated to " no cell " sign, finishes;

Step 460, cell sends the state information that control module 113 is returned according to above-mentioned PVC queue management module 104, and whether in this PVC passage have common ATM cell send, if having, carry out step 470, otherwise directly finish if judging;

Step 470, read common ATM cell, cell sends control module 113 and reads a cell and send to the next stage module from memory 102 by memory control module 103, upgrade the state information of corresponding PVC passage in the PVC queue management module 104 simultaneously, finish once common ATM cell transmit operation.

Need to prove that in the division of unit difference can being arranged, so the present invention is not limited to the functional unit partition mode in the above-mentioned flow process from functional perspective.

As adopt a public memory block fifo queue to deposit the oam cell of all passages, because sending, the cell of each PVC controlled by its service attribute and bandwidth, can only could send after the time slot arrival that it sends at this, should not can not send any cell in the time of its transmission.If should not certain PVC passage send, and send the oam cell of this passage, may abandon oam cell because the bandwidth that surpasses configuration at receiving terminal so.The same FIFO that adopts also can bring this to send the oam cell of certain passage, yet owing to have the oam cell of other passage to be in the front of fifo queue in its front, sending control module 113 can not read from FIFO, causes the oam cell of this passage in time not send.

If as handling common cell, deposit oam cell for fixing FIFO of each PVC channel allocation, also can reach the purpose of preferential transmission oam cell, but, need very big memory space because system can handle several thousand (maximum can be handled several ten thousand) PVC passages.This just needs big external memory storage, has increased system cost; According to the characteristic of oam cell, oam cell is considerably less in general, and in one of several second, it is very little to also have all PVC to send the probability of oam cell simultaneously, can realize so utilize the method for the little RAM communal space to realize that a plurality of PVC passage oam cells are transmitted.So suitable as long as the RAM size is provided with, just the situation appearance that oam cell abandons because there not being memory space can not appear.

In sum, the invention solves the oam cell issue of priority, the preferential common cell of the oam cell of same passage sends, and has solved the interference between the different PVC passages, has guaranteed that the oam cell of each PVC passage can both in time send.And can further save ram space, and then save system cost by the method for sharing.

Claims

A transmitting quickly operation, administer and maintain the method for oam cell, comprise the handling process of the asynchronous transfer mode ATM cell that receives, may further comprise the steps:

(a) after system receives at least one complete cell, read the header information of this cell, the permanent virtual of obtaining this cell connects PVC channel number and cell attribute information, and common cell and oam cell are handled respectively, as this cell is oam cell, carries out step (b);

(b) when the memory space that uses for oam cell in the random access memory ram has free memory blocks, take out a free memory blocks pointer, this cell is saved in this memory block, and set up the affiliated PVC passage of this cell and this pointer association relation;

This method also comprises the transmission handling process to the ATM cell that receives, and may further comprise the steps:

When (d) sending time slots arrives, obtain the PVC channel number that need send cell at this time slot; When inquiring the oam cell of this PVC passage, read oam cell and send according to the pointer of this PVC passage association.
2. the method for claim 1 is characterized in that, for each PVC passage is provided with a mode bit, in the described step (b), after the oam cell preservation that receives, the mode bit that also upgrades its affiliated PVC passage is " cell is arranged " sign; After sending oam cell in the step (d), do not had the oam cell of this PVC passage as memory, the mode bit that also upgrades this passage is " no cell " sign.
3. the method for claim 1, it is characterized in that, the oam cell of all PVC passages uses the memory space of sharing, and this memory space is divided into the memory block of a plurality of oam cell sizes, and safeguards the pointer alignment that free memory blocks in this memory space is arranged.
4. method as claimed in claim 3 is characterized in that, in the described step (b), the pointer alignment of described free memory blocks is the fifo queue of a high bit pointer.
5. the method for claim 1, it is characterized in that, in the described step (b), when the memory space of oam cell in the random access memory does not have free memory blocks, wait for and inquire about this RAM once more whether have free space to store this oam cell with the default time cycle, up to overtime this oam cell that abandons.
6. the method for claim 1 is characterized in that, in the described step (a), is common ATM cell as this cell, deposits this cell in the fifo fifo formation according to the PVC channel number; In the described step (d), when inquiring the oam cell of this PVC passage not, whether inquiry has the common ATM cell of this PVC passage again, if having, reads the common ATM cell of this PVC passage and sends.
7. the device of a transmitting quickly operation, OAM cell OAM comprises that asynchronous transfer mode ATM cell buffer memory control module, oam cell administration module, ATM cell send control module, and the random access memory ram memory module, wherein:

Described ATM cell buffer memory control module, be used for after system receives at least one complete cell, read the header information of this cell, the permanent virtual of obtaining this cell connects PVC channel number and cell attribute information, common cell and oam cell are handled respectively, are oam cells as this cell, when the memory space of oam cell in the described RAM memory module has free memory blocks, take out a free memory blocks pointer from described oam cell administration module, this cell is saved in this memory block;

Described oam cell administration module, be used for described RAM memory module is managed for the memory space that oam cell uses, safeguard the pointer of free memory blocks, control the read-write of RAM memory module, and set up the incidence relation of the affiliated PVC passage of this oam cell and its pointer;

Described RAM memory module is used to store oam cell;

Described ATM cell sends control module, is used for when sending time slots arrives, and obtains the PVC channel number that need send cell at this time slot; When inquiring the oam cell of this PVC passage, read oam cell and send according to the pointer of this PVC passage association.
8. device as claimed in claim 7, it is characterized in that, also comprise common ATM cell administration module and memory, described common ATM cell administration module is used for described memory is invented a plurality of fifo queues, manage the state of described formation, provide Query Information for described ATM cell buffer memory control module and described ATM cell send control module; Described memory is used for the common ATM cell of buffer memory.
9. device as claimed in claim 7 is characterized in that, described oam cell administration module comprises cell pointer management module, RAM block controller and status register, wherein:

Described cell pointer management module is used to safeguard a fifo queue of depositing the RAM memory module for the free memory blocks high address of oam cell use;

Described RAM block controller is used to control the read-write of RAM memory module, and produces the low address of described RAM memory module automatically;

Described status register is used to deposit the oam cell state of each PVC passage and the pointer of oam cell.
10. device as claimed in claim 7 is characterized in that, described ATM cell sends control module and comprises that also time slot generation module, time slot packing module and cell send control module, wherein:

Described time slot generation module is used to system constantly to generate the standard sequence of time slots, and each time slot allows to send an ATM cell;

Described time slot packing module is used for the bandwidth for each PVC channel arrangement according to system, and which bar PVC passage certain time slot that determines described time slot generation module to generate should be sent by;

Described cell sends control module, is used for the PVC passage according to described time slot packing module decision, inquiry oam cell formation and common ATM cell formation, if oam cell is arranged, then the reading and sending oam cell is to the next stage module; Otherwise when not having oam cell, the common ATM cell of reading and sending is to the next stage module; If there is not common ATM cell, then directly finish.