CN100571195C - Multiport Ethernet switch and data transmission method - Google Patents
Multiport Ethernet switch and data transmission method Download PDFInfo
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- CN100571195C CN100571195C CN 200510036218 CN200510036218A CN100571195C CN 100571195 C CN100571195 C CN 100571195C CN 200510036218 CN200510036218 CN 200510036218 CN 200510036218 A CN200510036218 A CN 200510036218A CN 100571195 C CN100571195 C CN 100571195C
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Abstract
The invention provides a kind of multiport Ethernet switch and data transmission method, this processing unit is based on the mode of storage forwarding and shared buffer memory, it is characterized in that, this switch has professional repeating process and data access process separated structures, comprise: data path, the Frame that is used for receiving from network is not made any Business Processing and just is saved in an external memory storage, and in response to the control of control access, Frame is read, carried out sending to network after the necessary processing; And the control access, adopt multi-stage pipeline arrangement, be used for the data frame control information is handled, control the process of transmitting of described data path to Frame.
Description
Technical field
The present invention relates to a kind of Ethernet switch and data transmission method, relate in particular to a kind of multiport Ethernet switch and data transmission method of transmitting with the storage isolating construction that have.
Background technology
Two layers or more the message that the function of Ethernet switching chip provides between a plurality of ethernet ports is transmitted, if two layers of forwarding, then the behavior of transmitting should be implemented in strict accordance with the mode of IEEE 802.3 (agreement about ethernet local area network of international IEEE definition) protocol definition, if the forwarding more than two layers then should be implemented according to the mode of IP protocol definition.Ethernet switching chip is the core devices of ethernet switching device, has determined the performance and the function of Ethernet switch.
Ethernet exchanges most important index and is systematic function, just the ability of linear speed exchange between port.So-called linear speed exchange refers to and sends one to one between the same rate ethernet port under the message situation, and all of the port can be with the full rate frame that transmits and receive data, and losing and postponing of any Frame do not occur.The speed of Ethernet rises to 100M, 1G, 10G from 10M, requires exchange chip must promote performance synchronously to satisfy the linear speed processing requirements.
Another important indicator of Ethernet exchange is a traffic handing capacity.Different with the simple communication that early stage Ethernet only is used between computer equipment, present Ethernet requires to provide such as all Multiservice capability such as user management, service quality, safety management, flow managements, thereby requires Ethernet switching chip that the complicated service disposal ability can be provided.
Ethernet switching chip is generally based on " storage-forwarding " mode.So-called " storage-forwardings " when being meant the ethernet data frame exchange, receives Frame is complete earlier, be kept in the internal storage, after the correctness verification and transmitting processing, ability with Frame internally memory send on the Ethernet.Pass-through mode on the other side is " leading directly to ", as long as receive enough Frame headers, just begins to transmit and handles, and Frame is sent on the Ethernet, and this moment, Frame may also not receive, and was in the state of " edge joint is received the limit and sent ".The advantage that " leads directly to " mode is that forward delay is little, and problem is that wrong Frame also can be sent out, thereby less being used.
The Ethernet exchange process is usually based on " shared buffer memory " mode." shared buffer memory " refers to, and the Frame that all of the port receives is all concentrated and is saved in the common memory, and when needing to send Frame, read data frame sends and gets final product from this memory.
Summary of the invention
The objective of the invention is to a kind of multiport Ethernet switch, adopt the working method of storage forwarding and shared buffer memory, have professional repeating process and data access process separated structures, with strengthening system stability.
Wherein, this processing unit comprises:
A kind of multiport Ethernet switch adopts the working method of storing forwarding and shared buffer memory, comprising:
Data path, comprise receiving terminal first-in first-out type memory and transmitting terminal first-in first-out type memory, be used for not make any Business Processing from the Frame that network receives and be cached to external memory storage, and, through transmitting terminal first-in first-out type memory Frame is sent after handling in response to the control read data frame of control access; And
The control access is used to carry out Business Processing and controls described data path to the buffer memory of Frame with read process;
Described control access comprises:
Cache manager is used to safeguard the use of external memory storage;
The input wheel is inquired about control module, be used for the state of described receiving terminal first-in first-out type memory is carried out poll and control, spatial cache for Frame application external memory storage, the control data path stores Frame into described external memory storage, according to the memory location generation Frame control information of Frame;
Frame is transmitted and operational processor, is used to carry out Business Processing, and according to the forwarding of described Frame control information control data frame;
Output queue and scheduler are used to receive that described Frame is transmitted and the Frame control information of operational processor, and the control cache manager discharges buffer memory, and described Frame control information is sent to described output wheel inquire about control module;
The output wheel is inquired about control module, the state that is used for the described transmitting terminal first-in first-out of poll type memory, send the scheduling application to described output queue and scheduler, according to the Frame control information of dispatching out, control described data path described transmitting terminal first-in first-out type memory is read and sent to Frame from external memory storage, and submit maintenance information to cache manager.
Wherein, described control access also comprises:
Frame information first-in first-out type memory is used to store from described input wheel and inquires about the Frame control information of control module, and sends to described Frame forwarding and operational processor.
Wherein, this data path comprises:
Receiving terminal Ethernet media controller is used for from the network receiving data frames.
Receiving terminal first-in first-out type memory is used for the Frame that temporary receiving terminal Ethernet media controller receives.
Fan-in is that the multichannel that can carry out the data insertion is selected a switch according to channel module in design, the Frame of choosing is read and finished sending on the output bus after data are inserted from receiving terminal first-in first-out type memory.
The external memory interface controller is connected according to channel module with fan-out according to channel module with fan-in, is used for the process that control data deposited and read external memory storage in.
Fan-out carries out necessary modifications, insertion or deletion action according to channel module to the Frame that is about to output, then Frame is sent in the transmitting terminal first-in first-out type memory.
Transmitting terminal first-in first-out type memory is kept in from fan-out according to Frame channel module, that be about to transmission.
Transmitting terminal Ethernet media controller is connected with transmitting terminal first-in first-out type memory, and the Frame after handling is sent to network.
Frame is transmitted and operational processor is made of a plurality of Service Processing Units, forms multi-stage pipeline arrangement.
Wherein, input wheel is inquired about control module and is comprised:
Input poll module is used to receive the state information from described receiving terminal first-in first-out type memory, finishes the poll to described receiving terminal first-in first-out type memory state, selects pending port numbers.
Input state-maintenance module, Frame in the pending port that reception goes out from input poll module poll, when Frame is new data frame, input state-maintenance module is to the available external cache of cache manager application, and maintenance port data write state information, new data frame head cache control signal is outputed in the data frame head buffer memory; When Frame is not new data frame, direct examination and maintenance port data write state information, the output result of status checkout and maintenance writes the address of external cache for data, if pending port is the data postambles, then needs the postamble index signal is outputed in the data frame head buffer memory.
Data frame head buffer memory writes control module, receives the new data frame head cache control signal from described input state-maintenance module, controls described data path the data frame head is write data frame head buffer memory.
Fan-in is according to storage control module, reception is from the address information that writes external cache of described input state-maintenance module, and the Frame of controlling in the described receiving terminal first-in first-out type memory that described data path will choose writes the external memory storage output bus.
Fan-in is according to the frame control information generation module, be used to receive signal from input state-maintenance module, when receiving the data postamble, to be configured to the Frame control information for information about in the port status information, and the Frame control information that generates is outputed in the Frame information first-in first-out type memory.
Wherein, output queue and scheduler comprise:
The output queue server is used to provide the grade of service, and Frame forwarding and operational processor and data output channel are separated.The output queue server is a first-in first-out type memory on function.
Scheduler is exported a Frame according to the request that described output wheel is inquired about control module from port queue.
Wherein, output wheel is inquired about control module and is comprised:
Output poll module is used to receive the state information of described transmitting terminal first-in first-out type memory, finishes the poll to described transmitting terminal first-in first-out type memory state, selects pending port numbers.
The state output terminal maintenance module, Frame in the pending port that reception goes out from output poll module poll, the Frame transmit status of examination and maintenance port, and whether the judgment data frame has sent finishes, if having finished, the Frame transmission proposes to discharge application to cache manager, cache manager carries out releasing operation to the control information of respective cache unit, if the Frame that returns shows Frame and abandons because of certain reason has been marked as, then the state output terminal maintenance module uses the buffer unit address that is kept in the Frame control information to propose to discharge application to cache manager, and cache manager carries out releasing operation to the control information of respective cache unit.
Control module is read and revised to the output Frame, reception is from the address signal of described state output terminal maintenance module, control described fan-out according to channel module from described external memory interface controller sense data, and control described fan-out and finish modification to Frame according to channel module, amended data Be Controlled is written in the described transmitting terminal first-in first-out type memory.
A kind of data transmission method of multiport Ethernet switch is characterized in that, this data transmission method may further comprise the steps:
Step 202, poll and control are carried out to the state of the receiving terminal first-in first-out type memory of data path in the control access, spatial cache for Frame application external memory storage, the control data path stores Frame into described external memory storage, externally generates the Frame control information in the memory location in the memory according to Frame; And
Step 204, Business Processing is carried out in described control access, and according to the forwarding of Frame control information control data frame, according to described Frame control information notice external memory storage
DischargeBuffer memory; And
Step 206, described control access are controlled described data path Frame are read from external memory storage according to described Frame control information, and described data path carries out after the necessary processing it being sent to described Frame.
Wherein, step 202 may further comprise the steps:
Step 202a, receiving terminal Ethernet media controller is from the network receiving data frames, and the Frame that receives is sent in the receiving terminal first-in first-out type memory.
Step 202b, receiving terminal first-in first-out type memory carries out cutting with Frame in the temporal data frame.
Step 202c, input wheel inquire about control module the receiving terminal first-in first-out type memory of port are constantly carried out poll, and poll goes out a port that has received Frame, carries out address maintenance of Frame buffer unit and Business Processing and prepares.
Step 202d is written to the data in the receiving terminal first-in first-out type memory in the external memory storage according to channel module and external memory interface controller by fan-in.
Wherein, step 206 may further comprise the steps:
Step 206a, the output wheel is inquired about the state that the continuous poll transmitting terminal of control module first-in first-out type memory sends data, up to finding that ports having has one or more idle data block spaces.
Step 206b, whether the Frame of inspection port has sent and has finished, finish if Frame has sent,, and use the external cache address in the Frame control information that Frame is read from external memory storage then to output queue and the new Frame to be sent of scheduler application; Do not finish if Frame also sends, then use the address information in the port status that Frame is read from described external memory storage.
Step 206c, fan-out take turns under the control of inquiring about control module at output according to channel module the Frame of reading are handled, and it is write transmitting terminal first-in first-out type memory.
Step 206d, the output wheel is inquired about control module and data frame buffer element address is safeguarded transmitting terminal Ethernet media controller sends to network with Frame.
Wherein, input wheel is inquired about control module and is taken turns the process of inquiring about processing and be:
Step 402, input poll module is carried out poll to the state of the receiving terminal first-in first-out type memory of all of the port, and poll goes out certain receiving terminal first-in first-out type memory that has received a data block.
Step 406, if new data frame, to the available external cache address of cache manager application.
Step 414, receiving terminal Ethernet media controller judge whether it is the data postambles, and send this information to input state-maintenance module by the appointed information position.
Step 418, fan-in generates the Frame control information according to the frame control information generation module and it is write in the Frame information first-in first-out type memory.
The input wheel is inquired about control module and is adopted multistage poll structure, is about to port and is divided into a plurality of groups, carries out poll separately in each group, and the poll result to all groups organizes a poll again, selects each receiving terminal first-in first-out type port memory that needs processing.
Wherein, output wheel is inquired about control module and is taken turns the process of inquiring about processing and be:
Step 602, output poll module poll go out to have at least the transmitting terminal first-in first-out type memory of a freed data blocks.
Step 604, state output terminal maintenance module are judged whether the Frame of this port has sent and are finished.
Step 606 finishes if the frame of port has sent, and the state output terminal maintenance module is to output queue and the new Frame to be sent of scheduler application so.
Step 608, control module control output end data path module and transmitting terminal first-in first-out type memory are read and revised to the output Frame, data block is read from external memory storage, carry out necessary processing and write then in the transmitting terminal first-in first-out type memory.
Step 610, the frame transmit status of state output terminal maintenance module maintenance port.
Step 612, transmitting terminal first-in first-out type memory processes finishes, and takes turns next time and inquires about processing.
Repeating process separates with storing process, is beneficial to the repeating process of realizing that high-performance, high professional ability require.Repeating process is handled the complicated service handling process, uses multi-stage pipeline to realize, can not exert an influence to systematic function.Storing process uses the data of two-forty to preserve and the fetch channel structure, and the external dynamic memory that use cost is cheap can be supported high-performance, high bandwidth requirement, can not push the flexible disposal ability of repeating process.
For each Frame to be transmitted, just carry out storage operation without any forwarding processing, simplified requirement to cache management, the stability of a system has been strengthened in especially multicast caching management, has reduced chip cost.
Description of drawings
By with reference to the accompanying drawings, it is more obvious that the features and advantages of the present invention will become, wherein:
Fig. 1 is the block diagram according to multiport Ethernet switch of the present invention;
Fig. 2 is the block diagram according to the data transmission method of multiport Ethernet switch of the present invention;
Fig. 3 is the building-block of logic that input wheel according to the present invention is inquired about control module;
Fig. 4 is that input wheel according to the present invention is inquired about the flow chart that control module is taken turns the process of inquiring about processing;
Fig. 5 is the building-block of logic that output wheel according to the present invention is inquired about control module; And
Fig. 6 is that output wheel according to the present invention is inquired about the flow chart that control module is taken turns the process of inquiring about processing.
Embodiment
, should be appreciated that specific embodiment described herein only is used to explain the present invention, and be not used in qualification the present invention describing according to a particular embodiment of the invention referring now to accompanying drawing.
Fig. 1 is the block diagram according to multiport Ethernet switch of the present invention, and this processing unit is a chip.Remainder among the figure except that outside memory 130 has constituted present design, and external memory storage 130 uses the DDR SDRAM of industrial standard, and the high performance cost that reduces whole system simultaneously is being provided.High-performance Ethernet switch of the present invention is made of data path and control access.Among the figure, fine line is represented control information or service handling information, and the unit that fine line links to each other constitutes the control access, consummatory behavior control and service processing function.Heavy line is represented data message, and the unit composition data path that it links to each other is finished data and preserved and sending function.
Data path comprises receiving terminal Ethernet media controller (RxMAC) 102, receiving terminal first-in first-out type memory (RxFIFO) 104, fan-in is according to channel module 110, external memory interface controller 112, fan-out is according to channel module 114, transmitting terminal first-in first-out type memory (TxFIFO) 108, transmitting terminal Ethernet media controller (TxMAC) 106, its function is: under the control of control access, RxMAC 102 is saved in the external memory storage (DDR SDRAM) 130 from the Frame that network receives, under the control of control access, be issued on the network from TxMAC 106 Frame read and revise frame format from external memory storage 130 after.
The control access comprises that the input wheel is inquired about control module 116, Frame information first-in first-out type memory 118, Frame forwarding and operational processor 120, output queue and scheduler 122, the output wheel is inquired about control module 124, cache manager 126, its function is: control data writes the process of external memory storage 130, then the data of input are finished Business Processing and forwarding decision, after finishing the output queue scheduling, the control outgoing data is read external memory storage 130 and is sent to the process of network.
An exchange that is embodied as 4 1G ethernet ports and 24 100M ethernet ports of the present invention, all design parameters in the following specification are target with this design specification.If support the exchange of more or less quantity ethernet port, may need the partial design parameter is adjusted, adjusting parameter can not have substantial improvements to the present invention.
RxMAC102 and TxMAC106 are respectively the receiving units of MAC (Ethernet media controller) and send part, the function of MAC defines in IEEE 802.3 agreements, be the Ethernet data frame processing unit of standard, be used for receiving or send Frame from ethernet link.During practical application, also need be on MAC external ethernet physical layer chip could real and ethernet communication.For simplifying the cost of integral device, also the ethernet physical layer chip can be integrated into Ethernet switching chip inside, this only is the raising of integrated level, does not constitute substantial improvements of the present invention.During the external a plurality of ethernet port of this programme, then the chip planted agent comprises the MAC of respective numbers.
RxFIFO 104 is used for the data that temporary RxMAC 102 receives.In the present embodiment, when being saved to external memory storage 130, Frame need be cut into regular length, as 128 bytes, therefore RxFIFO 104 also finishes the cutting of Frame in temporal data, per 128 byte cuttings are one, the message of less than 128 bytes or data postamble also are divided into one, and the cutting process realizes by the mode of reading by data block.Because the data rate memory in the chip is that unit is weighed far above speed and the storage that RxMAC 102 receives data with 128 block of bytes, RxFIFO 104 only need be designed to 2 128 byte data block lengths, be no more than 3 128 byte data length at most, can support the full rate Data Receiving, need not to consider pending Frame total length.In addition, low in order to adapt to input speed, the characteristics that reading speed is high, it is different with the output bit wide that this RxFIFO 104 can be designed as the input bit wide, the bit wide that writes RxFIFO 104 as RxMAC 102 is 32bit, and the bit wide that fan-in reads according to channel module 110 is 64bit or 128bit, thereby reduces the bus bit wide of RxMAC 102 sides, reduces chip area.
The function that the input wheel is inquired about control module 116 is the situation of Data Receiving among all RxFIFO 104 of poll, be the available external cache of each Frame application, control input end data path module 110 writes Frame in the buffer memory of applying for, when each Frame is preserved when finishing, the control informations such as preservation position of data frame head and Frame are sent to by Frame information first-in first-out type memory 118 Frame is transmitted and operational processor 120 carries out Business Processing.
Fan-in is to inquire about under the control of control module 116 at the input wheel according to the function of channel module 110, the data of the RxFIFO 104 that chooses are read on the output bus that sends to external memory storage 130, if new data frame sends to this Frame in the data frame head buffer memory of related port simultaneously.In addition, this unit has data and inserts function, can insert default data before the input data are sent to external memory storage 130, is used for the uniform format operation of input data frame, makes things convenient for Business Processing.Fan-in mainly is that the multichannel that can carry out the data insertion is selected a switch according to channel module 110 in design.
Frame is transmitted and operational processor 120 is the multi-stage pipelines that are made of a plurality of Service Processing Units, is used to finish the business functions such as two layers of forwarding, IP forwarding, safe handling of Ethernet exchange needs support.Detailed Business Processing process and the present invention are irrelevant, and this paper no longer discusses.
Frame is transmitted and operational processor 120 inquires about control module 116 by Frame information first-in first-out type memory 118 with the input wheel and data frame head buffer memory is connected with the input DRP data reception process, inquiring about control module 124 by output queue and scheduler 122 and output wheel is connected with the output data transmission procedure, because the speed buffer action of output queue and scheduler 122 makes Frame transmit and operational processor 120 structurally is totally independent of the data input.In addition, Frame is transmitted and information such as operational processor 120 uses Frame header and input port can be transmitted by the determination data frame, thereby Frame is transmitted and the adjustment of the streamline of operational processor 120 can not send and inbound pacing generation restriction data.Like this, no matter how the Business Processing process changes, and guarantees the streamline full speed running as long as adjust the design of Business Processing streamline, can guarantee that chip system provides the full rate disposal ability.Equally, if ethernet port increases or port speed improves, then can improve the performance of data path and the performance of Business Processing streamline respectively, both do not constitute the relation of conditioning each other.
The function of output queue and scheduler 122 is can be sent out successively so that output to the Frame of this port for each port provides a plurality of formations.The configuration structure of output queue, congestion avoidance algorithm, scheduling output algorithm etc. are the keys of the service quality that provides of decision Ethernet switching chip, and its specific definition and processing procedure and the present invention have nothing to do, and this paper no longer discusses.
The output queue server is a first-in first-out type memory on function, and Business Processing streamline and data output procedure are isolated, and detailed formation implementation structure and the present invention are irrelevant, and this paper no longer discusses.
The function of scheduler is the application that response output wheel is inquired about 124 pairs of each ports of control module, selects Frame to be sent from a plurality of output queues of this port.In order to improve the response speed of scheduler, scheduler has used " pre-scheduling " structure.So-called " pre-scheduling ", be meant that scheduler dispatches out a Frame for all of the port in advance, when inquiring about the scheduling application of control module 124 proposition ports, the output wheel can provide scheduling result at once, when the dateout process is used this scheduling result, scheduler can be finished the scheduling of the next data of this port, so that response is next time to the scheduling application of the port.By " pre-scheduling " structure, make that output poll and queue scheduling can parallel work-flows, reduced processing speed requirement to scheduler.
The function that the output wheel is inquired about control module 124 is the state of poll TxFIFO 108, poll goes out to have at least the TxFIFO 108 of a data block free time, then to the outgoing data frame information of scheduler application port, after obtaining return information, content according to wherein external cache address sense data frame from external memory storage 130, after indication output end data path module 114 is finished last modification, be written among the TxFIFO 108.If data length to be sent surpasses a data block size, then need repeatedly this port of poll and carry out repeatedly transmit operation.
TxFIFO 108 is used for the temporary data that are about to transmission.In the present embodiment, though being the data block that is cut into regular length, Frame is kept in the external memory storage, and output procedure also is to be that unit reads among the TxFIFO 108 with the data block, but each data block is deposited continuously in TxFIFO 108,106 needs of TxMAC send continuously successively and get final product, and the cutting of data block can not produce any influence to sending.Because the data reading speed in the chip sends the speed of data far above TxMAC 106, TxFIFO 108 only need be designed to 2 128 byte data block lengths, be no more than 3 128 byte data length at most, can support the full rate data to send, need not to consider pending Frame total length, this can reduce chip area.Equally, require high in order to adapt to input speed, reading speed requires low characteristics, it is different with the output bit wide that TxFIFO 108 also can be designed as the input bit wide, as TxMAC 106 sides is 32bit, fan-out is 64bit or 128bit according to channel module 114 sides, to reduce the bus bit wide of TxMAC 106 sides, reduces chip area.
What external memory interface controller 112 received that the inputs wheel inquires about control module 116 writes the external memory storage application, the data that input data path module 110 is sent on the external memory storage input bus are written in the external memory storage 130, and receive that the output wheel inquires about control module 124 read the external memory storage application, data in the external memory storage 130 are sent to output data path module 114 by the external memory storage output bus, and each read-write operation is 1～128 byte.
Because DDR SDRAM 130 visits need operations such as precharge, activation just can carry out read-write operation, going for the high-bandwidth access ability must careful design access sequential.The external memory interface controller has used the patent algorithm to coordinate the read-write application, accessing time sequence is set, for the metadata cache process provides enough bandwidth of memory supports.Because this patent content does not influence the technical scheme that the present invention relates to, this paper is not described in detail this patent, and particular content please refer to relevant patent design documentation CN 1855880A.
The function of cache manager 126 is service data frame buffers, just safeguards the use of external memory storage 130.Present embodiment has used by 128 byte data pieces and has read and write as the unit, but method according to long data frame service data frame buffer, particular content is: is that unit divides with all external memory storages 130 by long data frame byte, as 2048 bytes, be called buffer unit, each buffer unit is represented with an address, can directly correspond to external memory address.To each Frame that newly enters, all distribute a buffer memory, no matter real data occupancy how many contents, idle bytes uses all can not for other Frames, Frame all carries buffer unit address and Frame length all the time when inter-process, that uses when Frame is exported like this that these two information just can be correct reads data in the external memory storage 130.Make in this way, cache manager only need be safeguarded each buffer unit and get final product, a Frame only can use a buffer unit, thereby reduced the data volume that cache manager need be operated, thereby with the use of coarseness at a low price the mode of external memory storage exchanged the significantly minimizing of chip internal data volume for, and simplified the chip algorithm expense.
As preceding, be that process that the unit carries out reading and writing data is inquired about in the control module 124 at input and output wheel fully and finished with 128 bytes, cache manager no longer needs to get involved, and has reduced the designing requirement of cache manager.
The process of cache management comprises that buffer memory distributes and buffer memory reclaims two processes.Buffer memory distributes and to occur in the data input process, inquire about control module 116 by the input wheel and propose to distribute application, cache manager 126 receive return after the application one not the buffer unit address of usefulness get final product.Buffer memory reclaims and occurs in formation and the data output procedure, if sending to finish or congested needs have taken place, output queue abandons Frame, proposed discharge application to cache manager 126 by output queue and scheduler 122 usefulness buffer unit addresses this moment, and releasing operation is carried out in the control information of 126 pairs of respective cache unit of cache manager.Professional repeating process can cause some Frames to be dropped because of service reason, all abandon the buffer memory release of Frame and apply for that can inquire about control module 124 by the output wheel uses the buffer unit address that is kept in the Frame control information to cache manager 126 applications, carries out releasing operation by cache manager 126.
Need to distinguish two kinds of situations of clean culture and multicast in the cache management process.Clean culture is the Frame of " singly going into singly ", and multicast is the Frame of " singly going into to have more ", and in the Frame repeating process, multicast has only a copy to leave in the external memory storage 130, then this copy is carried out repeatedly read operation in the time of need repeatedly exporting.Cache management during for unified clean culture and multicast forwarding, used the method for " Frame reference counter " in the buffer storage managing algorithm, be counter of each data frame unit address setting, when new data frame is carried out the buffer memory application, dispose a peaked counter for the buffer unit that distributes earlier, finish the operation of joining the team of output queue when Service Processing Unit after, promptly can know the actual copy umber of each Frame, clean culture is a, multicast is a or many parts, cache manager 126 duplicates the counter of status update buffer unit according to the Frame of output queue and scheduler 112 transmissions, the quantity of duplicating with accurate reflection Frame, when Frame when data output channel sends, Frame of every transmission just carries out reducing to the counter of respective cache unit, have only when being kept to zero with the counter of data frame unit, the all-multicast Frame of just representing this unit all is sent out and finishes, and this buffer unit can be recovered and be used for new data frame.
Need to prove, using which kind of buffer memory management method is not key technology of the present invention, any method of buffer memory distribution and reclaim mechanism that can provide can support core scheme of the present invention, and more than being elaborated only is in order to make elaboration of the present invention more clear and complete.
For the Frame of each input, at first receive and be saved among the RxFIFO 104 by RxMAC 102.The RxFIFO 104 that the input wheel is inquired about control module 116 continuous each port of poll receives the state of data, has received a full block of data as long as find ports having, then carries out the input-buffer operation.The input-buffer operation at first will be to cache manager 126 application buffer units, external memory address just, by the external memory storage input bus data among the RxFIFO 104 are written in the external memory storage 130 according to channel module 110 and external memory interface controller 112 by fan-in behind the address acquisition, for the Frame that surpasses a data block length, the later data block of data frame head no longer needs to apply for new storage address, only needs to inquire about control module 116 by the input wheel and carries out address arithmetic automatically and can obtain the exterior storage address.
To each Frame, all the information of data frame head with certain byte length to be kept in the data frame head buffer memory that is provided with into every port, all preserve the back that finishes together with Frame and inquire about the control information that control module 116 provides by the input wheel, transfer to Frame forwarding and operational processor and carry out Frame forwarding and Business Processing, revise control information through the output port and the Frame that can obtain Frame after the Business Processing.All these information are formed the output data frame control information, comprise buffer unit address, Frame length, Frame output port, the instruction of Frame output modifications etc., enter output queue as a Frame controlling packet, wait for sending from output port.Unicast data frames only is admitted to an output port queue, and multicast data frame can be admitted to one or more output port queues.The statistical information that Frame is sent into output port queue sends to cache manager 126 by output queue and scheduler 122, safeguards so that carry out the buffer unit usage count.
At outlet side, the output wheel is inquired about control module 124 continuous poll TxFIFO 108 and is sent the state of data, as long as find that ports having has one or more idle data block spaces, just sends the scheduling application to output queue and scheduler 122.If data to be sent are arranged in the output queue of output port correspondence, output queue and scheduler 122 will return its Frame control information, the output wheel is inquired about 124 pairs of these control informations of control module and is resolved, with memory address information to outside memory interface controller send read the application, with Frame length information Control read procedure repeatedly, carrying out Frame with output modifications commands for controlling fan-out according to channel module 114 revises, can finish data and read and send to TxFIFO108 according to channel module 114, and finish the process that necessary Frame is revised through external memory storage output bus and fan-out from external memory storage 130.Whenever finish the transmission of a Frame, the output wheel is inquired about control module 124 and is all sent a release application to cache manager 126, if from scheduler be the Frame that need directly abandon, then do not carry out any output function, directly send one and discharge application to cache manager.
The data that send among the TxFIFO 108 send to network by TxMAC 106, promptly finish the forwarding of Frame.
Fig. 2 is the block diagram according to the operation method of multiport Ethernet switch of the present invention.The operation method of this multiport Ethernet switching chip is to adopt the mode of storage forwarding and shared buffer memory to carry out, and may further comprise the steps:
Step 202, control access control data path will just be stored in the external memory storage 130 without any Business Processing from the Frame that network receives.
Step 204, control access adopt the multi-stage pipeline mode that the data frame control information is handled.
Step 206, the control access is according to the result of Business Processing streamline to Frame, and the control data path is read the Frame that is stored in the external memory storage 130, and it is carried out sending to network after the necessary modifications.
Wherein, step 202 may further comprise the steps:
Step 202a, receiving terminal Ethernet media controller 102 is from the network receiving data frames, and the Frame that receives is sent in the receiving terminal first-in first-out type memory 104.
Step 202b, receiving terminal first-in first-out type memory 104 carries out cutting with Frame in the temporal data frame.
Step 202c, the receiving terminal first-in first-out type memory 104 that the input wheel is inquired about 116 pairs of ports of control module constantly carries out poll, and poll goes out a port that has received Frame, carries out address maintenance of Frame buffer unit and Business Processing and prepares.
Step 202d is written to the data in the receiving terminal first-in first-out type memory 104 in the external memory storage 130 according to channel module 110 and external memory interface controller 112 by fan-in.
Wherein, step 206 may further comprise the steps:
Step 206a, output wheel inquire about the state that control module 124 continuous poll transmitting terminal first-in first-out type memories 108 send data, up to finding that ports having has one or more idle data block spaces.
Step 206b, whether the Frame of checking this port has sent and has finished, finish if Frame has sent,, and use the external cache address in the Frame control information that Frame is read from external memory storage 130 then to output queue and the new Frame to be sent of scheduler 122 applications; Do not finish if Frame also sends, then use the address information in the port status that Frame is read from described external memory storage.
Step 206c, fan-out take turns under the control of inquiring about control module 124 at output according to channel module 114 Frame of reading are made amendment, and it is write transmitting terminal first-in first-out type memory 108.
Step 206d, output wheel inquire about 124 pairs of data frame buffers of control module element address and safeguard, transmitting terminal Ethernet media controller 106 sends to network with Frame.
Fig. 3 is the building-block of logic that input wheel according to the present invention is inquired about control module.Wherein, input wheel is inquired about control module and is comprised:
Input poll module 302 is used to receive the state information from described receiving terminal first-in first-out type memory 104, finishes the poll to described receiving terminal first-in first-out type memory state, selects pending port.
Input state-maintenance module 304, reception is from the pending port of described input poll module 302, when being new frame in the pending port to described cache manager 126 available external cache of application and maintenance port data write state information, direct examination and maintenance port data write state information when not being new frame, the output result of status checkout and maintenance writes the address of external cache for data, if in the pending port be new frame, need the new frame head cache control signal of output, need export the postamble index signal if pending port is a postamble.
Data frame head buffer memory writes control module 306, receives the new frame head cache control signal from described input state-maintenance module 304, controls described data path the data frame head is write data frame head buffer memory 128.
Fan-in is according to storage control module 308, reception is from the address information that writes external cache of described input state-maintenance module 304, and the Frame of controlling in the described receiving terminal first-in first-out type memory 104 that described data path will choose writes the external memory storage output bus; And
Fan-in is according to frame control information generation module 310, after the postamble index signal of reception from described input state-maintenance module 304, to be configured to the Frame control information for information about in the port status information, output in the described Frame information first-in first-out type memory 118.
Fig. 4 is the course of work flow chart that input wheel according to the present invention is inquired about control module.The course of work that the input wheel is inquired about control module may further comprise the steps:
Step 402, the state of the receiving terminal first-in first-out type memory 104 of 302 pairs of all of the ports of input poll module carries out poll, and poll goes out certain receiving terminal first-in first-out type memory 104 that has received a data block.
Step 406, if new data frame, to the available external cache address of cache manager 126 applications.
Step 414, receiving terminal Ethernet media controller 102 judge whether it is the data postambles, and send this information to input state-maintenance module by the appointed information position.
Step 418, fan-in generates the Frame control information according to frame control information generation module 310 and it is write in the Frame information first-in first-out type memory 118.
Step 420,104 processing of receiving terminal first-in first-out type memory finish, and take turns next time and inquire about processing.
Write in the process of external cache in data, the input wheel is inquired about control module 116 and is read instruction to RxFIFO transmission to be operated, instruction fan-in receives the output of this RxFIFO 104 according to channel module 110, write application to the external memory interface transmission, can finish data and preserve process from the data that RxFIFO 104 read and write external memory storage 130.
If the input port negligible amounts, RxFIFO quantity is few, and the input wheel is inquired about control module and can be adopted single-stage poll structure, promptly all checks the state of all of the port RxFIFO at every turn, selects the port that receives full block of data, carries out relevant the processing then.If input port quantity is more, RxFIFO quantity is big, input data polling and control module can adopt multistage poll structure, be about to port and be divided into a plurality of groups, carry out poll separately in each group, poll result to all groups organizes a poll again, selects each RxFIFO port that needs processing.The purpose that adopts multistage poll structure is the fast as far as possible RxFIFO that finds needs to handle from all RxFIFO rapidly, RxFIFO quantity is a lot of if only adopt single-stage poll structure, directly therefrom finds out pending RxFIFO and need consume chip area and long operation time.
Fig. 5 is the building-block of logic that output wheel according to the present invention is inquired about control module.Wherein, output wheel is inquired about control module and is comprised:
State output terminal maintenance module 504, reception is from the pending port of described output poll module, pending port then proposes the Frame application to described output queue and scheduler 122 if finished the transmission of a Frame, described output queue and scheduler 122 return the Frame information of dispatching out and give described state output terminal maintenance module in order to the maintenance port send state information, the Frame of pending port is not if send the directly Frame transmit status of examination and maintenance port that finishes then, the output result of status checkout and maintenance is the address that is used for from the external cache reading of data, whether status checkout and safeguard also is used for the judgment data frame and has sent and finish, described state output terminal maintenance module 504 uses the buffer unit address that is kept in the Frame control information to propose to discharge application to described cache manager 126 if the Frame transmission finishes, releasing operation is carried out in the control information of 126 pairs of respective cache unit of cache manager, if the Frame that aforementioned output queue and scheduler 122 return shows Frame and abandons because of certain reason has been marked as, then described state output terminal maintenance module 504 uses the buffer unit address that is kept in the Frame control information to propose to discharge application to described cache manager 126, and releasing operation is carried out in the control information of 126 pairs of respective cache unit of cache manager.
Fig. 6 is the course of work flow chart that output wheel according to the present invention is inquired about control module.The course of work that the output wheel is inquired about control module may further comprise the steps:
Step 602, output poll module 502 polls go out to have at least the transmitting terminal first-in first-out type memory 108 of a freed data blocks.
Step 604, state output terminal maintenance module 504 are judged whether the Frame of this port has sent and are finished.
Step 606 finishes if the frame of port has sent, and the state output terminal maintenance module is to output queue and the new Frame to be sent of scheduler 122 applications so.
Step 608, control module 506 control output end data path modules and transmitting terminal first-in first-out type memory 108 are read and revised to the output Frame, data block is read, revised from external memory storage 130, and write in the transmitting terminal first-in first-out type memory 108.
Step 610, the frame transmit status of state output terminal maintenance module 504 maintenance ports.
Step 612,108 processing of transmitting terminal first-in first-out type memory finish, and take turns next time and inquire about processing.
Read in the external cache process in data, the output wheel is inquired about control module 124 and is read application to the external memory interface transmission, indication TxFIFO 108 receives the input of this fan-out according to channel module 114, send write command to TxFIFO to be operated 108, can finish data read and write TxFIFO 108 from external memory storage 130 data preservation process.In addition, in the process of carrying out aforesaid operations, the output wheel is inquired about control module 124 can send the data modification instruction according to channel module 114 to fan-out, to finish sending the modification of Frame.
To inquire about control module similar with input wheel, and the output wheel is inquired about control module and can be adopted single-stage poll structure, also can adopt multistage poll structure to improve poll speed and to reduce chip area consumption.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (16)
1. a multiport Ethernet switch adopts the working method of storing forwarding and shared buffer memory, it is characterized in that, comprising:
Data path, comprise receiving terminal first-in first-out type memory and transmitting terminal first-in first-out type memory, be used for not make any Business Processing from the Frame that network receives and be cached to external memory storage, and, through transmitting terminal first-in first-out type memory Frame is sent after handling in response to the control read data frame of control access; And
The control access is used to carry out Business Processing and controls described data path to the buffer memory of Frame with read process;
Described control access comprises:
Cache manager is used to safeguard the use of external memory storage;
The input wheel is inquired about control module, be used for the state of described receiving terminal first-in first-out type memory is carried out poll and control, spatial cache for Frame application external memory storage, the control data path stores Frame into described external memory storage, according to the memory location generation Frame control information of Frame;
Frame is transmitted and operational processor, is used to carry out Business Processing, and according to the forwarding of described Frame control information control data frame;
Output queue and scheduler are used to receive that described Frame is transmitted and the Frame control information of operational processor, and the control cache manager discharges buffer memory, and described Frame control information is sent to described output wheel inquire about control module;
The output wheel is inquired about control module, the state that is used for the described transmitting terminal first-in first-out of poll type memory, send the scheduling application to described output queue and scheduler, according to the Frame control information of dispatching out, control described data path described transmitting terminal first-in first-out type memory is read and sent to Frame from external memory storage, and submit maintenance information to cache manager.
2. multiport Ethernet switch according to claim 1 is characterized in that described control access also comprises:
Frame information first-in first-out type memory is used to store from described input wheel and inquires about the Frame control information of control module, and sends to described Frame forwarding and operational processor.
3. multiport Ethernet switch according to claim 1 and 2 is characterized in that described data path comprises:
Receiving terminal Ethernet media controller is used for from the network receiving data frames;
Receiving terminal first-in first-out type memory is used for the Frame that temporary described receiving terminal Ethernet media controller receives;
Fan-in is according to channel module, and the Frame that is used for choosing is read and finished from described receiving terminal first-in first-out type memory and sends to the external memory storage output bus after data are inserted;
The external memory interface controller is connected according to channel module with fan-out according to channel module with described fan-in, is used for the process that control data deposited and read external memory storage in;
Fan-out carries out necessary modifications, insertion or deletion action according to channel module to the Frame that is about to output, then Frame is sent;
Transmitting terminal first-in first-out type memory is used for keeping in from described fan-out according to Frame channel module, that be about to transmission; And
Transmitting terminal Ethernet media controller is connected with described transmitting terminal first-in first-out type memory, is used for the Frame after handling is sent to network.
4. multiport Ethernet switch according to claim 3 is characterized in that, described fan-in is that multichannel is selected a switch according to channel module in design.
5. multiport Ethernet switch according to claim 1 is characterized in that, described Frame is transmitted and operational processor is made of a plurality of Service Processing Units, forms multi-stage pipeline arrangement.
6. multiport Ethernet switch according to claim 2 is characterized in that, described input wheel is inquired about control module and comprised:
Input poll module is used to receive the state information from described receiving terminal first-in first-out type memory, finishes the poll to described receiving terminal first-in first-out type memory state, selects pending port numbers;
Input state-maintenance module, the Frame of the pending port that reception goes out from described input poll module poll, when described Frame is new data frame, described input state-maintenance module is to the available external cache of described cache manager application, and maintenance port data write state information, new data frame head cache control signal is outputed in the data frame head buffer memory; When described Frame is not new data frame, direct examination and maintenance port data write state information, the output result of status checkout and maintenance writes the address of external cache for data, if the data postamble then outputs to the postamble index signal in the described data frame head buffer memory;
Data frame head buffer memory writes control module, receives the new data frame head cache control signal from described input state-maintenance module, controls described data path the data frame head is write data frame head buffer memory;
Fan-in is according to storage control module, reception is from the address information that writes external cache of described input state-maintenance module, and the Frame of controlling in the described receiving terminal first-in first-out type memory that described data path will choose writes the external memory storage output bus; And
Fan-in is according to the frame control information generation module, after the postamble index signal of reception from described input state-maintenance module, to be configured to the Frame control information for information about in the port status information, output in the described Frame information first-in first-out type memory.
7. multiport Ethernet switch according to claim 1 is characterized in that described output queue and scheduler comprise:
The output queue server is used to provide the grade of service, and Frame forwarding and operational processor and data output channel are separated; And
Scheduler is exported a Frame according to the request that described output wheel is inquired about control module from port queue.
8. multiport Ethernet switch according to claim 7 is characterized in that, described output queue server is first-in first-out type memory on function.
9. multiport Ethernet switch according to claim 7, it is characterized in that described scheduler adopts the pre-scheduling structure, goes out a Frame for each Port Scheduling in advance, when the output wheel is inquired about the scheduling application of control module proposition port, can provide scheduling result at once.
10. multiport Ethernet switch according to claim 3 is characterized in that described output wheel inquires about control module and comprise:
Output poll module is used to receive the state information of described transmitting terminal first-in first-out type memory, finishes the poll to described transmitting terminal first-in first-out type memory state, selects pending port numbers;
The state output terminal maintenance module, reception is from the Frame of the pending port of described output poll module poll, the Frame transmit status of examination and maintenance port, and whether the judgment data frame has sent finishes, if finishing, the Frame transmission proposes to discharge application to described cache manager, cache manager carries out releasing operation to the control information of respective cache unit, if the Frame that returns shows Frame and abandons because of certain reason has been marked as, then described state output terminal maintenance module uses the buffer unit address that is kept in the Frame control information to propose to discharge application to described cache manager, and cache manager carries out releasing operation to the control information of respective cache unit; And
Control module is read and revised to the output Frame, reception is from the address signal of described state output terminal maintenance module, control described fan-out according to channel module from described external memory interface controller sense data, and control described fan-out and finish processing to Frame according to channel module, the data after the processing are written in the described transmitting terminal first-in first-out type memory.
11. the data transmission method of a multiport Ethernet switch is characterized in that, said method comprising the steps of:
Step 202, poll and control are carried out to the state of the receiving terminal first-in first-out type memory of data path in the control access, spatial cache for Frame application external memory storage, the control data path stores Frame into described external memory storage, externally generates the Frame control information in the memory location in the memory according to Frame; And
Step 204, Business Processing is carried out in described control access, and according to the forwarding of Frame control information control data frame, discharges buffer memory according to described Frame control information notice external memory storage; And
Step 206, described control access are controlled described data path Frame are read from external memory storage according to described Frame control information, and described data path carries out after the necessary processing it being sent to described Frame.
12. data transmission method according to claim 11 is characterized in that, described step 202 may further comprise the steps:
Step 202a, receiving terminal Ethernet media controller is from the network receiving data frames, and the Frame that receives is sent in the described receiving terminal first-in first-out type memory;
Step 202b, described receiving terminal first-in first-out type memory carries out cutting with Frame in the temporal data frame;
Step 202c, input wheel inquire about control module the receiving terminal first-in first-out type memory of port are carried out poll, and poll goes out to receive the port of Frame, carries out address maintenance of Frame buffer unit and Business Processing and prepares, and generates the Frame control information; And
Step 202d is written to the Frame in the described receiving terminal first-in first-out type memory in the external memory storage according to channel module and external memory interface controller by fan-in.
13. data transmission method according to claim 11 is characterized in that, described step 206 may further comprise the steps:
Step 206a, the output wheel is inquired about the state that the continuous poll transmitting terminal of control module first-in first-out type memory sends data, up to finding that ports having has one or more idle data block spaces;
Step 206b, whether the Frame of checking described port has sent and has finished, finish if Frame has sent,, and use the external cache address in the Frame control information that new Frame is read from external memory storage then to output queue and the new Frame to be sent of scheduler application; Do not finish if described Frame also sends, then use the address information in the port status that described Frame is read from described external memory storage;
Step 206c, fan-out take turns under the control of inquiring about control module at described output according to channel module the Frame of reading are made amendment, and it is write described transmitting terminal first-in first-out type memory;
Step 206d, described output wheel is inquired about control module and data frame buffer element address is safeguarded transmitting terminal Ethernet media controller sends to network with Frame.
14. data transmission method according to claim 12 is characterized in that, described input wheel is inquired about control module and is taken turns the process of inquiring about processing and be:
Step 402, input poll module is carried out poll to the state of the receiving terminal first-in first-out type memory of all of the port, and poll goes out certain receiving terminal first-in first-out type memory that has received a data block;
Step 404, input state-maintenance module judge whether the Frame that receives is new data frame;
Step 406, if new data frame, to the available external cache address of cache manager application;
Step 408, if new data frame, data frame head buffer memory writes control module one control signal is sent to data frame head buffer memory, and the data frame head of new data frame is write in the described data frame head buffer memory;
Step 410, fan-in controls described receiving terminal first-in first-out type memory according to storage control module and described fan-in writes the data block that receives in the external memory storage according to channel module and described external memory interface controller;
Step 412, the writing information and the state of described input state-maintenance module maintenance port data;
Step 414, receiving terminal Ethernet media controller judge whether it is the data postambles, and send this information to described input state-maintenance module by the appointed information position;
Step 416, if the data postamble, described input state-maintenance module is adjusted port information;
Step 418, fan-in generates the Frame control information according to the frame control information generation module and it is write in the Frame information first-in first-out type memory; And
Step 420, described receiving terminal first-in first-out type memory processes finishes, and takes turns next time and inquires about processing.
15. data transmission method according to claim 12, described input wheel is inquired about control module and is adopted multistage poll structure, be about to port and be divided into a plurality of groups, carry out poll separately in each group, poll result to all groups organizes a poll again, selects each receiving terminal first-in first-out type port memory of need handling number.
16. data transmission method according to claim 13 is characterized in that, described output wheel is inquired about control module and is taken turns the process of inquiring about processing and be:
Step 602, output poll module poll go out to have at least the transmitting terminal first-in first-out type memory of a freed data blocks;
Step 604, state output terminal maintenance module are judged whether the Frame of this port has sent and are finished;
Step 606 finishes if the Frame of described port has sent, and so described state output terminal maintenance module is to output queue and the new Frame to be sent of scheduler application;
Step 608, output Frame are read and are revised control module and control described fan-out according to channel module and described transmitting terminal first-in first-out type memory, data block are read from external memory storage, are revised, and write in the transmitting terminal first-in first-out type memory;
Step 610, the frame transmit status of described state output terminal maintenance module maintenance port; And
Step 612, described transmitting terminal first-in first-out type memory processes finishes, and takes turns next time and inquires about processing.
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| CN101136817B (en) * | 2006-09-20 | 2011-06-22 | 中兴通讯股份有限公司 | Data transmission control method of ethernet chip |
| CN101656659B (en) * | 2008-08-19 | 2012-05-23 | 中兴通讯股份有限公司 | Method for caching mixed service flow and method and device for storing and forwarding mixed service flow |
| CN101414973B (en) * | 2008-11-25 | 2011-08-17 | 中国人民解放军信息工程大学 | Method and apparatus for transmitting data packet |
| CN101527686B (en) * | 2009-04-07 | 2011-08-24 | 华为技术有限公司 | Method of data exchange and equipment |
| CN102065011A (en) * | 2010-12-17 | 2011-05-18 | 天津曙光计算机产业有限公司 | Method for converging data streams of multi-port network card |
| CN102104548B (en) * | 2011-03-02 | 2015-06-10 | 中兴通讯股份有限公司 | Method and device for receiving and processing data packets |
| CN103209141A (en) * | 2012-01-17 | 2013-07-17 | 中兴通讯股份有限公司 | Method for processing data messages with switching chip and switching chip |
| CN102821045B (en) * | 2012-08-03 | 2015-07-22 | 中兴通讯股份有限公司 | Method and device for copying multicast message |
| CN103780506B (en) * | 2012-10-26 | 2017-08-08 | 中兴通讯股份有限公司 | A kind of data buffering system and method for ethernet device |
| CN104486258B (en) * | 2014-12-09 | 2017-09-26 | 中国航空工业集团公司第六三一研究所 | A kind of switched circuit based on interchange channel |
| CN108614667B (en) * | 2016-12-12 | 2021-03-26 | 中国航空工业集团公司西安航空计算技术研究所 | Configurable broadcast ELS data frame power-on automatic loading circuit and method |
| CN111930083B (en) * | 2020-08-05 | 2021-08-27 | 智昌科技集团股份有限公司 | Method and device for collecting industrial equipment data |
| CN112434479B (en) * | 2020-11-23 | 2023-09-08 | 北京中电华大电子设计有限责任公司 | High-speed algorithm interface circuit structure and control method thereof |
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